-- bch_seq_interrupt.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre-André Galmes -- Test de seq_interrupt. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.isa_const.all; use work.nono_const.all; entity bch_seq_interrupt is end bch_seq_interrupt; architecture sim1 of bch_seq_interrupt is component seq_interrupt port ( rst : in std_logic; clk : in std_logic; irq : in std_logic; -- On a une interruption. rst_bas : out std_logic; -- raz des bascules. rst_irq : out std_logic; -- raz de l'IRQ. en_reg : out std_logic; -- Chip select cs0 : in std_logic; cs1 : in std_logic; cs2 : in std_logic ); end component; -- définiton des signaux signal rst : std_logic; signal clk : std_logic := '0'; signal irq : std_logic; signal rst_bas : std_logic; signal rst_irq : std_logic; signal en_reg : std_logic; signal cs0 : std_logic; signal cs1 : std_logic; signal cs2 : std_logic; begin U1 : seq_interrupt port map ( rst, clk, irq, rst_bas, rst_irq, en_reg, cs0, cs1, cs2); rst <= '1', '0' after CK_PERIOD/4; clk <= not clk after CK_PERIOD/2; irq <= '0', '1' after 2*CK_PERIOD; cs0 <= '0', '1' after 3*CK_PERIOD, '0' after 4*CK_PERIOD; cs1 <= '0', '1' after 4*CK_PERIOD, '0' after 5*CK_PERIOD; cs2 <= '0', '1' after 5*CK_PERIOD, '0' after 6*CK_PERIOD; end sim1; configuration cf1_bch_seq_interrupt of bch_seq_interrupt is for sim1 for all : seq_interrupt use entity work.seq_interrupt(RTL); end for; end for; end cf1_bch_seq_interrupt;