info x 61 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  radix x 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpio term mark 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.nono_const.all;  var add 2 0 0 226 16 0 257 200 100 100 10 10 0 0 0 0 clk_iInstd_logicDUAL_EDGEclk_i var add 1 0 0 98 15 0 257 100 50 50 10 10 0 0 0 0 rstInstd_logicDUAL_EDGEclk_i var add 4 0 0 98 18 0 257 100 50 50 10 10 0 0 0 0 rwInstd_logicDUAL_EDGEclk_i var add 9 0 0 98 24 0 257 100 50 50 10 10 0 0 0 0 cs_reg_directionInstd_logicDUAL_EDGEclk_i var add 10 0 0 98 25 0 257 100 50 50 10 10 0 0 0 0 cs_reg_it_maskInstd_logicDUAL_EDGEclk_i var add 8 0 0 98 23 0 257 100 50 50 10 10 0 0 0 0 cs_reg_dataInstd_logicDUAL_EDGEclk_i var add 11 0 0 98 26 0 257 100 50 50 10 10 0 0 0 0 cs_read_outputInstd_logicDUAL_EDGEclk_i var add 6 7 0 100 20 0 257 100 50 50 10 10 0 0 0 0 bus_dataInOutstd_logic_vectorDUAL_EDGEclk_i var add 7 7 0 100 21 0 257 100 50 50 10 10 0 0 0 0 io_outputInOutstd_logic_vectorDUAL_EDGEclk_i var add 3 0 0 226 17 0 257 100 50 50 10 10 0 0 0 0 clk_mInstd_logicRISING_EDGEclk_m var add 5 0 0 98 19 0 257 100 50 50 10 10 0 0 0 0 interruptOutstd_logicRISING_EDGEclk_m vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  npos xxx 139 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  cell fill 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 cell fill 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 3 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 cell fill 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 4 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 cell fill 4 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 4 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 cell fill 4 56 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 5 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 cell fill 5 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 5 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 cell fill 5 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 6 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 cell fill 6 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 6 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 cell fill 6 72 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 7 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 cell fill 7 88 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cell fill 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000000 cell fill 8 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000111 cell fill 8 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11111000 cell fill 8 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001 cell fill 8 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZZZZZZZZ cell fill 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00001ZZZ cell fill 9 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00100ZZZ time info 50 50 10 10 100 100 1 0 0 0 0 0 0 0 0 0 ns font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman src mod 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\gpio\gpio.vhd utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  cellenab on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  grid on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  com add 1 0 10 461 13 0 -79 0 0 0 0 0 0 0 0 0 Waveform created by HDL Bencher 6.1i Source = f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\gpio\gpio.vhd Wed Mar 17 16:59:37 2004 type info 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clkBITDOWNTO opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  NumClocks x 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  clock_1 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk_i clock_2 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk_m Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.50000000000002