# Xilinx CORE Generator 6.1.03i # Username = Administrateur # COREGenPath = D:\xilinx\coregen # ProjectPath = D:\vhdl\robot\carte_fpga\src\fpga # ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\fpga # OverwriteFiles = true # Core name: sfifo # Number of Primitives in design: 87 # Number of CLBs used in design cannot be determined when there is no RPMed logic # Number of Slices used in design cannot be determined when there is no RPMed logic # Number of LUT sites used in design: 43 # Number of LUTs used in design: 35 # Number of REG used in design: 22 # Number of SRL16s used in design: 8 # Number of Distributed RAM primitives used in design: 0 # Number of Block Memories used in design: 0 # Number of Dedicated Multipliers used in design: 0 # Number of HU_SETs used: 0 # SET BusFormat = BusFormatAngleBracketNotRipped SET XilinxFamily = Spartan2 SET OutputOption = OutputProducts SET FlowVendor = Foundation_iSE SET FormalVerification = None SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0 CSET data_width = 8 CSET read_error_sense = Active_Low CSET read_error_flag = true CSET write_acknowledge_flag = true CSET write_error_flag = true CSET data_count = true CSET memory_type = Distributed_Memory CSET read_acknowledge_sense = Active_Low CSET component_name = sfifo CSET fifo_depth = 16 CSET read_acknowledge_flag = true CSET data_count_width = 2 CSET write_error_sense = Active_Low CSET write_acknowledge_sense = Active_Low GENERATE