-- Xilinx Vhdl netlist produced by netgen application (version G.26) -- Command : -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim fpga.ngd fpga_translate.vhd -- Input file : fpga.ngd -- Output file : fpga_translate.vhd -- Design name : fpga -- # of Entities : 1 -- Xilinx : D:/xilinx -- Device : 2s200pq208-6 -- This vhdl netlist is a simulation model and uses simulation -- primitives which may not represent the true implementation of the -- device, however the netlist is functionally correct and should not -- be modified. This file cannot be synthesized and should only be used -- with supported simulation tools. library IEEE; use IEEE.STD_LOGIC_1164.ALL; library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity fpga is port ( rst : in STD_LOGIC := 'X'; rxin1 : in STD_LOGIC := 'X'; clk_speed : in STD_LOGIC := 'X'; AEN : in STD_LOGIC := 'X'; IOR : in STD_LOGIC := 'X'; IOW : in STD_LOGIC := 'X'; clk_ref : in STD_LOGIC := 'X'; irq : out STD_LOGIC; irqrxERR : out STD_LOGIC; irqrxRX : out STD_LOGIC; irqtx : out STD_LOGIC; txout1 : out STD_LOGIC; irqrxFIFO : out STD_LOGIC; bus_adr : in STD_LOGIC_VECTOR ( 23 downto 0 ); bus_data : inout STD_LOGIC_VECTOR ( 7 downto 0 ) ); end fpga; architecture Structure of fpga is signal bus_clk : STD_LOGIC; signal irqrxERR_OBUF : STD_LOGIC; signal irqrxRX_OBUF : STD_LOGIC; signal rst_BUFGP : STD_LOGIC; signal rxin1_IBUF : STD_LOGIC; signal bus_adr_1_IBUF : STD_LOGIC; signal clk_speed_BUFGP : STD_LOGIC; signal AEN_IBUF : STD_LOGIC; signal irqtx_OBUF : STD_LOGIC; signal Inst_txserie1_TX1_TX : STD_LOGIC; signal irqrxFIFO_OBUF : STD_LOGIC; signal IOR_IBUF : STD_LOGIC; signal IOW_IBUF : STD_LOGIC; signal clk_ref_BUFGP : STD_LOGIC; signal bus_adr_0_IBUF : STD_LOGIC; signal rw : STD_LOGIC; signal Inst_txserie1_TX1_n0026 : STD_LOGIC; signal Inst_txserie1_TX1_n0032 : STD_LOGIC; signal Inst_txserie1_TX1_n0027 : STD_LOGIC; signal Inst_txserie1_TX1_n0033 : STD_LOGIC; signal Inst_txserie1_TX1_n0034 : STD_LOGIC; signal bus_adr_15_IBUF : STD_LOGIC; signal bus_adr_14_IBUF : STD_LOGIC; signal bus_adr_13_IBUF : STD_LOGIC; signal bus_adr_12_IBUF : STD_LOGIC; signal bus_adr_11_IBUF : STD_LOGIC; signal bus_adr_10_IBUF : STD_LOGIC; signal bus_adr_9_IBUF : STD_LOGIC; signal bus_adr_8_IBUF : STD_LOGIC; signal bus_adr_7_IBUF : STD_LOGIC; signal bus_adr_6_IBUF : STD_LOGIC; signal bus_adr_5_IBUF : STD_LOGIC; signal bus_adr_4_IBUF : STD_LOGIC; signal bus_adr_3_IBUF : STD_LOGIC; signal bus_adr_2_IBUF : STD_LOGIC; signal Inst_rxserie1_RCONF_n0007 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_write_FFd2 : STD_LOGIC; signal Inst_rxserie1_RCONF_I1_N1528 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_write_FFd1 : STD_LOGIC; signal Inst_txserie1_FIFO1_state_write_FFd1 : STD_LOGIC; signal Inst_rxserie1_state_rx_read_FFd3_In : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_read_FFd1_In : STD_LOGIC; signal bus_data_6_IOBUF : STD_LOGIC; signal Inst_rxserie1_state_rx_read_FFd2 : STD_LOGIC; signal Inst_rxserie1_RC1_RXDATARDY : STD_LOGIC; signal bus_data_3_IOBUF : STD_LOGIC; signal N6239 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_ckout : STD_LOGIC; signal Inst_rxserie1_geneck : STD_LOGIC; signal Inst_rxserie1_rxread : STD_LOGIC; signal Inst_txserie1_FIFO1_state_read_FFd3_In : STD_LOGIC; signal Inst_rxserie1_RC1_OVERRUN : STD_LOGIC; signal Inst_rxserie1_RC1_FRAMING_ERR : STD_LOGIC; signal Inst_rxserie1_RC1_PARITY_ERR : STD_LOGIC; signal Inst_rxserie1_I7_N1528 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_read_FFd3 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_read_FFd3_In : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_read_FFd4 : STD_LOGIC; signal Inst_rxserie1_FIFO1_rd_en : STD_LOGIC; signal Inst_rxserie1_FIFO1_wr_en : STD_LOGIC; signal N8727 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_write_FFd3 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_read_FFd4_In : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_1_n0000 : STD_LOGIC; signal Inst_txserie1_FIFO1_state_read_FFd1_In : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_0_n0000 : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_5_n0000 : STD_LOGIC; signal Inst_txserie1_FIFO1_state_read_FFd1 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_write_FFd3_In : STD_LOGIC; signal Inst_txserie1_FIFO1_state_read_FFd4_In : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_4_n0000 : STD_LOGIC; signal Inst_txserie1_FIFO1_dready : STD_LOGIC; signal bus_data_2_IOBUF : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_write_FFd1_In : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_write_FFd2_In : STD_LOGIC; signal Inst_txserie1_state_txload_0_Q : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_read_FFd1 : STD_LOGIC; signal Inst_txserie1_RFLAG_n0007 : STD_LOGIC; signal Inst_rxserie1_RFLAG_I1_N1528 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_read_FFd2 : STD_LOGIC; signal Inst_rxserie1_RFLAG_n0007 : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_2_n0000 : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_6_n0000 : STD_LOGIC; signal Inst_txserie1_FIFO1_state_write_FFd2 : STD_LOGIC; signal Inst_txserie1_FIFO1_state_write_FFd1_In : STD_LOGIC; signal Inst_txserie1_FIFO1_state_write_FFd3_In : STD_LOGIC; signal Inst_txserie1_FIFO1_dready_N1514 : STD_LOGIC; signal Inst_rxserie1_state_rx_read_FFd4 : STD_LOGIC; signal Inst_rxserie1_state_rx_read_FFd1 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_read_FFd4_N1643 : STD_LOGIC; signal Inst_rxserie1_state_rx_read_FFd3 : STD_LOGIC; signal N15406 : STD_LOGIC; signal Inst_txserie1_FIFO1_state_write_FFd2_In : STD_LOGIC; signal Inst_txserie1_FIFO1_state_write_FFd3 : STD_LOGIC; signal Inst_txserie1_RCONF_n0007 : STD_LOGIC; signal Inst_txserie1_FIFO1_wr_en : STD_LOGIC; signal Inst_txserie1_RCONF_I1_N1528 : STD_LOGIC; signal bus_data_4_IOBUF : STD_LOGIC; signal Inst_txserie1_RFLAG_REG_0_n0000 : STD_LOGIC; signal Inst_txserie1_FIFO1_state_read_FFd4 : STD_LOGIC; signal Inst_txserie1_RFLAG_REG_2_n0000 : STD_LOGIC; signal Inst_txserie1_RFLAG_I1_N1528 : STD_LOGIC; signal Inst_txserie1_FIFO1_rd_en : STD_LOGIC; signal Inst_txserie1_RFLAG_REG_3_n0000 : STD_LOGIC; signal Inst_txserie1_RFLAG_REG_1_n0000 : STD_LOGIC; signal Inst_txserie1_FIFO1_state_read_FFd3 : STD_LOGIC; signal Inst_txserie1_state_txload_2_Q : STD_LOGIC; signal bus_data_5_IOBUF : STD_LOGIC; signal Inst_txserie1_txready : STD_LOGIC; signal Inst_txserie1_fifopurge : STD_LOGIC; signal Inst_txserie1_txload : STD_LOGIC; signal Inst_txserie1_CLOCK1_ckout : STD_LOGIC; signal Inst_txserie1_n0010 : STD_LOGIC; signal N6828 : STD_LOGIC; signal bus_data_0_IOBUF : STD_LOGIC; signal bus_data_7_IOBUF : STD_LOGIC; signal bus_data_1_IOBUF : STD_LOGIC; signal Inst_txserie1_TX1_n0039 : STD_LOGIC; signal Inst_rxserie1_RC1_n0050 : STD_LOGIC; signal Inst_rxserie1_RC1_Madd_n0040_inst_cy_12 : STD_LOGIC; signal Inst_rxserie1_RC1_Madd_n0040_inst_cy_11 : STD_LOGIC; signal Inst_rxserie1_RC1_N10580 : STD_LOGIC; signal Inst_rxserie1_RC1_n0062 : STD_LOGIC; signal Inst_rxserie1_RC1_HUNT : STD_LOGIC; signal Inst_rxserie1_RC1_RX1 : STD_LOGIC; signal Inst_rxserie1_RC1_PARITYGEN : STD_LOGIC; signal Inst_rxserie1_RC1_n0051 : STD_LOGIC; signal Inst_decodisa_reg_select : STD_LOGIC; signal Inst_rxserie1_RC1_RXCLK : STD_LOGIC; signal Inst_rxserie1_RC1_READ1 : STD_LOGIC; signal Inst_rxserie1_RC1_IDLE1 : STD_LOGIC; signal Inst_rxserie1_RC1_READ2 : STD_LOGIC; signal Inst_rxserie1_RC1_n0020 : STD_LOGIC; signal Inst_rxserie1_RC1_n0015 : STD_LOGIC; signal Inst_rxserie1_RC1_n0021 : STD_LOGIC; signal Inst_rxserie1_RC1_n0022 : STD_LOGIC; signal Inst_rxserie1_RC1_n0023 : STD_LOGIC; signal Inst_rxserie1_RC1_n0024 : STD_LOGIC; signal Inst_rxserie1_RC1_n0019 : STD_LOGIC; signal Inst_rxserie1_RC1_n0025 : STD_LOGIC; signal Inst_rxserie1_RC1_n0031 : STD_LOGIC; signal Inst_rxserie1_RC1_n0026 : STD_LOGIC; signal Inst_rxserie1_RC1_n0027 : STD_LOGIC; signal Inst_rxserie1_RC1_n0028 : STD_LOGIC; signal Inst_rxserie1_RC1_n0034 : STD_LOGIC; signal Inst_rxserie1_RC1_n0029 : STD_LOGIC; signal Inst_rxserie1_RC1_RXPARITY : STD_LOGIC; signal Inst_rxserie1_RC1_n0035 : STD_LOGIC; signal Inst_rxserie1_RC1_RXSTOP : STD_LOGIC; signal Inst_rxserie1_RC1_n0041 : STD_LOGIC; signal Inst_rxserie1_RC1_n0036 : STD_LOGIC; signal Inst_rxserie1_RC1_n0063 : STD_LOGIC; signal Inst_rxserie1_RC1_Madd_n0040_inst_lut2_10 : STD_LOGIC; signal Inst_rxserie1_RC1_Madd_n0040_inst_cy_10 : STD_LOGIC; signal Inst_rxserie1_RC1_IDLE : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6 : STD_LOGIC; signal Inst_txserie1_CLOCK1_n0005 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 : STD_LOGIC; signal N15395 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_0_3_n0001 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_n0006 : STD_LOGIC; signal N15387 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_0_0_n0001 : STD_LOGIC; signal Inst_rxserie1_RC1_RXCNT_3_rt : STD_LOGIC; signal N15389 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_0_0_n0000 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_0_2_n0000 : STD_LOGIC; signal N15391 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_0_3_n0000 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_0_1_n0001 : STD_LOGIC; signal N15393 : STD_LOGIC; signal N15397 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_0_2_n0001 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_0_1_n0000 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_rt : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_n0005 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_3_n0001 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_n0006 : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_0_rt : STD_LOGIC; signal Inst_rxserie1_RC1_RXCNT_1_rt : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_0_n0001 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_0_n0000 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_2_n0000 : STD_LOGIC; signal Inst_rxserie1_RC1_RXCNT_2_rt : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_3_n0000 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_1_n0001 : STD_LOGIC; signal N15385 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_2_n0001 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_1_n0000 : STD_LOGIC; signal N15399 : STD_LOGIC; signal Inst_txserie1_TX1_WRITE2 : STD_LOGIC; signal Inst_txserie1_TX1_TXCLK : STD_LOGIC; signal Inst_txserie1_TX1_WRITE1 : STD_LOGIC; signal Inst_txserie1_TX1_TXDONE : STD_LOGIC; signal Inst_txserie1_TX1_TXDATARDY : STD_LOGIC; signal Inst_txserie1_TX1_n0048 : STD_LOGIC; signal Inst_txserie1_TX1_TXDONE1 : STD_LOGIC; signal Inst_txserie1_TX1_TAG1 : STD_LOGIC; signal Inst_txserie1_TX1_TAG2 : STD_LOGIC; signal Inst_txserie1_TX1_TXPARITY : STD_LOGIC; signal Inst_txserie1_TX1_n0020 : STD_LOGIC; signal Inst_txserie1_TX1_n0021 : STD_LOGIC; signal Inst_txserie1_TX1_n0022 : STD_LOGIC; signal Inst_txserie1_TX1_n0017 : STD_LOGIC; signal Inst_txserie1_TX1_n0023 : STD_LOGIC; signal Inst_txserie1_TX1_n0018 : STD_LOGIC; signal Inst_txserie1_TX1_n0024 : STD_LOGIC; signal Inst_txserie1_TX1_n0019 : STD_LOGIC; signal Inst_txserie1_TX1_n0030 : STD_LOGIC; signal Inst_txserie1_TX1_n0025 : STD_LOGIC; signal Inst_txserie1_TX1_n0031 : STD_LOGIC; signal N14869 : STD_LOGIC; signal N15437 : STD_LOGIC; signal CHOICE135 : STD_LOGIC; signal N14920 : STD_LOGIC; signal N15477 : STD_LOGIC; signal CHOICE95 : STD_LOGIC; signal CHOICE41 : STD_LOGIC; signal N15425 : STD_LOGIC; signal CHOICE68 : STD_LOGIC; signal CHOICE98 : STD_LOGIC; signal CHOICE36 : STD_LOGIC; signal CHOICE144 : STD_LOGIC; signal N15429 : STD_LOGIC; signal N15433 : STD_LOGIC; signal CHOICE116 : STD_LOGIC; signal N14659 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N47 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N48 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N49 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N50 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N51 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N52 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N53 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N54 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1271 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1143 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1142 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N74 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1113 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1110 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1107 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1104 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1101 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N73 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1040 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1037 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1034 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1031 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1028 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N716 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N738 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N715 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N735 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N733 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N17 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N714 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N730 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N728 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N18 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N713 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N725 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N723 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N19 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N712 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N720 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N717 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N20 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N718 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N592 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N609 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N4 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N591 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N606 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N604 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N5 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N590 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N601 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N599 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N6 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N589 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N596 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N593 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N7 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N594 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N33 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_wr_ack : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N505 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_wr_err : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N456 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N38 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N3 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_rd_ack : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N333 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_rd_err : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N284 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N37 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N2 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N0 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N47 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N48 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N49 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N50 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N51 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N52 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N53 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N54 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1271 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1143 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1142 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N74 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1113 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1110 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1107 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1104 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1101 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N73 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1040 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1037 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1034 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1031 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1028 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N716 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N738 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N715 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N735 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N733 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N17 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N714 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N730 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N728 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N18 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N713 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N725 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N723 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N19 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N712 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N720 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N717 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N20 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N718 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N592 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N609 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N4 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N591 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N606 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N604 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N5 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N590 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N601 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N599 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N6 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N589 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N596 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N593 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N7 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N594 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N33 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_wr_ack : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N505 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_wr_err : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N456 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N38 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N3 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_rd_ack : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N333 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_rd_err : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N284 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N37 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N2 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N0 : STD_LOGIC; signal Inst_txserie1_FIFO1_fifo0_N1 : STD_LOGIC; signal Inst_decodisa_dadrL_O_255_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18685 : STD_LOGIC; signal Inst_decodisa_dadrL_N18684 : STD_LOGIC; signal Inst_decodisa_dadrL_O_254_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18614 : STD_LOGIC; signal Inst_decodisa_dadrL_N18613 : STD_LOGIC; signal Inst_decodisa_dadrL_O_253_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18543 : STD_LOGIC; signal Inst_decodisa_dadrL_N18542 : STD_LOGIC; signal Inst_decodisa_dadrL_O_252_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18472 : STD_LOGIC; signal Inst_decodisa_dadrL_N18471 : STD_LOGIC; signal Inst_decodisa_dadrL_O_251_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18401 : STD_LOGIC; signal Inst_decodisa_dadrL_N18400 : STD_LOGIC; signal Inst_decodisa_dadrL_O_250_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18330 : STD_LOGIC; signal Inst_decodisa_dadrL_N18329 : STD_LOGIC; signal Inst_decodisa_dadrL_O_249_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18259 : STD_LOGIC; signal Inst_decodisa_dadrL_N18258 : STD_LOGIC; signal Inst_decodisa_dadrL_O_248_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18188 : STD_LOGIC; signal Inst_decodisa_dadrL_N18187 : STD_LOGIC; signal Inst_decodisa_dadrL_O_247_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18117 : STD_LOGIC; signal Inst_decodisa_dadrL_N18116 : STD_LOGIC; signal Inst_decodisa_dadrL_O_246_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18046 : STD_LOGIC; signal Inst_decodisa_dadrL_N18045 : STD_LOGIC; signal Inst_decodisa_dadrL_O_245_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17975 : STD_LOGIC; signal Inst_decodisa_dadrL_N17974 : STD_LOGIC; signal Inst_decodisa_dadrL_O_244_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17904 : STD_LOGIC; signal Inst_decodisa_dadrL_N17903 : STD_LOGIC; signal Inst_decodisa_dadrL_O_243_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17833 : STD_LOGIC; signal Inst_decodisa_dadrL_N17832 : STD_LOGIC; signal Inst_decodisa_dadrL_O_242_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17762 : STD_LOGIC; signal Inst_decodisa_dadrL_N17761 : STD_LOGIC; signal Inst_decodisa_dadrL_O_241_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17691 : STD_LOGIC; signal Inst_decodisa_dadrL_N17690 : STD_LOGIC; signal Inst_decodisa_dadrL_O_240_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17620 : STD_LOGIC; signal Inst_decodisa_dadrL_N17619 : STD_LOGIC; signal Inst_decodisa_dadrL_O_239_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17549 : STD_LOGIC; signal Inst_decodisa_dadrL_N17548 : STD_LOGIC; signal Inst_decodisa_dadrL_O_238_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17478 : STD_LOGIC; signal Inst_decodisa_dadrL_N17477 : STD_LOGIC; signal Inst_decodisa_dadrL_O_237_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17407 : STD_LOGIC; signal Inst_decodisa_dadrL_N17406 : STD_LOGIC; signal Inst_decodisa_dadrL_O_236_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17336 : STD_LOGIC; signal Inst_decodisa_dadrL_N17335 : STD_LOGIC; signal Inst_decodisa_dadrL_O_235_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17265 : STD_LOGIC; signal Inst_decodisa_dadrL_N17264 : STD_LOGIC; signal Inst_decodisa_dadrL_O_234_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17194 : STD_LOGIC; signal Inst_decodisa_dadrL_N17193 : STD_LOGIC; signal Inst_decodisa_dadrL_O_233_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17123 : STD_LOGIC; signal Inst_decodisa_dadrL_N17122 : STD_LOGIC; signal Inst_decodisa_dadrL_O_232_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N17052 : STD_LOGIC; signal Inst_decodisa_dadrL_N17051 : STD_LOGIC; signal Inst_decodisa_dadrL_O_231_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16981 : STD_LOGIC; signal Inst_decodisa_dadrL_N16980 : STD_LOGIC; signal Inst_decodisa_dadrL_O_230_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16910 : STD_LOGIC; signal Inst_decodisa_dadrL_N16909 : STD_LOGIC; signal Inst_decodisa_dadrL_O_229_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16839 : STD_LOGIC; signal Inst_decodisa_dadrL_N16838 : STD_LOGIC; signal Inst_decodisa_dadrL_O_228_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16768 : STD_LOGIC; signal Inst_decodisa_dadrL_N16767 : STD_LOGIC; signal Inst_decodisa_dadrL_O_227_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16697 : STD_LOGIC; signal Inst_decodisa_dadrL_N16696 : STD_LOGIC; signal Inst_decodisa_dadrL_O_226_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16626 : STD_LOGIC; signal Inst_decodisa_dadrL_N16625 : STD_LOGIC; signal Inst_decodisa_dadrL_O_225_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16555 : STD_LOGIC; signal Inst_decodisa_dadrL_N16554 : STD_LOGIC; signal Inst_decodisa_dadrL_O_224_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16484 : STD_LOGIC; signal Inst_decodisa_dadrL_N16483 : STD_LOGIC; signal Inst_decodisa_dadrL_O_223_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16413 : STD_LOGIC; signal Inst_decodisa_dadrL_N16412 : STD_LOGIC; signal Inst_decodisa_dadrL_O_222_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16342 : STD_LOGIC; signal Inst_decodisa_dadrL_N16341 : STD_LOGIC; signal Inst_decodisa_dadrL_O_221_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16271 : STD_LOGIC; signal Inst_decodisa_dadrL_N16270 : STD_LOGIC; signal Inst_decodisa_dadrL_O_220_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16200 : STD_LOGIC; signal Inst_decodisa_dadrL_N16199 : STD_LOGIC; signal Inst_decodisa_dadrL_O_219_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16129 : STD_LOGIC; signal Inst_decodisa_dadrL_N16128 : STD_LOGIC; signal Inst_decodisa_dadrL_O_218_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N16058 : STD_LOGIC; signal Inst_decodisa_dadrL_N16057 : STD_LOGIC; signal Inst_decodisa_dadrL_O_217_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15987 : STD_LOGIC; signal Inst_decodisa_dadrL_N15986 : STD_LOGIC; signal Inst_decodisa_dadrL_O_216_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15916 : STD_LOGIC; signal Inst_decodisa_dadrL_N15915 : STD_LOGIC; signal Inst_decodisa_dadrL_O_215_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15845 : STD_LOGIC; signal Inst_decodisa_dadrL_N15844 : STD_LOGIC; signal Inst_decodisa_dadrL_O_214_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15774 : STD_LOGIC; signal Inst_decodisa_dadrL_N15773 : STD_LOGIC; signal Inst_decodisa_dadrL_O_213_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15703 : STD_LOGIC; signal Inst_decodisa_dadrL_N15702 : STD_LOGIC; signal Inst_decodisa_dadrL_O_212_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15632 : STD_LOGIC; signal Inst_decodisa_dadrL_N15631 : STD_LOGIC; signal Inst_decodisa_dadrL_O_211_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15561 : STD_LOGIC; signal Inst_decodisa_dadrL_N15560 : STD_LOGIC; signal Inst_decodisa_dadrL_O_210_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15490 : STD_LOGIC; signal Inst_decodisa_dadrL_N15489 : STD_LOGIC; signal Inst_decodisa_dadrL_O_209_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15419 : STD_LOGIC; signal Inst_decodisa_dadrL_N15418 : STD_LOGIC; signal Inst_decodisa_dadrL_O_208_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15348 : STD_LOGIC; signal Inst_decodisa_dadrL_N15347 : STD_LOGIC; signal Inst_decodisa_dadrL_O_207_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15277 : STD_LOGIC; signal Inst_decodisa_dadrL_N15276 : STD_LOGIC; signal Inst_decodisa_dadrL_O_206_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15206 : STD_LOGIC; signal Inst_decodisa_dadrL_N15205 : STD_LOGIC; signal Inst_decodisa_dadrL_O_205_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15135 : STD_LOGIC; signal Inst_decodisa_dadrL_N15134 : STD_LOGIC; signal Inst_decodisa_dadrL_O_204_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N15064 : STD_LOGIC; signal Inst_decodisa_dadrL_N15063 : STD_LOGIC; signal Inst_decodisa_dadrL_O_203_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14993 : STD_LOGIC; signal Inst_decodisa_dadrL_N14992 : STD_LOGIC; signal Inst_decodisa_dadrL_O_202_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14922 : STD_LOGIC; signal Inst_decodisa_dadrL_N14921 : STD_LOGIC; signal Inst_decodisa_dadrL_O_201_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14851 : STD_LOGIC; signal Inst_decodisa_dadrL_N14850 : STD_LOGIC; signal Inst_decodisa_dadrL_O_200_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14780 : STD_LOGIC; signal Inst_decodisa_dadrL_N14779 : STD_LOGIC; signal Inst_decodisa_dadrL_O_199_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14709 : STD_LOGIC; signal Inst_decodisa_dadrL_N14708 : STD_LOGIC; signal Inst_decodisa_dadrL_O_198_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14638 : STD_LOGIC; signal Inst_decodisa_dadrL_N14637 : STD_LOGIC; signal Inst_decodisa_dadrL_O_197_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14567 : STD_LOGIC; signal Inst_decodisa_dadrL_N14566 : STD_LOGIC; signal Inst_decodisa_dadrL_O_196_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14496 : STD_LOGIC; signal Inst_decodisa_dadrL_N14495 : STD_LOGIC; signal Inst_decodisa_dadrL_O_195_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14425 : STD_LOGIC; signal Inst_decodisa_dadrL_N14424 : STD_LOGIC; signal Inst_decodisa_dadrL_O_194_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14354 : STD_LOGIC; signal Inst_decodisa_dadrL_N14353 : STD_LOGIC; signal Inst_decodisa_dadrL_O_193_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14283 : STD_LOGIC; signal Inst_decodisa_dadrL_N14282 : STD_LOGIC; signal Inst_decodisa_dadrL_O_192_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14212 : STD_LOGIC; signal Inst_decodisa_dadrL_N14211 : STD_LOGIC; signal Inst_decodisa_dadrL_O_191_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14141 : STD_LOGIC; signal Inst_decodisa_dadrL_N14140 : STD_LOGIC; signal Inst_decodisa_dadrL_O_190_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N14070 : STD_LOGIC; signal Inst_decodisa_dadrL_N14069 : STD_LOGIC; signal Inst_decodisa_dadrL_O_189_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13999 : STD_LOGIC; signal Inst_decodisa_dadrL_N13998 : STD_LOGIC; signal Inst_decodisa_dadrL_O_188_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13928 : STD_LOGIC; signal Inst_decodisa_dadrL_N13927 : STD_LOGIC; signal Inst_decodisa_dadrL_O_187_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13857 : STD_LOGIC; signal Inst_decodisa_dadrL_N13856 : STD_LOGIC; signal Inst_decodisa_dadrL_O_186_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13786 : STD_LOGIC; signal Inst_decodisa_dadrL_N13785 : STD_LOGIC; signal Inst_decodisa_dadrL_O_185_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13715 : STD_LOGIC; signal Inst_decodisa_dadrL_N13714 : STD_LOGIC; signal Inst_decodisa_dadrL_O_184_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13644 : STD_LOGIC; signal Inst_decodisa_dadrL_N13643 : STD_LOGIC; signal Inst_decodisa_dadrL_O_183_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13573 : STD_LOGIC; signal Inst_decodisa_dadrL_N13572 : STD_LOGIC; signal Inst_decodisa_dadrL_O_182_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13502 : STD_LOGIC; signal Inst_decodisa_dadrL_N13501 : STD_LOGIC; signal Inst_decodisa_dadrL_O_181_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13431 : STD_LOGIC; signal Inst_decodisa_dadrL_N13430 : STD_LOGIC; signal Inst_decodisa_dadrL_O_180_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13360 : STD_LOGIC; signal Inst_decodisa_dadrL_N13359 : STD_LOGIC; signal Inst_decodisa_dadrL_O_179_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13289 : STD_LOGIC; signal Inst_decodisa_dadrL_N13288 : STD_LOGIC; signal Inst_decodisa_dadrL_O_178_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13218 : STD_LOGIC; signal Inst_decodisa_dadrL_N13217 : STD_LOGIC; signal Inst_decodisa_dadrL_O_177_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13147 : STD_LOGIC; signal Inst_decodisa_dadrL_N13146 : STD_LOGIC; signal Inst_decodisa_dadrL_O_176_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13076 : STD_LOGIC; signal Inst_decodisa_dadrL_N13075 : STD_LOGIC; signal Inst_decodisa_dadrL_O_175_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N13005 : STD_LOGIC; signal Inst_decodisa_dadrL_N13004 : STD_LOGIC; signal Inst_decodisa_dadrL_O_174_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12934 : STD_LOGIC; signal Inst_decodisa_dadrL_N12933 : STD_LOGIC; signal Inst_decodisa_dadrL_O_173_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12863 : STD_LOGIC; signal Inst_decodisa_dadrL_N12862 : STD_LOGIC; signal Inst_decodisa_dadrL_O_172_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12792 : STD_LOGIC; signal Inst_decodisa_dadrL_N12791 : STD_LOGIC; signal Inst_decodisa_dadrL_O_171_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12721 : STD_LOGIC; signal Inst_decodisa_dadrL_N12720 : STD_LOGIC; signal Inst_decodisa_dadrL_O_170_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12650 : STD_LOGIC; signal Inst_decodisa_dadrL_N12649 : STD_LOGIC; signal Inst_decodisa_dadrL_O_169_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12579 : STD_LOGIC; signal Inst_decodisa_dadrL_N12578 : STD_LOGIC; signal Inst_decodisa_dadrL_O_168_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12508 : STD_LOGIC; signal Inst_decodisa_dadrL_N12507 : STD_LOGIC; signal Inst_decodisa_dadrL_O_167_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12437 : STD_LOGIC; signal Inst_decodisa_dadrL_N12436 : STD_LOGIC; signal Inst_decodisa_dadrL_O_166_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12366 : STD_LOGIC; signal Inst_decodisa_dadrL_N12365 : STD_LOGIC; signal Inst_decodisa_dadrL_O_165_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12295 : STD_LOGIC; signal Inst_decodisa_dadrL_N12294 : STD_LOGIC; signal Inst_decodisa_dadrL_O_164_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12224 : STD_LOGIC; signal Inst_decodisa_dadrL_N12223 : STD_LOGIC; signal Inst_decodisa_dadrL_O_163_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12153 : STD_LOGIC; signal Inst_decodisa_dadrL_N12152 : STD_LOGIC; signal Inst_decodisa_dadrL_O_162_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12082 : STD_LOGIC; signal Inst_decodisa_dadrL_N12081 : STD_LOGIC; signal Inst_decodisa_dadrL_O_161_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N12011 : STD_LOGIC; signal Inst_decodisa_dadrL_N12010 : STD_LOGIC; signal Inst_decodisa_dadrL_O_160_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11940 : STD_LOGIC; signal Inst_decodisa_dadrL_N11939 : STD_LOGIC; signal Inst_decodisa_dadrL_O_159_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11869 : STD_LOGIC; signal Inst_decodisa_dadrL_N11868 : STD_LOGIC; signal Inst_decodisa_dadrL_O_158_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11798 : STD_LOGIC; signal Inst_decodisa_dadrL_N11797 : STD_LOGIC; signal Inst_decodisa_dadrL_O_157_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11727 : STD_LOGIC; signal Inst_decodisa_dadrL_N11726 : STD_LOGIC; signal Inst_decodisa_dadrL_O_156_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11656 : STD_LOGIC; signal Inst_decodisa_dadrL_N11655 : STD_LOGIC; signal Inst_decodisa_dadrL_O_155_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11585 : STD_LOGIC; signal Inst_decodisa_dadrL_N11584 : STD_LOGIC; signal Inst_decodisa_dadrL_O_154_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11514 : STD_LOGIC; signal Inst_decodisa_dadrL_N11513 : STD_LOGIC; signal Inst_decodisa_dadrL_O_153_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11443 : STD_LOGIC; signal Inst_decodisa_dadrL_N11442 : STD_LOGIC; signal Inst_decodisa_dadrL_O_152_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11372 : STD_LOGIC; signal Inst_decodisa_dadrL_N11371 : STD_LOGIC; signal Inst_decodisa_dadrL_O_151_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11301 : STD_LOGIC; signal Inst_decodisa_dadrL_N11300 : STD_LOGIC; signal Inst_decodisa_dadrL_O_150_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11230 : STD_LOGIC; signal Inst_decodisa_dadrL_N11229 : STD_LOGIC; signal Inst_decodisa_dadrL_O_149_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11159 : STD_LOGIC; signal Inst_decodisa_dadrL_N11158 : STD_LOGIC; signal Inst_decodisa_dadrL_O_148_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11088 : STD_LOGIC; signal Inst_decodisa_dadrL_N11087 : STD_LOGIC; signal Inst_decodisa_dadrL_O_147_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N11017 : STD_LOGIC; signal Inst_decodisa_dadrL_N11016 : STD_LOGIC; signal Inst_decodisa_dadrL_O_146_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10946 : STD_LOGIC; signal Inst_decodisa_dadrL_N10945 : STD_LOGIC; signal Inst_decodisa_dadrL_O_145_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10875 : STD_LOGIC; signal Inst_decodisa_dadrL_N10874 : STD_LOGIC; signal Inst_decodisa_dadrL_O_144_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10804 : STD_LOGIC; signal Inst_decodisa_dadrL_N10803 : STD_LOGIC; signal Inst_decodisa_dadrL_O_143_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10733 : STD_LOGIC; signal Inst_decodisa_dadrL_N10732 : STD_LOGIC; signal Inst_decodisa_dadrL_O_142_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10662 : STD_LOGIC; signal Inst_decodisa_dadrL_N10661 : STD_LOGIC; signal Inst_decodisa_dadrL_O_141_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10591 : STD_LOGIC; signal Inst_decodisa_dadrL_N10590 : STD_LOGIC; signal Inst_decodisa_dadrL_O_140_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10520 : STD_LOGIC; signal Inst_decodisa_dadrL_N10519 : STD_LOGIC; signal Inst_decodisa_dadrL_O_139_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10449 : STD_LOGIC; signal Inst_decodisa_dadrL_N10448 : STD_LOGIC; signal Inst_decodisa_dadrL_O_138_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10378 : STD_LOGIC; signal Inst_decodisa_dadrL_N10377 : STD_LOGIC; signal Inst_decodisa_dadrL_O_137_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10307 : STD_LOGIC; signal Inst_decodisa_dadrL_N10306 : STD_LOGIC; signal Inst_decodisa_dadrL_O_136_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10236 : STD_LOGIC; signal Inst_decodisa_dadrL_N10235 : STD_LOGIC; signal Inst_decodisa_dadrL_O_135_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10165 : STD_LOGIC; signal Inst_decodisa_dadrL_N10164 : STD_LOGIC; signal Inst_decodisa_dadrL_O_134_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10094 : STD_LOGIC; signal Inst_decodisa_dadrL_N10093 : STD_LOGIC; signal Inst_decodisa_dadrL_O_133_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N10023 : STD_LOGIC; signal Inst_decodisa_dadrL_N10022 : STD_LOGIC; signal Inst_decodisa_dadrL_O_132_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9952 : STD_LOGIC; signal Inst_decodisa_dadrL_N9951 : STD_LOGIC; signal Inst_decodisa_dadrL_O_131_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9881 : STD_LOGIC; signal Inst_decodisa_dadrL_N9880 : STD_LOGIC; signal Inst_decodisa_dadrL_O_130_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9810 : STD_LOGIC; signal Inst_decodisa_dadrL_N9809 : STD_LOGIC; signal Inst_decodisa_dadrL_O_129_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9739 : STD_LOGIC; signal Inst_decodisa_dadrL_N9738 : STD_LOGIC; signal Inst_decodisa_dadrL_O_128_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9668 : STD_LOGIC; signal Inst_decodisa_dadrL_N9667 : STD_LOGIC; signal Inst_decodisa_dadrL_O_127_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9597 : STD_LOGIC; signal Inst_decodisa_dadrL_N9596 : STD_LOGIC; signal Inst_decodisa_dadrL_O_126_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9526 : STD_LOGIC; signal Inst_decodisa_dadrL_N9525 : STD_LOGIC; signal Inst_decodisa_dadrL_O_125_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9455 : STD_LOGIC; signal Inst_decodisa_dadrL_N9454 : STD_LOGIC; signal Inst_decodisa_dadrL_O_124_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9384 : STD_LOGIC; signal Inst_decodisa_dadrL_N9383 : STD_LOGIC; signal Inst_decodisa_dadrL_O_123_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9313 : STD_LOGIC; signal Inst_decodisa_dadrL_N9312 : STD_LOGIC; signal Inst_decodisa_dadrL_O_122_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9242 : STD_LOGIC; signal Inst_decodisa_dadrL_N9241 : STD_LOGIC; signal Inst_decodisa_dadrL_O_121_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9171 : STD_LOGIC; signal Inst_decodisa_dadrL_N9170 : STD_LOGIC; signal Inst_decodisa_dadrL_O_120_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9100 : STD_LOGIC; signal Inst_decodisa_dadrL_N9099 : STD_LOGIC; signal Inst_decodisa_dadrL_O_119_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N9029 : STD_LOGIC; signal Inst_decodisa_dadrL_N9028 : STD_LOGIC; signal Inst_decodisa_dadrL_O_118_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8958 : STD_LOGIC; signal Inst_decodisa_dadrL_N8957 : STD_LOGIC; signal Inst_decodisa_dadrL_O_117_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8887 : STD_LOGIC; signal Inst_decodisa_dadrL_N8886 : STD_LOGIC; signal Inst_decodisa_dadrL_O_116_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8816 : STD_LOGIC; signal Inst_decodisa_dadrL_N8815 : STD_LOGIC; signal Inst_decodisa_dadrL_O_115_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8745 : STD_LOGIC; signal Inst_decodisa_dadrL_N8744 : STD_LOGIC; signal Inst_decodisa_dadrL_O_114_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8674 : STD_LOGIC; signal Inst_decodisa_dadrL_N8673 : STD_LOGIC; signal Inst_decodisa_dadrL_O_113_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8603 : STD_LOGIC; signal Inst_decodisa_dadrL_N8602 : STD_LOGIC; signal Inst_decodisa_dadrL_O_112_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8532 : STD_LOGIC; signal Inst_decodisa_dadrL_N8531 : STD_LOGIC; signal Inst_decodisa_dadrL_O_111_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8461 : STD_LOGIC; signal Inst_decodisa_dadrL_N8460 : STD_LOGIC; signal Inst_decodisa_dadrL_O_110_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8390 : STD_LOGIC; signal Inst_decodisa_dadrL_N8389 : STD_LOGIC; signal Inst_decodisa_dadrL_O_109_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8319 : STD_LOGIC; signal Inst_decodisa_dadrL_N8318 : STD_LOGIC; signal Inst_decodisa_dadrL_O_108_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8248 : STD_LOGIC; signal Inst_decodisa_dadrL_N8247 : STD_LOGIC; signal Inst_decodisa_dadrL_O_107_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8177 : STD_LOGIC; signal Inst_decodisa_dadrL_N8176 : STD_LOGIC; signal Inst_decodisa_dadrL_O_106_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8106 : STD_LOGIC; signal Inst_decodisa_dadrL_N8105 : STD_LOGIC; signal Inst_decodisa_dadrL_O_105_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N8035 : STD_LOGIC; signal Inst_decodisa_dadrL_N8034 : STD_LOGIC; signal Inst_decodisa_dadrL_O_104_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7964 : STD_LOGIC; signal Inst_decodisa_dadrL_N7963 : STD_LOGIC; signal Inst_decodisa_dadrL_O_103_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7893 : STD_LOGIC; signal Inst_decodisa_dadrL_N7892 : STD_LOGIC; signal Inst_decodisa_dadrL_O_102_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7822 : STD_LOGIC; signal Inst_decodisa_dadrL_N7821 : STD_LOGIC; signal Inst_decodisa_dadrL_O_101_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7751 : STD_LOGIC; signal Inst_decodisa_dadrL_N7750 : STD_LOGIC; signal Inst_decodisa_dadrL_O_100_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7680 : STD_LOGIC; signal Inst_decodisa_dadrL_N7679 : STD_LOGIC; signal Inst_decodisa_dadrL_O_99_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7609 : STD_LOGIC; signal Inst_decodisa_dadrL_N7608 : STD_LOGIC; signal Inst_decodisa_dadrL_O_98_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7538 : STD_LOGIC; signal Inst_decodisa_dadrL_N7537 : STD_LOGIC; signal Inst_decodisa_dadrL_O_97_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7467 : STD_LOGIC; signal Inst_decodisa_dadrL_N7466 : STD_LOGIC; signal Inst_decodisa_dadrL_O_96_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7396 : STD_LOGIC; signal Inst_decodisa_dadrL_N7395 : STD_LOGIC; signal Inst_decodisa_dadrL_O_95_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7325 : STD_LOGIC; signal Inst_decodisa_dadrL_N7324 : STD_LOGIC; signal Inst_decodisa_dadrL_O_94_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7254 : STD_LOGIC; signal Inst_decodisa_dadrL_N7253 : STD_LOGIC; signal Inst_decodisa_dadrL_O_93_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7183 : STD_LOGIC; signal Inst_decodisa_dadrL_N7182 : STD_LOGIC; signal Inst_decodisa_dadrL_O_92_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7112 : STD_LOGIC; signal Inst_decodisa_dadrL_N7111 : STD_LOGIC; signal Inst_decodisa_dadrL_O_91_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N7041 : STD_LOGIC; signal Inst_decodisa_dadrL_N7040 : STD_LOGIC; signal Inst_decodisa_dadrL_O_90_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6970 : STD_LOGIC; signal Inst_decodisa_dadrL_N6969 : STD_LOGIC; signal Inst_decodisa_dadrL_O_89_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6899 : STD_LOGIC; signal Inst_decodisa_dadrL_N6898 : STD_LOGIC; signal Inst_decodisa_dadrL_O_88_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6828 : STD_LOGIC; signal Inst_decodisa_dadrL_N6827 : STD_LOGIC; signal Inst_decodisa_dadrL_O_87_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6757 : STD_LOGIC; signal Inst_decodisa_dadrL_N6756 : STD_LOGIC; signal Inst_decodisa_dadrL_O_86_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6686 : STD_LOGIC; signal Inst_decodisa_dadrL_N6685 : STD_LOGIC; signal Inst_decodisa_dadrL_O_85_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6615 : STD_LOGIC; signal Inst_decodisa_dadrL_N6614 : STD_LOGIC; signal Inst_decodisa_dadrL_O_84_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6544 : STD_LOGIC; signal Inst_decodisa_dadrL_N6543 : STD_LOGIC; signal Inst_decodisa_dadrL_O_83_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6473 : STD_LOGIC; signal Inst_decodisa_dadrL_N6472 : STD_LOGIC; signal Inst_decodisa_dadrL_O_82_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6402 : STD_LOGIC; signal Inst_decodisa_dadrL_N6401 : STD_LOGIC; signal Inst_decodisa_dadrL_O_81_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6331 : STD_LOGIC; signal Inst_decodisa_dadrL_N6330 : STD_LOGIC; signal Inst_decodisa_dadrL_O_80_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6260 : STD_LOGIC; signal Inst_decodisa_dadrL_N6259 : STD_LOGIC; signal Inst_decodisa_dadrL_O_79_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6189 : STD_LOGIC; signal Inst_decodisa_dadrL_N6188 : STD_LOGIC; signal Inst_decodisa_dadrL_O_78_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6118 : STD_LOGIC; signal Inst_decodisa_dadrL_N6117 : STD_LOGIC; signal Inst_decodisa_dadrL_O_77_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N6047 : STD_LOGIC; signal Inst_decodisa_dadrL_N6046 : STD_LOGIC; signal Inst_decodisa_dadrL_O_76_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5976 : STD_LOGIC; signal Inst_decodisa_dadrL_N5975 : STD_LOGIC; signal Inst_decodisa_dadrL_O_75_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5905 : STD_LOGIC; signal Inst_decodisa_dadrL_N5904 : STD_LOGIC; signal Inst_decodisa_dadrL_O_74_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5834 : STD_LOGIC; signal Inst_decodisa_dadrL_N5833 : STD_LOGIC; signal Inst_decodisa_dadrL_O_73_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5763 : STD_LOGIC; signal Inst_decodisa_dadrL_N5762 : STD_LOGIC; signal Inst_decodisa_dadrL_O_72_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5692 : STD_LOGIC; signal Inst_decodisa_dadrL_N5691 : STD_LOGIC; signal Inst_decodisa_dadrL_O_71_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5621 : STD_LOGIC; signal Inst_decodisa_dadrL_N5620 : STD_LOGIC; signal Inst_decodisa_dadrL_O_70_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5550 : STD_LOGIC; signal Inst_decodisa_dadrL_N5549 : STD_LOGIC; signal Inst_decodisa_dadrL_O_69_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5479 : STD_LOGIC; signal Inst_decodisa_dadrL_N5478 : STD_LOGIC; signal Inst_decodisa_dadrL_O_68_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5408 : STD_LOGIC; signal Inst_decodisa_dadrL_N5407 : STD_LOGIC; signal Inst_decodisa_dadrL_O_67_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5337 : STD_LOGIC; signal Inst_decodisa_dadrL_N5336 : STD_LOGIC; signal Inst_decodisa_dadrL_O_66_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5266 : STD_LOGIC; signal Inst_decodisa_dadrL_N5265 : STD_LOGIC; signal Inst_decodisa_dadrL_O_65_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5195 : STD_LOGIC; signal Inst_decodisa_dadrL_N5194 : STD_LOGIC; signal Inst_decodisa_dadrL_O_64_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5124 : STD_LOGIC; signal Inst_decodisa_dadrL_N5123 : STD_LOGIC; signal Inst_decodisa_dadrL_O_63_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N5053 : STD_LOGIC; signal Inst_decodisa_dadrL_N5052 : STD_LOGIC; signal Inst_decodisa_dadrL_O_62_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4982 : STD_LOGIC; signal Inst_decodisa_dadrL_N4981 : STD_LOGIC; signal Inst_decodisa_dadrL_O_61_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4911 : STD_LOGIC; signal Inst_decodisa_dadrL_N4910 : STD_LOGIC; signal Inst_decodisa_dadrL_O_60_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4840 : STD_LOGIC; signal Inst_decodisa_dadrL_N4839 : STD_LOGIC; signal Inst_decodisa_dadrL_O_59_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4769 : STD_LOGIC; signal Inst_decodisa_dadrL_N4768 : STD_LOGIC; signal Inst_decodisa_dadrL_O_58_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4698 : STD_LOGIC; signal Inst_decodisa_dadrL_N4697 : STD_LOGIC; signal Inst_decodisa_dadrL_O_57_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4627 : STD_LOGIC; signal Inst_decodisa_dadrL_N4626 : STD_LOGIC; signal Inst_decodisa_dadrL_O_56_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4556 : STD_LOGIC; signal Inst_decodisa_dadrL_N4555 : STD_LOGIC; signal Inst_decodisa_dadrL_O_55_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4485 : STD_LOGIC; signal Inst_decodisa_dadrL_N4484 : STD_LOGIC; signal Inst_decodisa_dadrL_O_54_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4414 : STD_LOGIC; signal Inst_decodisa_dadrL_N4413 : STD_LOGIC; signal Inst_decodisa_dadrL_O_53_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4343 : STD_LOGIC; signal Inst_decodisa_dadrL_N4342 : STD_LOGIC; signal Inst_decodisa_dadrL_O_52_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4272 : STD_LOGIC; signal Inst_decodisa_dadrL_N4271 : STD_LOGIC; signal Inst_decodisa_dadrL_O_51_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4201 : STD_LOGIC; signal Inst_decodisa_dadrL_N4200 : STD_LOGIC; signal Inst_decodisa_dadrL_O_50_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4130 : STD_LOGIC; signal Inst_decodisa_dadrL_N4129 : STD_LOGIC; signal Inst_decodisa_dadrL_O_49_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N4059 : STD_LOGIC; signal Inst_decodisa_dadrL_N4058 : STD_LOGIC; signal Inst_decodisa_dadrL_O_48_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3988 : STD_LOGIC; signal Inst_decodisa_dadrL_N3987 : STD_LOGIC; signal Inst_decodisa_dadrL_O_47_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3917 : STD_LOGIC; signal Inst_decodisa_dadrL_N3916 : STD_LOGIC; signal Inst_decodisa_dadrL_O_46_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3846 : STD_LOGIC; signal Inst_decodisa_dadrL_N3845 : STD_LOGIC; signal Inst_decodisa_dadrL_O_45_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3775 : STD_LOGIC; signal Inst_decodisa_dadrL_N3774 : STD_LOGIC; signal Inst_decodisa_dadrL_O_44_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3704 : STD_LOGIC; signal Inst_decodisa_dadrL_N3703 : STD_LOGIC; signal Inst_decodisa_dadrL_O_43_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3633 : STD_LOGIC; signal Inst_decodisa_dadrL_N3632 : STD_LOGIC; signal Inst_decodisa_dadrL_O_42_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3562 : STD_LOGIC; signal Inst_decodisa_dadrL_N3561 : STD_LOGIC; signal Inst_decodisa_dadrL_O_41_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3491 : STD_LOGIC; signal Inst_decodisa_dadrL_N3490 : STD_LOGIC; signal Inst_decodisa_dadrL_O_40_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3420 : STD_LOGIC; signal Inst_decodisa_dadrL_N3419 : STD_LOGIC; signal Inst_decodisa_dadrL_O_39_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3349 : STD_LOGIC; signal Inst_decodisa_dadrL_N3348 : STD_LOGIC; signal Inst_decodisa_dadrL_O_38_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3278 : STD_LOGIC; signal Inst_decodisa_dadrL_N3277 : STD_LOGIC; signal Inst_decodisa_dadrL_O_37_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3207 : STD_LOGIC; signal Inst_decodisa_dadrL_N3206 : STD_LOGIC; signal Inst_decodisa_dadrL_O_36_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3136 : STD_LOGIC; signal Inst_decodisa_dadrL_N3135 : STD_LOGIC; signal Inst_decodisa_dadrL_O_35_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N3065 : STD_LOGIC; signal Inst_decodisa_dadrL_N3064 : STD_LOGIC; signal Inst_decodisa_dadrL_O_34_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2994 : STD_LOGIC; signal Inst_decodisa_dadrL_N2993 : STD_LOGIC; signal Inst_decodisa_dadrL_O_33_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2923 : STD_LOGIC; signal Inst_decodisa_dadrL_N2922 : STD_LOGIC; signal Inst_decodisa_dadrL_O_32_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2852 : STD_LOGIC; signal Inst_decodisa_dadrL_N2851 : STD_LOGIC; signal Inst_decodisa_dadrL_O_31_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2781 : STD_LOGIC; signal Inst_decodisa_dadrL_N2780 : STD_LOGIC; signal Inst_decodisa_dadrL_O_30_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2710 : STD_LOGIC; signal Inst_decodisa_dadrL_N2709 : STD_LOGIC; signal Inst_decodisa_dadrL_O_29_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2639 : STD_LOGIC; signal Inst_decodisa_dadrL_N2638 : STD_LOGIC; signal Inst_decodisa_dadrL_O_28_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2568 : STD_LOGIC; signal Inst_decodisa_dadrL_N2567 : STD_LOGIC; signal Inst_decodisa_dadrL_O_27_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2497 : STD_LOGIC; signal Inst_decodisa_dadrL_N2496 : STD_LOGIC; signal Inst_decodisa_dadrL_O_26_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2426 : STD_LOGIC; signal Inst_decodisa_dadrL_N2425 : STD_LOGIC; signal Inst_decodisa_dadrL_O_25_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2355 : STD_LOGIC; signal Inst_decodisa_dadrL_N2354 : STD_LOGIC; signal Inst_decodisa_dadrL_O_24_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2284 : STD_LOGIC; signal Inst_decodisa_dadrL_N2283 : STD_LOGIC; signal Inst_decodisa_dadrL_O_23_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2213 : STD_LOGIC; signal Inst_decodisa_dadrL_N2212 : STD_LOGIC; signal Inst_decodisa_dadrL_O_22_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2142 : STD_LOGIC; signal Inst_decodisa_dadrL_N2141 : STD_LOGIC; signal Inst_decodisa_dadrL_O_21_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2071 : STD_LOGIC; signal Inst_decodisa_dadrL_N2070 : STD_LOGIC; signal Inst_decodisa_dadrL_O_20_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N2000 : STD_LOGIC; signal Inst_decodisa_dadrL_N1999 : STD_LOGIC; signal Inst_decodisa_dadrL_O_19_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1929 : STD_LOGIC; signal Inst_decodisa_dadrL_N1928 : STD_LOGIC; signal Inst_decodisa_dadrL_O_18_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1858 : STD_LOGIC; signal Inst_decodisa_dadrL_N1857 : STD_LOGIC; signal Inst_decodisa_dadrL_O_17_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1787 : STD_LOGIC; signal Inst_decodisa_dadrL_N1786 : STD_LOGIC; signal Inst_decodisa_dadrL_O_16_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1716 : STD_LOGIC; signal Inst_decodisa_dadrL_N1715 : STD_LOGIC; signal Inst_decodisa_dadrL_O_15_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1645 : STD_LOGIC; signal Inst_decodisa_dadrL_N1644 : STD_LOGIC; signal Inst_decodisa_dadrL_O_14_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1574 : STD_LOGIC; signal Inst_decodisa_dadrL_N1573 : STD_LOGIC; signal Inst_decodisa_dadrL_O_13_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1503 : STD_LOGIC; signal Inst_decodisa_dadrL_N1502 : STD_LOGIC; signal Inst_decodisa_dadrL_O_12_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1432 : STD_LOGIC; signal Inst_decodisa_dadrL_N1431 : STD_LOGIC; signal Inst_decodisa_dadrL_O_11_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1361 : STD_LOGIC; signal Inst_decodisa_dadrL_N1360 : STD_LOGIC; signal Inst_decodisa_dadrL_O_10_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1290 : STD_LOGIC; signal Inst_decodisa_dadrL_N1289 : STD_LOGIC; signal Inst_decodisa_dadrL_O_9_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1219 : STD_LOGIC; signal Inst_decodisa_dadrL_N1218 : STD_LOGIC; signal Inst_decodisa_dadrL_O_8_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1148 : STD_LOGIC; signal Inst_decodisa_dadrL_N1147 : STD_LOGIC; signal Inst_decodisa_dadrL_O_7_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1077 : STD_LOGIC; signal Inst_decodisa_dadrL_N1076 : STD_LOGIC; signal Inst_decodisa_dadrL_N1006 : STD_LOGIC; signal Inst_decodisa_dadrL_N1005 : STD_LOGIC; signal Inst_decodisa_dadrL_N935 : STD_LOGIC; signal Inst_decodisa_dadrL_N934 : STD_LOGIC; signal Inst_decodisa_dadrL_N864 : STD_LOGIC; signal Inst_decodisa_dadrL_N863 : STD_LOGIC; signal Inst_decodisa_dadrL_N793 : STD_LOGIC; signal Inst_decodisa_dadrL_N792 : STD_LOGIC; signal Inst_decodisa_dadrL_N722 : STD_LOGIC; signal Inst_decodisa_dadrL_N721 : STD_LOGIC; signal Inst_decodisa_dadrL_N651 : STD_LOGIC; signal Inst_decodisa_dadrL_N650 : STD_LOGIC; signal Inst_decodisa_dadrL_O_0_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N580 : STD_LOGIC; signal Inst_decodisa_dadrL_N579 : STD_LOGIC; signal Inst_decodisa_dadrL_N0 : STD_LOGIC; signal clk_ref_BUFGP_IBUFG : STD_LOGIC; signal clk_speed_BUFGP_IBUFG : STD_LOGIC; signal rst_BUFGP_IBUFG : STD_LOGIC; signal GSR : STD_LOGIC; signal Inst_txserie1_RFLAG_REG_2_GSR_OR : STD_LOGIC; signal Inst_txserie1_RFLAG_REG_1_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_0_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RCONF_REG_0_GSR_OR : STD_LOGIC; signal Inst_rxserie1_FIFO1_wr_en_GSR_OR : STD_LOGIC; signal Inst_rxserie1_FIFO1_rd_en_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_6_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_5_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_4_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_3_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_2_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_1_GSR_OR : STD_LOGIC; signal Inst_txserie1_RFLAG_REG_3_GSR_OR : STD_LOGIC; signal Inst_txserie1_RCONF_REG_2_GSR_OR : STD_LOGIC; signal Inst_txserie1_RCONF_REG_7_GSR_OR : STD_LOGIC; signal Inst_txserie1_RCONF_REG_3_GSR_OR : STD_LOGIC; signal Inst_txserie1_RCONF_REG_5_GSR_OR : STD_LOGIC; signal Inst_txserie1_RCONF_REG_4_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RCONF_REG_7_GSR_OR : STD_LOGIC; signal Inst_txserie1_RCONF_REG_6_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RCONF_REG_6_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RCONF_REG_5_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RCONF_REG_4_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RCONF_REG_3_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RCONF_REG_2_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RCONF_REG_1_GSR_OR : STD_LOGIC; signal Inst_txserie1_RCONF_REG_1_GSR_OR : STD_LOGIC; signal Inst_txserie1_RFLAG_REG_0_GSR_OR : STD_LOGIC; signal Inst_txserie1_RCONF_REG_0_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_CNT_1_GSR_OR : STD_LOGIC; signal Inst_txserie1_FIFO1_wr_en_GSR_OR : STD_LOGIC; signal Inst_txserie1_FIFO1_rd_en_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_6_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_3_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_5_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_4_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_0_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_2_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_1_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_READ2_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_IDLE1_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_READ1_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_IDLE_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_HUNT_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RXCNT_1_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RX1_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RXCLK_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RXPARITY_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_PARITYGEN_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RXSTOP_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RSR_7_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RSR_6_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RSR_5_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RSR_4_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RSR_3_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RSR_2_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RSR_1_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RSR_0_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_7_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RXDATARDY_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_OVERRUN_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_PARITY_ERR_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RXCNT_3_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RXCNT_2_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RXCNT_0_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_ckout_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_9_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_8_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_0_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_1_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_2_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_3_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_4_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_5_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_6_GSR_OR : STD_LOGIC; signal Inst_txserie1_CLOCK1_compteur_7_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_ckout_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_9_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_8_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_1_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_2_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_3_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_4_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_5_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_6_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_7_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_THR_6_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_THR_5_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_THR_3_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TSR_0_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TSR_1_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_THR_4_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TXDONE1_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_WRITE1_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_WRITE2_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TXDATARDY_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_THR_7_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TXCLK_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TAG2_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TAG1_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TXPARITY_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TX_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TSR_7_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TSR_6_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TSR_5_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TSR_4_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TSR_3_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_TSR_2_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_THR_0_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_THR_1_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_THR_2_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_CNT_2_GSR_OR : STD_LOGIC; signal Inst_txserie1_TX1_CNT_0_GSR_OR : STD_LOGIC; signal GTS : STD_LOGIC; signal bus_data_0_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal bus_data_1_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal bus_data_2_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal bus_data_3_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal bus_data_4_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal bus_data_5_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal bus_data_6_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal bus_data_7_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal txout1_OBUF_GTS_TRI : STD_LOGIC; signal irqtx_OBUF_GTS_TRI : STD_LOGIC; signal irqrxFIFO_OBUF_GTS_TRI : STD_LOGIC; signal irqrxRX_OBUF_GTS_TRI : STD_LOGIC; signal irqrxERR_OBUF_GTS_TRI : STD_LOGIC; signal GND : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_0_T : STD_LOGIC; signal VCC : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_7_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_6_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_5_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_4_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_3_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_2_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_1_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_wr_en_C : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_rd_en_C : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_1_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_2_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_0_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RCONF_I1_1_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_7_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_6_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_5_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_4_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_3_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RCONF_I1_2_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RCONF_I1_0_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RCONF_I1_7_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RCONF_I1_6_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd2_C : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_1_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_2_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RCONF_I1_5_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_0_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RCONF_I1_4_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_7_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_6_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_5_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_4_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_3_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RCONF_I1_3_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd3_C : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd2_C : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd1_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd1_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_txload_G : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd4_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_FIFO1_wr_en_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_FIFO1_dready_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd3_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_FIFO1_rd_en_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_1_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_2_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd3_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_0_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_7_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_6_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_5_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_4_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_3_T : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd1_C : STD_LOGIC; signal NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd4_C : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C : STD_LOGIC; signal NLW_Inst_rxserie1_FIFO1_fifo0_BU161_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_rxserie1_FIFO1_fifo0_BU143_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_rxserie1_FIFO1_fifo0_BU137_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_rxserie1_FIFO1_fifo0_BU7_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_txserie1_FIFO1_fifo0_BU161_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_txserie1_FIFO1_fifo0_BU143_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_txserie1_FIFO1_fifo0_BU137_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_txserie1_FIFO1_fifo0_BU7_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_decodisa_dadrL_VCC_O_UNCONNECTED : STD_LOGIC; signal NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; signal NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; signal NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; signal NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; signal NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; signal NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; signal NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; signal NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; signal NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; signal NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; signal NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; signal NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; signal NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; signal NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; signal NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; signal NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; signal NlwInverterSignal_txout1_OBUF_GTS_TRI_CTL : STD_LOGIC; signal NlwInverterSignal_irqtx_OBUF_GTS_TRI_CTL : STD_LOGIC; signal NlwInverterSignal_irqrxFIFO_OBUF_GTS_TRI_CTL : STD_LOGIC; signal NlwInverterSignal_irqrxRX_OBUF_GTS_TRI_CTL : STD_LOGIC; signal NlwInverterSignal_irqrxERR_OBUF_GTS_TRI_CTL : STD_LOGIC; signal cs : STD_LOGIC_VECTOR ( 6 downto 1 ); signal Inst_txserie1_TX1_CNT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal Inst_txserie1_TX1_THR : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_txserie1_TX1_CNT_n0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); signal Inst_txserie1_inter_data : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_txserie1_fifoLevel : STD_LOGIC_VECTOR ( 1 downto 0 ); signal Inst_txserie1_RCONF_REG : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_rxserie1_RCONF_REG : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_rxserie1_inter_fifo : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_rxserie1_RC1_RHR : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_rxserie1_flagreg : STD_LOGIC_VECTOR ( 3 downto 0 ); signal Inst_txserie1_flagreg : STD_LOGIC_VECTOR ( 3 downto 2 ); signal Inst_rxserie1_RFLAG_output : STD_LOGIC_VECTOR ( 7 downto 7 ); signal Inst_rxserie1_RFLAG_REG : STD_LOGIC_VECTOR ( 6 downto 0 ); signal Inst_txserie1_RFLAG_REG : STD_LOGIC_VECTOR ( 3 downto 0 ); signal Inst_rxserie1_RC1_n0018 : STD_LOGIC_VECTOR ( 3 downto 0 ); signal Inst_rxserie1_RC1_RSR : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_rxserie1_RC1_n0040 : STD_LOGIC_VECTOR ( 3 downto 1 ); signal Inst_rxserie1_RC1_RXCNT : STD_LOGIC_VECTOR ( 3 downto 0 ); signal Inst_txserie1_CLOCK1_compteur_n0005 : STD_LOGIC_VECTOR ( 9 downto 0 ); signal Inst_txserie1_CLOCK1_compteur : STD_LOGIC_VECTOR ( 9 downto 0 ); signal Inst_txserie1_CLOCK1_compteur_n0001 : STD_LOGIC_VECTOR ( 9 downto 0 ); signal Inst_rxserie1_CLOCK1_compteur_n0005 : STD_LOGIC_VECTOR ( 9 downto 0 ); signal Inst_rxserie1_CLOCK1_compteur : STD_LOGIC_VECTOR ( 9 downto 0 ); signal Inst_rxserie1_CLOCK1_compteur_n0001 : STD_LOGIC_VECTOR ( 9 downto 0 ); signal Inst_txserie1_TX1_TSR : STD_LOGIC_VECTOR ( 7 downto 0 ); begin Inst_txserie1_RFLAG_REG_2 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_flagreg(2), CE => Inst_txserie1_RFLAG_n0007, RST => Inst_txserie1_RFLAG_REG_2_GSR_OR, SET => Inst_txserie1_flagreg(2), CLK => bus_clk, O => Inst_txserie1_RFLAG_REG(2) ); Inst_decodisa_n00021 : X_LUT3 generic map( INIT => X"F8" ) port map ( ADR0 => IOW_IBUF, ADR1 => IOR_IBUF, ADR2 => AEN_IBUF, O => bus_clk ); Inst_txserie1_FIFO1_state_write_FFd1_In1 : X_LUT3 generic map( INIT => X"BA" ) port map ( ADR0 => Inst_txserie1_FIFO1_state_write_FFd2, ADR1 => N8727, ADR2 => Inst_txserie1_FIFO1_state_write_FFd1, O => Inst_txserie1_FIFO1_state_write_FFd1_In ); XST_GND : X_ZERO port map ( O => Inst_rxserie1_RFLAG_output(7) ); Inst_txserie1_TX1_n0019_SW0 : X_LUT4 generic map( INIT => X"DC8C" ) port map ( ADR0 => Inst_txserie1_TX1_n0033, ADR1 => Inst_txserie1_TX1_TSR(0), ADR2 => Inst_txserie1_TX1_TSR(1), ADR3 => Inst_txserie1_TX1_TXPARITY, O => N14920 ); Inst_rxserie1_geneck1 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => Inst_rxserie1_RCONF_REG(4), ADR1 => clk_ref_BUFGP, O => Inst_rxserie1_geneck ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_5 : X_XOR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, O => Inst_rxserie1_CLOCK1_compteur_n0005(5) ); Inst_rxserie1_FIFO1_state_write_FFd2_In1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_rxserie1_rxread, ADR1 => Inst_rxserie1_FIFO1_state_write_FFd3, ADR2 => Inst_rxserie1_flagreg(2), O => Inst_rxserie1_FIFO1_state_write_FFd2_In ); Inst_rxserie1_irqFIFO1 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => Inst_rxserie1_flagreg(1), ADR1 => Inst_rxserie1_flagreg(0), O => irqrxFIFO_OBUF ); irqrxRX1 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_flagreg(3), O => irqrxRX_OBUF, ADR1 => GND ); Inst_rxserie1_irqERR1 : X_LUT4 generic map( INIT => X"FFFE" ) port map ( ADR0 => Inst_rxserie1_RC1_FRAMING_ERR, ADR1 => Inst_rxserie1_flagreg(2), ADR2 => Inst_rxserie1_RC1_PARITY_ERR, ADR3 => Inst_rxserie1_RC1_OVERRUN, O => irqrxERR_OBUF ); Inst_rxserie1_I7_0 : X_TRI port map ( I => Inst_rxserie1_inter_fifo(7), CTL => NlwInverterSignal_Inst_rxserie1_I7_0_T, O => bus_data_7_IOBUF ); XST_VCC : X_ONE port map ( O => N6239 ); Inst_txserie1_RFLAG_REG_1 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_fifoLevel(1), CE => Inst_txserie1_RFLAG_n0007, RST => Inst_txserie1_RFLAG_REG_1_GSR_OR, SET => Inst_txserie1_fifoLevel(1), CLK => bus_clk, O => Inst_txserie1_RFLAG_REG(1) ); Inst_rxserie1_rxread_0 : X_SFF generic map( INIT => '0' ) port map ( I => N6239, SRST => Inst_rxserie1_state_rx_read_FFd2, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_rxread, CE => VCC, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_state_rx_read_FFd3_1 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_state_rx_read_FFd3_In, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_state_rx_read_FFd3, CE => VCC, SET => GND, RST => GSR ); Inst_rxserie1_RC1_Madd_n0040_inst_cy_10_2 : X_MUX2 port map ( IB => Inst_rxserie1_RFLAG_output(7), IA => N6239, SEL => Inst_rxserie1_RC1_Madd_n0040_inst_lut2_10, O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10 ); Inst_rxserie1_RFLAG_REG_0 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_flagreg(0), CE => Inst_rxserie1_RFLAG_n0007, RST => Inst_rxserie1_RFLAG_REG_0_GSR_OR, SET => Inst_rxserie1_flagreg(0), CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(0) ); Inst_rxserie1_RCONF_REG_0 : X_FF generic map( INIT => '0' ) port map ( I => N15385, CE => Inst_rxserie1_RCONF_n0007, RST => Inst_rxserie1_RCONF_REG_0_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_rxserie1_RCONF_REG(0) ); Inst_rxserie1_I7_EnableTr_INV1 : X_LUT3 generic map( INIT => X"DF" ) port map ( ADR0 => cs(1), ADR1 => rst_BUFGP, ADR2 => rw, O => Inst_rxserie1_I7_N1528 ); Inst_rxserie1_I7_7 : X_TRI port map ( I => Inst_rxserie1_inter_fifo(0), CTL => NlwInverterSignal_Inst_rxserie1_I7_7_T, O => bus_data_0_IOBUF ); Inst_rxserie1_I7_6 : X_TRI port map ( I => Inst_rxserie1_inter_fifo(1), CTL => NlwInverterSignal_Inst_rxserie1_I7_6_T, O => bus_data_1_IOBUF ); Inst_rxserie1_I7_5 : X_TRI port map ( I => Inst_rxserie1_inter_fifo(2), CTL => NlwInverterSignal_Inst_rxserie1_I7_5_T, O => bus_data_2_IOBUF ); Inst_rxserie1_I7_4 : X_TRI port map ( I => Inst_rxserie1_inter_fifo(3), CTL => NlwInverterSignal_Inst_rxserie1_I7_4_T, O => bus_data_3_IOBUF ); Inst_rxserie1_I7_3 : X_TRI port map ( I => Inst_rxserie1_inter_fifo(4), CTL => NlwInverterSignal_Inst_rxserie1_I7_3_T, O => bus_data_4_IOBUF ); Inst_rxserie1_I7_2 : X_TRI port map ( I => Inst_rxserie1_inter_fifo(5), CTL => NlwInverterSignal_Inst_rxserie1_I7_2_T, O => bus_data_5_IOBUF ); Inst_rxserie1_I7_1 : X_TRI port map ( I => Inst_rxserie1_inter_fifo(6), CTL => NlwInverterSignal_Inst_rxserie1_I7_1_T, O => bus_data_6_IOBUF ); Inst_rxserie1_FIFO1_state_read_FFd3_In1 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => Inst_rxserie1_FIFO1_state_read_FFd4, ADR1 => rst_BUFGP, ADR2 => rw, ADR3 => cs(1), O => Inst_rxserie1_FIFO1_state_read_FFd3_In ); Inst_rxserie1_FIFO1_wr_en_3 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_FIFO1_state_write_FFd2_In, RST => Inst_rxserie1_FIFO1_wr_en_GSR_OR, CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_wr_en_C, O => Inst_rxserie1_FIFO1_wr_en, CE => VCC, SET => GND ); Inst_rxserie1_state_rx_read_FFd2_4 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_state_rx_read_FFd3, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_state_rx_read_FFd2, CE => VCC, SET => GND, RST => GSR ); Inst_rxserie1_FIFO1_state_read_FFd4_N16431 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => rst_BUFGP, O => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, ADR1 => GND ); Inst_txserie1_FIFO1_state_write_FFd3_In1 : X_LUT3 generic map( INIT => X"E0" ) port map ( ADR0 => Inst_txserie1_FIFO1_state_write_FFd3, ADR1 => Inst_txserie1_FIFO1_state_write_FFd1, ADR2 => N8727, O => Inst_txserie1_FIFO1_state_write_FFd3_In ); Inst_rxserie1_FIFO1_rd_en_5 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_FIFO1_state_read_FFd3_In, RST => Inst_rxserie1_FIFO1_rd_en_GSR_OR, CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_rd_en_C, O => Inst_rxserie1_FIFO1_rd_en, CE => VCC, SET => GND ); Inst_rxserie1_state_rx_read_FFd1_In11 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => Inst_rxserie1_RC1_RXDATARDY, ADR1 => Inst_rxserie1_state_rx_read_FFd1, O => N15406 ); Ker87251 : X_LUT4 generic map( INIT => X"FEFF" ) port map ( ADR0 => IOW_IBUF, ADR1 => AEN_IBUF, ADR2 => rst_BUFGP, ADR3 => cs(4), O => N8727 ); Inst_rxserie1_RFLAG_I1_1 : X_TRI port map ( I => Inst_rxserie1_RFLAG_REG(6), CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_1_T, O => bus_data_6_IOBUF ); Inst_rxserie1_RFLAG_I1_2 : X_TRI port map ( I => Inst_rxserie1_RFLAG_REG(5), CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_2_T, O => bus_data_5_IOBUF ); Inst_rxserie1_RFLAG_n00071 : X_LUT4 generic map( INIT => X"FB00" ) port map ( ADR0 => IOR_IBUF, ADR1 => IOW_IBUF, ADR2 => AEN_IBUF, ADR3 => cs(3), O => Inst_rxserie1_RFLAG_n0007 ); Inst_rxserie1_RFLAG_I1_0 : X_TRI port map ( I => Inst_rxserie1_RFLAG_output(7), CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_0_T, O => bus_data_7_IOBUF ); Inst_txserie1_RCONF_I1_1 : X_TRI port map ( I => Inst_txserie1_RCONF_REG(6), CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_1_T, O => bus_data_6_IOBUF ); Inst_rxserie1_RFLAG_I1_EnableTr_INV1 : X_LUT3 generic map( INIT => X"DF" ) port map ( ADR0 => cs(3), ADR1 => rst_BUFGP, ADR2 => rw, O => Inst_rxserie1_RFLAG_I1_N1528 ); Inst_rxserie1_RFLAG_I1_7 : X_TRI port map ( I => Inst_rxserie1_RFLAG_REG(0), CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_7_T, O => bus_data_0_IOBUF ); Inst_rxserie1_RFLAG_I1_6 : X_TRI port map ( I => Inst_rxserie1_RFLAG_REG(1), CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_6_T, O => bus_data_1_IOBUF ); Inst_rxserie1_RFLAG_I1_5 : X_TRI port map ( I => Inst_rxserie1_RFLAG_REG(2), CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_5_T, O => bus_data_2_IOBUF ); Inst_rxserie1_RFLAG_I1_4 : X_TRI port map ( I => Inst_rxserie1_RFLAG_REG(3), CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_4_T, O => bus_data_3_IOBUF ); Inst_rxserie1_RFLAG_I1_3 : X_TRI port map ( I => Inst_rxserie1_RFLAG_REG(4), CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_3_T, O => bus_data_4_IOBUF ); Inst_txserie1_RCONF_I1_2 : X_TRI port map ( I => Inst_txserie1_RCONF_REG(5), CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_2_T, O => bus_data_5_IOBUF ); Inst_rxserie1_RFLAG_REG_6_n00001 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_RC1_OVERRUN, O => Inst_rxserie1_RFLAG_REG_6_n0000, ADR1 => GND ); Inst_rxserie1_RFLAG_REG_0_n00001 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_flagreg(0), O => Inst_rxserie1_RFLAG_REG_0_n0000, ADR1 => GND ); Inst_rxserie1_RFLAG_REG_1_n00001 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_flagreg(1), O => Inst_rxserie1_RFLAG_REG_1_n0000, ADR1 => GND ); Inst_rxserie1_RFLAG_REG_2_n00001 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), O => Inst_rxserie1_RFLAG_REG_2_n0000, ADR1 => GND ); Inst_rxserie1_FIFO1_state_write_FFd1_6 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_FIFO1_state_write_FFd1_In, CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C, O => Inst_rxserie1_FIFO1_state_write_FFd1, SET => GND, RST => GSR ); Inst_rxserie1_RFLAG_REG_4_n00001 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_RC1_PARITY_ERR, O => Inst_rxserie1_RFLAG_REG_4_n0000, ADR1 => GND ); Inst_rxserie1_RFLAG_REG_5_n00001 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_RC1_FRAMING_ERR, O => Inst_rxserie1_RFLAG_REG_5_n0000, ADR1 => GND ); Inst_txserie1_RCONF_I1_0 : X_TRI port map ( I => Inst_txserie1_RCONF_REG(7), CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_0_T, O => bus_data_7_IOBUF ); Inst_rxserie1_state_rx_read_FFd4_7 : X_SFF generic map( INIT => '1' ) port map ( I => N6239, SRST => Inst_rxserie1_RC1_RXDATARDY, CE => Inst_rxserie1_state_rx_read_FFd1, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_state_rx_read_FFd4, SET => GSR, RST => GND, SSET => GND ); Inst_rxserie1_RFLAG_REG_6 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_OVERRUN, CE => Inst_rxserie1_RFLAG_n0007, RST => Inst_rxserie1_RFLAG_REG_6_GSR_OR, SET => Inst_rxserie1_RC1_OVERRUN, CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(6) ); Inst_rxserie1_state_rx_read_FFd3_In1 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => Inst_rxserie1_RC1_RXDATARDY, ADR1 => Inst_rxserie1_state_rx_read_FFd4, O => Inst_rxserie1_state_rx_read_FFd3_In ); Inst_rxserie1_RFLAG_REG_5 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_FRAMING_ERR, CE => Inst_rxserie1_RFLAG_n0007, RST => Inst_rxserie1_RFLAG_REG_5_GSR_OR, SET => Inst_rxserie1_RC1_FRAMING_ERR, CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(5) ); Inst_txserie1_RCONF_I1_EnableTr_INV1 : X_LUT3 generic map( INIT => X"DF" ) port map ( ADR0 => cs(5), ADR1 => rst_BUFGP, ADR2 => rw, O => Inst_txserie1_RCONF_I1_N1528 ); Inst_rxserie1_RFLAG_REG_4 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_PARITY_ERR, CE => Inst_rxserie1_RFLAG_n0007, RST => Inst_rxserie1_RFLAG_REG_4_GSR_OR, SET => Inst_rxserie1_RC1_PARITY_ERR, CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(4) ); Inst_txserie1_RCONF_I1_7 : X_TRI port map ( I => Inst_txserie1_RCONF_REG(0), CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_7_T, O => bus_data_0_IOBUF ); Inst_rxserie1_RFLAG_REG_3 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_flagreg(3), CE => Inst_rxserie1_RFLAG_n0007, RST => Inst_rxserie1_RFLAG_REG_3_GSR_OR, SET => Inst_rxserie1_flagreg(3), CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(3) ); Inst_txserie1_RCONF_I1_6 : X_TRI port map ( I => Inst_txserie1_RCONF_REG(1), CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_6_T, O => bus_data_1_IOBUF ); Inst_rxserie1_RFLAG_REG_2 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_flagreg(2), CE => Inst_rxserie1_RFLAG_n0007, RST => Inst_rxserie1_RFLAG_REG_2_GSR_OR, SET => Inst_rxserie1_flagreg(2), CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(2) ); Inst_rxserie1_FIFO1_state_write_FFd2_8 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_FIFO1_state_write_FFd2_In, CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C, O => Inst_rxserie1_FIFO1_state_write_FFd2, SET => GND, RST => GSR ); Inst_rxserie1_RFLAG_REG_1 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_flagreg(1), CE => Inst_rxserie1_RFLAG_n0007, RST => Inst_rxserie1_RFLAG_REG_1_GSR_OR, SET => Inst_rxserie1_flagreg(1), CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(1) ); Inst_txserie1_RFLAG_REG_3 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_flagreg(3), CE => Inst_txserie1_RFLAG_n0007, RST => Inst_txserie1_RFLAG_REG_3_GSR_OR, SET => Inst_txserie1_flagreg(3), CLK => bus_clk, O => Inst_txserie1_RFLAG_REG(3) ); Inst_txserie1_FIFO1_state_write_FFd2_9 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_FIFO1_state_write_FFd2_In, CE => Inst_txserie1_FIFO1_dready_N1514, CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd2_C, O => Inst_txserie1_FIFO1_state_write_FFd2, SET => GND, RST => GSR ); Inst_txserie1_RCONF_n00071 : X_LUT4 generic map( INIT => X"FB00" ) port map ( ADR0 => IOR_IBUF, ADR1 => IOW_IBUF, ADR2 => AEN_IBUF, ADR3 => cs(5), O => Inst_txserie1_RCONF_n0007 ); Inst_rxserie1_RCONF_I1_1 : X_TRI port map ( I => Inst_rxserie1_RCONF_REG(6), CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_1_T, O => bus_data_6_IOBUF ); Inst_rxserie1_RCONF_I1_2 : X_TRI port map ( I => Inst_rxserie1_RCONF_REG(5), CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_2_T, O => bus_data_5_IOBUF ); Inst_txserie1_RCONF_I1_5 : X_TRI port map ( I => Inst_txserie1_RCONF_REG(2), CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_5_T, O => bus_data_2_IOBUF ); Inst_rxserie1_RCONF_I1_0 : X_TRI port map ( I => Inst_rxserie1_RCONF_REG(7), CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_0_T, O => bus_data_7_IOBUF ); Inst_txserie1_RCONF_I1_4 : X_TRI port map ( I => Inst_txserie1_RCONF_REG(3), CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_4_T, O => bus_data_3_IOBUF ); Inst_rxserie1_RCONF_I1_EnableTr_INV1 : X_LUT3 generic map( INIT => X"DF" ) port map ( ADR0 => cs(2), ADR1 => rst_BUFGP, ADR2 => rw, O => Inst_rxserie1_RCONF_I1_N1528 ); Inst_rxserie1_RCONF_I1_7 : X_TRI port map ( I => Inst_rxserie1_RCONF_REG(0), CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_7_T, O => bus_data_0_IOBUF ); Inst_rxserie1_RCONF_I1_6 : X_TRI port map ( I => Inst_rxserie1_RCONF_REG(1), CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_6_T, O => bus_data_1_IOBUF ); Inst_rxserie1_RCONF_I1_5 : X_TRI port map ( I => Inst_rxserie1_RCONF_REG(2), CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_5_T, O => bus_data_2_IOBUF ); Inst_rxserie1_RCONF_I1_4 : X_TRI port map ( I => Inst_rxserie1_RCONF_REG(3), CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_4_T, O => bus_data_3_IOBUF ); Inst_rxserie1_RCONF_I1_3 : X_TRI port map ( I => Inst_rxserie1_RCONF_REG(4), CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_3_T, O => bus_data_4_IOBUF ); Inst_txserie1_RCONF_I1_3 : X_TRI port map ( I => Inst_txserie1_RCONF_REG(4), CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_3_T, O => bus_data_4_IOBUF ); Inst_rxserie1_state_rx_read_FFd1_10 : X_SFF generic map( INIT => '0' ) port map ( I => N15406, SSET => Inst_rxserie1_state_rx_read_FFd2, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_state_rx_read_FFd1, CE => VCC, SET => GND, RST => GSR, SRST => GND ); txout1_OBUF : X_BUF port map ( I => Inst_txserie1_TX1_TX, O => txout1_OBUF_GTS_TRI ); Inst_txserie1_RCONF_REG_2 : X_FF generic map( INIT => '0' ) port map ( I => N15389, CE => Inst_txserie1_RCONF_n0007, RST => Inst_txserie1_RCONF_REG_2_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_txserie1_RCONF_REG(2) ); Inst_txserie1_RCONF_REG_7 : X_FF generic map( INIT => '0' ) port map ( I => N15399, CE => Inst_txserie1_RCONF_n0007, RST => Inst_txserie1_RCONF_REG_7_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_txserie1_RCONF_REG(7) ); Inst_txserie1_RCONF_REG_3 : X_FF generic map( INIT => '0' ) port map ( I => N15391, CE => Inst_txserie1_RCONF_n0007, RST => Inst_txserie1_RCONF_REG_3_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_txserie1_RCONF_REG(3) ); Inst_txserie1_RCONF_REG_5 : X_FF generic map( INIT => '0' ) port map ( I => N15395, CE => Inst_txserie1_RCONF_n0007, RST => Inst_txserie1_RCONF_REG_5_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_txserie1_RCONF_REG(5) ); Inst_txserie1_RCONF_REG_4 : X_FF generic map( INIT => '0' ) port map ( I => N15393, CE => Inst_txserie1_RCONF_n0007, RST => Inst_txserie1_RCONF_REG_4_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_txserie1_RCONF_REG(4) ); Inst_rxserie1_RCONF_REG_7 : X_FF generic map( INIT => '0' ) port map ( I => N15399, CE => Inst_rxserie1_RCONF_n0007, RST => Inst_rxserie1_RCONF_REG_7_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_rxserie1_RCONF_REG(7) ); Inst_txserie1_RCONF_REG_6 : X_FF generic map( INIT => '0' ) port map ( I => N15397, CE => Inst_txserie1_RCONF_n0007, RST => Inst_txserie1_RCONF_REG_6_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_txserie1_RCONF_REG(6) ); Inst_rxserie1_RCONF_REG_6 : X_FF generic map( INIT => '0' ) port map ( I => N15397, CE => Inst_rxserie1_RCONF_n0007, RST => Inst_rxserie1_RCONF_REG_6_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_rxserie1_RCONF_REG(6) ); Inst_rxserie1_FIFO1_state_read_FFd3_11 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_FIFO1_state_read_FFd3_In, CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd3_C, O => Inst_rxserie1_FIFO1_state_read_FFd3, SET => GND, RST => GSR ); Inst_rxserie1_RCONF_REG_5 : X_FF generic map( INIT => '0' ) port map ( I => N15395, CE => Inst_rxserie1_RCONF_n0007, RST => Inst_rxserie1_RCONF_REG_5_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_rxserie1_RCONF_REG(5) ); Inst_rxserie1_FIFO1_state_read_FFd2_12 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_FIFO1_state_read_FFd3, CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd2_C, O => Inst_rxserie1_FIFO1_state_read_FFd2, SET => GND, RST => GSR ); Inst_rxserie1_RCONF_REG_4 : X_FF generic map( INIT => '0' ) port map ( I => N15393, CE => Inst_rxserie1_RCONF_n0007, RST => Inst_rxserie1_RCONF_REG_4_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_rxserie1_RCONF_REG(4) ); Inst_rxserie1_FIFO1_state_read_FFd1_13 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_FIFO1_state_read_FFd1_In, CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd1_C, O => Inst_rxserie1_FIFO1_state_read_FFd1, SET => GND, RST => GSR ); Inst_rxserie1_RCONF_REG_3 : X_FF generic map( INIT => '0' ) port map ( I => N15391, CE => Inst_rxserie1_RCONF_n0007, RST => Inst_rxserie1_RCONF_REG_3_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_rxserie1_RCONF_REG(3) ); Inst_rxserie1_FIFO1_state_read_FFd4_In1 : X_LUT4 generic map( INIT => X"AAA8" ) port map ( ADR0 => Inst_rxserie1_I7_N1528, ADR1 => Inst_rxserie1_FIFO1_state_read_FFd2, ADR2 => Inst_rxserie1_FIFO1_state_read_FFd4, ADR3 => Inst_rxserie1_FIFO1_state_read_FFd1, O => Inst_rxserie1_FIFO1_state_read_FFd4_In ); Inst_rxserie1_RCONF_REG_2 : X_FF generic map( INIT => '0' ) port map ( I => N15389, CE => Inst_rxserie1_RCONF_n0007, RST => Inst_rxserie1_RCONF_REG_2_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_rxserie1_RCONF_REG(2) ); Inst_txserie1_FIFO1_state_write_FFd1_14 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_FIFO1_state_write_FFd1_In, CE => Inst_txserie1_FIFO1_dready_N1514, CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd1_C, O => Inst_txserie1_FIFO1_state_write_FFd1, SET => GND, RST => GSR ); Inst_rxserie1_RCONF_REG_1 : X_FF generic map( INIT => '0' ) port map ( I => N15387, CE => Inst_rxserie1_RCONF_n0007, RST => Inst_rxserie1_RCONF_REG_1_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_rxserie1_RCONF_REG(1) ); Inst_txserie1_RCONF_REG_1 : X_FF generic map( INIT => '0' ) port map ( I => N15387, CE => Inst_txserie1_RCONF_n0007, RST => Inst_txserie1_RCONF_REG_1_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_txserie1_RCONF_REG(1) ); Inst_txserie1_TX1_n003410 : X_LUT4 generic map( INIT => X"FFFE" ) port map ( ADR0 => Inst_txserie1_TX1_TAG2, ADR1 => Inst_txserie1_TX1_TAG1, ADR2 => Inst_txserie1_TX1_TSR(7), ADR3 => Inst_txserie1_TX1_TSR(6), O => CHOICE144 ); Inst_rxserie1_CLOCK1_n000539 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(0), ADR1 => Inst_rxserie1_CLOCK1_compteur(1), ADR2 => N15425, ADR3 => CHOICE135, O => Inst_rxserie1_CLOCK1_n0005 ); Inst_txserie1_state_txload_2_SW18 : X_LUT4 generic map( INIT => X"EA00" ) port map ( ADR0 => Inst_txserie1_state_txload_2_Q, ADR1 => Inst_txserie1_FIFO1_dready, ADR2 => Inst_txserie1_state_txload_0_Q, ADR3 => CHOICE41, O => Inst_txserie1_state_txload_2_Q ); Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_2_1 : X_LUT4 generic map( INIT => X"10FE" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_n0005, ADR1 => rst_BUFGP, ADR2 => Inst_rxserie1_CLOCK1_compteur_n0005(2), ADR3 => Inst_rxserie1_RCONF_REG(1), O => Inst_rxserie1_CLOCK1_compteur_n0001(2) ); Inst_rxserie1_RCONF_n00071 : X_LUT4 generic map( INIT => X"FB00" ) port map ( ADR0 => IOR_IBUF, ADR1 => IOW_IBUF, ADR2 => AEN_IBUF, ADR3 => cs(2), O => Inst_rxserie1_RCONF_n0007 ); Inst_rxserie1_RC1_n0018_0_1 : X_LUT3 generic map( INIT => X"75" ) port map ( ADR0 => Inst_rxserie1_RC1_RXCNT(0), ADR1 => Inst_rxserie1_RC1_HUNT, ADR2 => Inst_rxserie1_RC1_IDLE, O => Inst_rxserie1_RC1_n0018(0) ); Inst_txserie1_FIFO1_state_write_FFd2_In1 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => N8727, ADR1 => Inst_txserie1_FIFO1_state_write_FFd3, O => Inst_txserie1_FIFO1_state_write_FFd2_In ); Inst_txserie1_minIRQ1 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => Inst_txserie1_flagreg(2), ADR1 => Inst_txserie1_RCONF_REG(2), O => irqtx_OBUF ); Inst_txserie1_fifopurge1 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_txserie1_RCONF_REG(3), O => Inst_txserie1_fifopurge ); Inst_txserie1_txload_15 : X_LATCHE generic map( INIT => '0' ) port map ( I => Inst_txserie1_n0010, CLK => NlwInverterSignal_Inst_txserie1_txload_G, O => Inst_txserie1_txload, GE => VCC, SET => GND, RST => GSR ); Inst_txserie1_RFLAG_REG_0 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_fifoLevel(0), CE => Inst_txserie1_RFLAG_n0007, RST => Inst_txserie1_RFLAG_REG_0_GSR_OR, SET => Inst_txserie1_fifoLevel(0), CLK => bus_clk, O => Inst_txserie1_RFLAG_REG(0) ); Inst_txserie1_RCONF_REG_0 : X_FF generic map( INIT => '0' ) port map ( I => N15385, CE => Inst_txserie1_RCONF_n0007, RST => Inst_txserie1_RCONF_REG_0_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => bus_clk, O => Inst_txserie1_RCONF_REG(0) ); Inst_txserie1_TX1_CNT_1 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_CNT_n0000(1), RST => Inst_txserie1_TX1_CNT_1_GSR_OR, CLK => Inst_txserie1_CLOCK1_ckout, O => Inst_txserie1_TX1_CNT(1), CE => VCC, SET => GND ); Inst_rxserie1_FIFO1_state_read_FFd4_16 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_FIFO1_state_read_FFd4_In, CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd4_C, O => Inst_rxserie1_FIFO1_state_read_FFd4, SET => GSR, RST => GND ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_5 : X_XOR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, O => Inst_txserie1_CLOCK1_compteur_n0005(5) ); Inst_txserie1_FIFO1_dready_N15141 : X_LUT2 generic map( INIT => X"1" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_txserie1_RCONF_REG(3), O => Inst_txserie1_FIFO1_dready_N1514 ); Inst_txserie1_FIFO1_wr_en_17 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_FIFO1_state_write_FFd2_In, RST => Inst_txserie1_FIFO1_wr_en_GSR_OR, CLK => NlwInverterSignal_Inst_txserie1_FIFO1_wr_en_C, O => Inst_txserie1_FIFO1_wr_en, CE => VCC, SET => GND ); Inst_txserie1_FIFO1_dready_18 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_FIFO1_state_read_FFd3, CE => Inst_txserie1_FIFO1_dready_N1514, CLK => NlwInverterSignal_Inst_txserie1_FIFO1_dready_C, O => Inst_txserie1_FIFO1_dready, SET => GND, RST => GSR ); Inst_txserie1_FIFO1_state_write_FFd3_19 : X_FF generic map( INIT => '1' ) port map ( I => Inst_txserie1_FIFO1_state_write_FFd3_In, CE => Inst_txserie1_FIFO1_dready_N1514, CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd3_C, O => Inst_txserie1_FIFO1_state_write_FFd3, SET => GSR, RST => GND ); Inst_rxserie1_FIFO1_state_write_FFd1_In1 : X_LUT4 generic map( INIT => X"FF10" ) port map ( ADR0 => Inst_rxserie1_rxread, ADR1 => Inst_rxserie1_flagreg(2), ADR2 => Inst_rxserie1_FIFO1_state_write_FFd1, ADR3 => Inst_rxserie1_FIFO1_state_write_FFd2, O => Inst_rxserie1_FIFO1_state_write_FFd1_In ); Inst_txserie1_FIFO1_rd_en_20 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_FIFO1_state_read_FFd3_In, RST => Inst_txserie1_FIFO1_rd_en_GSR_OR, CLK => NlwInverterSignal_Inst_txserie1_FIFO1_rd_en_C, O => Inst_txserie1_FIFO1_rd_en, CE => VCC, SET => GND ); Inst_rxserie1_FIFO1_state_write_FFd3_In1 : X_LUT4 generic map( INIT => X"EEE0" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), ADR1 => Inst_rxserie1_rxread, ADR2 => Inst_rxserie1_FIFO1_state_write_FFd1, ADR3 => Inst_rxserie1_FIFO1_state_write_FFd3, O => Inst_rxserie1_FIFO1_state_write_FFd3_In ); Inst_txserie1_n00101 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_state_txload_2_Q, ADR2 => Inst_txserie1_TX1_TXDATARDY, O => Inst_txserie1_n0010 ); Inst_txserie1_RFLAG_I1_1 : X_TRI port map ( I => Inst_rxserie1_RFLAG_output(7), CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_1_T, O => bus_data_6_IOBUF ); Inst_txserie1_RFLAG_I1_2 : X_TRI port map ( I => Inst_rxserie1_RFLAG_output(7), CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_2_T, O => bus_data_5_IOBUF ); Inst_txserie1_FIFO1_state_read_FFd3_21 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_FIFO1_state_read_FFd3_In, CE => Inst_txserie1_FIFO1_dready_N1514, CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd3_C, O => Inst_txserie1_FIFO1_state_read_FFd3, SET => GND, RST => GSR ); Inst_txserie1_RFLAG_I1_0 : X_TRI port map ( I => Inst_rxserie1_RFLAG_output(7), CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_0_T, O => bus_data_7_IOBUF ); irqtx_OBUF_22 : X_BUF port map ( I => irqtx_OBUF, O => irqtx_OBUF_GTS_TRI ); Inst_txserie1_RFLAG_I1_7 : X_TRI port map ( I => Inst_txserie1_RFLAG_REG(0), CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_7_T, O => bus_data_0_IOBUF ); Inst_txserie1_RFLAG_I1_6 : X_TRI port map ( I => Inst_txserie1_RFLAG_REG(1), CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_6_T, O => bus_data_1_IOBUF ); Inst_txserie1_RFLAG_I1_5 : X_TRI port map ( I => Inst_txserie1_RFLAG_REG(2), CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_5_T, O => bus_data_2_IOBUF ); Inst_txserie1_RFLAG_I1_4 : X_TRI port map ( I => Inst_txserie1_RFLAG_REG(3), CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_4_T, O => bus_data_3_IOBUF ); Inst_txserie1_RFLAG_I1_3 : X_TRI port map ( I => Inst_rxserie1_RFLAG_output(7), CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_3_T, O => bus_data_4_IOBUF ); Inst_txserie1_FIFO1_state_read_FFd1_23 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_FIFO1_state_read_FFd1_In, CE => Inst_txserie1_FIFO1_dready_N1514, CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd1_C, O => Inst_txserie1_FIFO1_state_read_FFd1, SET => GND, RST => GSR ); Inst_rxserie1_CLOCK1_n000539_SW0 : X_LUT4 generic map( INIT => X"FFFE" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(2), ADR1 => Inst_rxserie1_CLOCK1_compteur(3), ADR2 => Inst_rxserie1_CLOCK1_compteur(6), ADR3 => Inst_rxserie1_CLOCK1_compteur(7), O => N15425 ); Inst_txserie1_RFLAG_REG_0_n00001 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_fifoLevel(0), O => Inst_txserie1_RFLAG_REG_0_n0000, ADR1 => GND ); Inst_txserie1_RFLAG_REG_1_n00001 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_fifoLevel(1), O => Inst_txserie1_RFLAG_REG_1_n0000, ADR1 => GND ); Inst_txserie1_RFLAG_REG_2_n00001 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_flagreg(2), O => Inst_txserie1_RFLAG_REG_2_n0000, ADR1 => GND ); Inst_txserie1_RFLAG_REG_3_n00001 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_flagreg(3), O => Inst_txserie1_RFLAG_REG_3_n0000, ADR1 => GND ); Inst_txserie1_RFLAG_I1_EnableTr_INV1 : X_LUT3 generic map( INIT => X"DF" ) port map ( ADR0 => cs(6), ADR1 => rst_BUFGP, ADR2 => rw, O => Inst_txserie1_RFLAG_I1_N1528 ); Inst_txserie1_FIFO1_state_read_FFd4_24 : X_FF generic map( INIT => '1' ) port map ( I => Inst_txserie1_FIFO1_state_read_FFd4_In, CE => Inst_txserie1_FIFO1_dready_N1514, CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd4_C, O => Inst_txserie1_FIFO1_state_read_FFd4, SET => GSR, RST => GND ); Inst_rxserie1_FIFO1_state_write_FFd3_25 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_FIFO1_state_write_FFd3_In, CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C, O => Inst_rxserie1_FIFO1_state_write_FFd3, SET => GSR, RST => GND ); Inst_txserie1_FIFO1_state_read_FFd1_In1 : X_LUT4 generic map( INIT => X"0C08" ) port map ( ADR0 => Inst_txserie1_FIFO1_state_read_FFd1, ADR1 => Inst_txserie1_txready, ADR2 => Inst_txserie1_flagreg(3), ADR3 => Inst_txserie1_FIFO1_dready, O => Inst_txserie1_FIFO1_state_read_FFd1_In ); Inst_txserie1_CLOCK1_compteur_0_rt_26 : X_LUT2 generic map( INIT => X"A" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(0), O => Inst_txserie1_CLOCK1_compteur_0_rt, ADR1 => GND ); Inst_decodisa_n00031 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => IOR_IBUF, ADR1 => IOW_IBUF, ADR2 => AEN_IBUF, O => rw ); Inst_rxserie1_RC1_Madd_n0040_inst_cy_12_27 : X_MUX2 port map ( IB => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11, IA => Inst_rxserie1_RFLAG_output(7), SEL => Inst_rxserie1_RC1_RXCNT_2_rt, O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_12 ); Inst_rxserie1_RC1_Madd_n0040_inst_sum_12 : X_XOR2 port map ( I0 => Inst_rxserie1_RC1_RXCNT_2_rt, I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11, O => Inst_rxserie1_RC1_n0040(2) ); Inst_rxserie1_RC1_n00631 : X_LUT4 generic map( INIT => X"44F4" ) port map ( ADR0 => Inst_rxserie1_RC1_READ2, ADR1 => Inst_rxserie1_RC1_READ1, ADR2 => Inst_rxserie1_RC1_IDLE, ADR3 => Inst_rxserie1_RC1_IDLE1, O => Inst_rxserie1_RC1_n0063 ); Inst_rxserie1_RC1_n00621 : X_LUT3 generic map( INIT => X"BA" ) port map ( ADR0 => Inst_rxserie1_RC1_N10580, ADR1 => Inst_rxserie1_RC1_READ2, ADR2 => Inst_rxserie1_RC1_READ1, O => Inst_rxserie1_RC1_n0062 ); Inst_rxserie1_RC1_Ker105781 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE1, ADR1 => Inst_rxserie1_RC1_IDLE, ADR2 => Inst_rxserie1_RC1_RXDATARDY, O => Inst_rxserie1_RC1_N10580 ); Inst_txserie1_TX1_Mmux_n0020_Result1 : X_LUT4 generic map( INIT => X"DC8C" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TAG1, ADR2 => Inst_txserie1_TX1_TXDATARDY, ADR3 => Inst_txserie1_TX1_THR(7), O => Inst_txserie1_TX1_n0020 ); Inst_rxserie1_RC1_n00501 : X_LUT3 generic map( INIT => X"FD" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RX1, ADR2 => rxin1_IBUF, O => Inst_rxserie1_RC1_n0050 ); Inst_rxserie1_RC1_RHR_6 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_RSR(6), CE => Inst_rxserie1_RC1_N10580, RST => Inst_rxserie1_RC1_RHR_6_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RHR(6), SET => GND ); Inst_rxserie1_RC1_RHR_3 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_RSR(3), CE => Inst_rxserie1_RC1_N10580, RST => Inst_rxserie1_RC1_RHR_3_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RHR(3), SET => GND ); Inst_rxserie1_RC1_RHR_5 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_RSR(5), CE => Inst_rxserie1_RC1_N10580, RST => Inst_rxserie1_RC1_RHR_5_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RHR(5), SET => GND ); Inst_rxserie1_RC1_RHR_4 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_RSR(4), CE => Inst_rxserie1_RC1_N10580, RST => Inst_rxserie1_RC1_RHR_4_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RHR(4), SET => GND ); Inst_rxserie1_RC1_RHR_0 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_RSR(0), CE => Inst_rxserie1_RC1_N10580, RST => Inst_rxserie1_RC1_RHR_0_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RHR(0), SET => GND ); Inst_rxserie1_RC1_RHR_2 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_RSR(2), CE => Inst_rxserie1_RC1_N10580, RST => Inst_rxserie1_RC1_RHR_2_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RHR(2), SET => GND ); Inst_rxserie1_RC1_RHR_1 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_RSR(1), CE => Inst_rxserie1_RC1_N10580, RST => Inst_rxserie1_RC1_RHR_1_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RHR(1), SET => GND ); Inst_rxserie1_RC1_n00411 : X_LUT3 generic map( INIT => X"A2" ) port map ( ADR0 => Inst_rxserie1_RC1_RXDATARDY, ADR1 => Inst_rxserie1_RC1_READ1, ADR2 => Inst_rxserie1_RC1_READ2, O => Inst_rxserie1_RC1_n0041 ); Inst_rxserie1_RC1_READ2_28 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_READ1, SET => Inst_rxserie1_RC1_READ2_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_READ2, CE => VCC, RST => GND ); Inst_rxserie1_RC1_n00311 : X_LUT2 generic map( INIT => X"D" ) port map ( ADR0 => Inst_rxserie1_RC1_READ1, ADR1 => Inst_rxserie1_RC1_READ2, O => Inst_rxserie1_RC1_n0031 ); Inst_rxserie1_RC1_n0018_1_1 : X_LUT3 generic map( INIT => X"A2" ) port map ( ADR0 => Inst_rxserie1_RC1_n0040(1), ADR1 => Inst_rxserie1_RC1_IDLE, ADR2 => Inst_rxserie1_RC1_HUNT, O => Inst_rxserie1_RC1_n0018(1) ); Inst_rxserie1_RC1_n00361 : X_LUT3 generic map( INIT => X"40" ) port map ( ADR0 => rxin1_IBUF, ADR1 => Inst_rxserie1_RC1_IDLE, ADR2 => Inst_rxserie1_RC1_RX1, O => Inst_rxserie1_RC1_n0036 ); Inst_rxserie1_RC1_n00351 : X_LUT3 generic map( INIT => X"51" ) port map ( ADR0 => Inst_rxserie1_RC1_RXSTOP, ADR1 => Inst_rxserie1_RC1_READ1, ADR2 => Inst_rxserie1_RC1_READ2, O => Inst_rxserie1_RC1_n0035 ); Inst_rxserie1_RC1_n00341 : X_LUT3 generic map( INIT => X"A2" ) port map ( ADR0 => Inst_rxserie1_RC1_PARITYGEN, ADR1 => Inst_rxserie1_RC1_READ1, ADR2 => Inst_rxserie1_RC1_READ2, O => Inst_rxserie1_RC1_n0034 ); Inst_rxserie1_RC1_Madd_n0040_inst_cy_11_29 : X_MUX2 port map ( IB => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10, IA => Inst_rxserie1_RFLAG_output(7), SEL => Inst_rxserie1_RC1_RXCNT_1_rt, O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11 ); Inst_rxserie1_RC1_n00291 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RSR(1), O => Inst_rxserie1_RC1_n0029 ); Inst_rxserie1_RC1_n00281 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RSR(2), O => Inst_rxserie1_RC1_n0028 ); Inst_rxserie1_RC1_n00271 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RSR(3), O => Inst_rxserie1_RC1_n0027 ); Inst_rxserie1_RC1_n00261 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RSR(4), O => Inst_rxserie1_RC1_n0026 ); Inst_rxserie1_RC1_n00251 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RSR(5), O => Inst_rxserie1_RC1_n0025 ); Inst_rxserie1_RC1_n00241 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RSR(6), O => Inst_rxserie1_RC1_n0024 ); Inst_rxserie1_RC1_n00231 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RSR(7), O => Inst_rxserie1_RC1_n0023 ); Inst_rxserie1_RC1_n00221 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RXPARITY, O => Inst_rxserie1_RC1_n0022 ); Inst_rxserie1_RC1_n00211 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => rxin1_IBUF, O => Inst_rxserie1_RC1_n0021 ); Inst_rxserie1_RC1_n00201 : X_LUT3 generic map( INIT => X"F6" ) port map ( ADR0 => Inst_rxserie1_RC1_RXSTOP, ADR1 => Inst_rxserie1_RC1_PARITYGEN, ADR2 => Inst_rxserie1_RC1_IDLE, O => Inst_rxserie1_RC1_n0020 ); Inst_rxserie1_RC1_n00191 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RXSTOP, O => Inst_rxserie1_RC1_n0019 ); Inst_txserie1_TX1_n00481 : X_LUT4 generic map( INIT => X"8F88" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TXDONE1, ADR2 => Inst_txserie1_TX1_WRITE2, ADR3 => Inst_txserie1_TX1_WRITE1, O => Inst_txserie1_TX1_n0048 ); Inst_rxserie1_RC1_Madd_n0040_inst_sum_11 : X_XOR2 port map ( I0 => Inst_rxserie1_RC1_RXCNT_1_rt, I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10, O => Inst_rxserie1_RC1_n0040(1) ); Inst_rxserie1_RC1_n0018_2_1 : X_LUT3 generic map( INIT => X"A2" ) port map ( ADR0 => Inst_rxserie1_RC1_n0040(2), ADR1 => Inst_rxserie1_RC1_IDLE, ADR2 => Inst_rxserie1_RC1_HUNT, O => Inst_rxserie1_RC1_n0018(2) ); Inst_rxserie1_RC1_n0018_3_1 : X_LUT3 generic map( INIT => X"A2" ) port map ( ADR0 => Inst_rxserie1_RC1_n0040(3), ADR1 => Inst_rxserie1_RC1_IDLE, ADR2 => Inst_rxserie1_RC1_HUNT, O => Inst_rxserie1_RC1_n0018(3) ); Inst_rxserie1_RC1_IDLE1_30 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_IDLE, SET => Inst_rxserie1_RC1_IDLE1_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_IDLE1, CE => VCC, RST => GND ); Inst_rxserie1_RC1_n00151 : X_LUT2 generic map( INIT => X"1" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => Inst_rxserie1_RC1_RSR(0), O => Inst_rxserie1_RC1_n0015 ); Inst_rxserie1_RC1_READ1_31 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_rxread, SET => Inst_rxserie1_RC1_READ1_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_READ1, CE => VCC, RST => GND ); Inst_rxserie1_RC1_IDLE_32 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0015, SET => Inst_rxserie1_RC1_IDLE_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_IDLE, CE => VCC, RST => GND ); Inst_rxserie1_RC1_HUNT_33 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_n0036, CE => Inst_rxserie1_RC1_n0050, RST => Inst_rxserie1_RC1_HUNT_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_HUNT, SET => GND ); Inst_rxserie1_RC1_RXCNT_1 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_n0018(1), CE => Inst_rxserie1_RC1_n0051, RST => Inst_rxserie1_RC1_RXCNT_1_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RXCNT(1), SET => GND ); Inst_rxserie1_RC1_RX1_34 : X_FF generic map( INIT => '1' ) port map ( I => rxin1_IBUF, SET => Inst_rxserie1_RC1_RX1_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RX1, CE => VCC, RST => GND ); Inst_rxserie1_RC1_RXCLK_35 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_RXCNT(3), RST => Inst_rxserie1_RC1_RXCLK_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RXCLK, CE => VCC, SET => GND ); Inst_rxserie1_RC1_RXPARITY_36 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0019, SET => Inst_rxserie1_RC1_RXPARITY_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_RXPARITY, CE => VCC, RST => GND ); Inst_rxserie1_RC1_PARITYGEN_37 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0020, SET => Inst_rxserie1_RC1_PARITYGEN_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_PARITYGEN, CE => VCC, RST => GND ); Inst_rxserie1_RC1_RXSTOP_38 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_n0021, RST => Inst_rxserie1_RC1_RXSTOP_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_RXSTOP, CE => VCC, SET => GND ); Inst_rxserie1_RC1_RSR_7 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0022, SET => Inst_rxserie1_RC1_RSR_7_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_RSR(7), CE => VCC, RST => GND ); Inst_rxserie1_RC1_RSR_6 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0023, SET => Inst_rxserie1_RC1_RSR_6_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_RSR(6), CE => VCC, RST => GND ); Inst_rxserie1_RC1_RSR_5 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0024, SET => Inst_rxserie1_RC1_RSR_5_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_RSR(5), CE => VCC, RST => GND ); Inst_rxserie1_RC1_RSR_4 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0025, SET => Inst_rxserie1_RC1_RSR_4_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_RSR(4), CE => VCC, RST => GND ); Inst_rxserie1_RC1_RSR_3 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0026, SET => Inst_rxserie1_RC1_RSR_3_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_RSR(3), CE => VCC, RST => GND ); Inst_rxserie1_RC1_RSR_2 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0027, SET => Inst_rxserie1_RC1_RSR_2_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_RSR(2), CE => VCC, RST => GND ); Inst_rxserie1_RC1_RSR_1 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0028, SET => Inst_rxserie1_RC1_RSR_1_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_RSR(1), CE => VCC, RST => GND ); Inst_rxserie1_RC1_RSR_0 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0029, SET => Inst_rxserie1_RC1_RSR_0_GSR_OR, CLK => Inst_rxserie1_RC1_RXCLK, O => Inst_rxserie1_RC1_RSR(0), CE => VCC, RST => GND ); Inst_rxserie1_RC1_RHR_7 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_RSR(7), CE => Inst_rxserie1_RC1_N10580, RST => Inst_rxserie1_RC1_RHR_7_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RHR(7), SET => GND ); Inst_rxserie1_RC1_RXDATARDY_39 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_n0031, CE => Inst_rxserie1_RC1_n0062, RST => Inst_rxserie1_RC1_RXDATARDY_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RXDATARDY, SET => GND ); Inst_rxserie1_RC1_OVERRUN_40 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_n0041, CE => Inst_rxserie1_RC1_n0063, RST => Inst_rxserie1_RC1_OVERRUN_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_OVERRUN, SET => GND ); Inst_rxserie1_RC1_PARITY_ERR_41 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_n0034, CE => Inst_rxserie1_RC1_n0062, RST => Inst_rxserie1_RC1_PARITY_ERR_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_PARITY_ERR, SET => GND ); Inst_rxserie1_RC1_FRAMING_ERR_42 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_n0035, CE => Inst_rxserie1_RC1_n0062, RST => Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_FRAMING_ERR, SET => GND ); Inst_rxserie1_RC1_RXCNT_3 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_n0018(3), CE => Inst_rxserie1_RC1_n0051, RST => Inst_rxserie1_RC1_RXCNT_3_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RXCNT(3), SET => GND ); Inst_rxserie1_RC1_RXCNT_2 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_RC1_n0018(2), CE => Inst_rxserie1_RC1_n0051, RST => Inst_rxserie1_RC1_RXCNT_2_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RXCNT(2), SET => GND ); Inst_rxserie1_RC1_RXCNT_0 : X_FF generic map( INIT => '1' ) port map ( I => Inst_rxserie1_RC1_n0018(0), CE => Inst_rxserie1_RC1_n0051, SET => Inst_rxserie1_RC1_RXCNT_0_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_RC1_RXCNT(0), RST => GND ); irqrxFIFO_OBUF_43 : X_BUF port map ( I => irqrxFIFO_OBUF, O => irqrxFIFO_OBUF_GTS_TRI ); Inst_rxserie1_RC1_Madd_n0040_inst_sum_13 : X_XOR2 port map ( I0 => Inst_rxserie1_RC1_RXCNT_3_rt, I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_12, O => Inst_rxserie1_RC1_n0040(3) ); Inst_rxserie1_RC1_Madd_n0040_inst_lut2_101 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_RC1_RXCNT(0), O => Inst_rxserie1_RC1_Madd_n0040_inst_lut2_10, ADR1 => GND ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_8 : X_XOR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, O => Inst_txserie1_CLOCK1_compteur_n0005(8) ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8_44 : X_MUX2 port map ( IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, IA => Inst_txserie1_CLOCK1_compteur(8), SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8 ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_6 : X_XOR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, O => Inst_txserie1_CLOCK1_compteur_n0005(6) ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7_45 : X_MUX2 port map ( IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, IA => Inst_txserie1_CLOCK1_compteur(7), SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7 ); Inst_txserie1_CLOCK1_compteur_0_n00011 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_txserie1_CLOCK1_compteur_n0001(0), O => Inst_txserie1_CLOCK1_compteur_0_0_n0001 ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_7 : X_XOR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, O => Inst_txserie1_CLOCK1_compteur_n0005(7) ); Inst_txserie1_CLOCK1_n000539 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(4), ADR1 => Inst_txserie1_CLOCK1_compteur(5), ADR2 => N15429, ADR3 => CHOICE116, O => Inst_txserie1_CLOCK1_n0005 ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_61 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(6), O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, ADR1 => GND ); Inst_txserie1_CLOCK1_ckout_46 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_n0005, RST => Inst_txserie1_CLOCK1_ckout_GSR_OR, CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_ckout, CE => VCC, SET => GND ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_71 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(7), O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, ADR1 => GND ); Inst_txserie1_CLOCK1_compteur_n00061 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_txserie1_CLOCK1_n0005, ADR1 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_n0006 ); Inst_txserie1_FIFO1_state_read_FFd3_In1 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => Inst_txserie1_flagreg(3), ADR1 => Inst_txserie1_TX1_n0034, ADR2 => Inst_txserie1_TX1_TXDATARDY, ADR3 => Inst_txserie1_FIFO1_state_read_FFd4, O => Inst_txserie1_FIFO1_state_read_FFd3_In ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_91 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(9), O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, ADR1 => GND ); Inst_txserie1_CLOCK1_compteur_0_n00001 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur_n0001(0), ADR1 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_0_0_n0000 ); Inst_txserie1_CLOCK1_compteur_9 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_compteur_n0001(9), RST => Inst_txserie1_CLOCK1_compteur_9_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_compteur(9), CE => VCC ); Inst_txserie1_CLOCK1_compteur_8 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_compteur_n0001(8), RST => Inst_txserie1_CLOCK1_compteur_8_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_compteur(8), CE => VCC ); Inst_txserie1_CLOCK1_compteur_0 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_compteur_n0001(0), RST => Inst_txserie1_CLOCK1_compteur_0_GSR_OR, SET => Inst_txserie1_CLOCK1_compteur_0_0_n0001, CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_compteur(0), CE => VCC ); Inst_txserie1_CLOCK1_compteur_1 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_compteur_n0001(1), RST => Inst_txserie1_CLOCK1_compteur_1_GSR_OR, SET => Inst_txserie1_CLOCK1_compteur_0_1_n0001, CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_compteur(1), CE => VCC ); Inst_txserie1_CLOCK1_compteur_2 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_compteur_n0001(2), RST => Inst_txserie1_CLOCK1_compteur_2_GSR_OR, SET => Inst_txserie1_CLOCK1_compteur_0_2_n0001, CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_compteur(2), CE => VCC ); Inst_txserie1_CLOCK1_compteur_3 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_compteur_n0001(3), RST => Inst_txserie1_CLOCK1_compteur_3_GSR_OR, SET => Inst_txserie1_CLOCK1_compteur_0_3_n0001, CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_compteur(3), CE => VCC ); Inst_txserie1_CLOCK1_compteur_4 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_compteur_n0001(4), RST => Inst_txserie1_CLOCK1_compteur_4_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_compteur(4), CE => VCC ); Inst_txserie1_CLOCK1_compteur_5 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_compteur_n0001(5), RST => Inst_txserie1_CLOCK1_compteur_5_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_compteur(5), CE => VCC ); Inst_txserie1_CLOCK1_compteur_6 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_compteur_n0001(6), RST => Inst_txserie1_CLOCK1_compteur_6_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_compteur(6), CE => VCC ); Inst_txserie1_CLOCK1_compteur_7 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_CLOCK1_compteur_n0001(7), RST => Inst_txserie1_CLOCK1_compteur_7_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => clk_ref_BUFGP, O => Inst_txserie1_CLOCK1_compteur(7), CE => VCC ); Inst_txserie1_state_txload_2_SW15 : X_LUT3 generic map( INIT => X"01" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_txserie1_TX1_n0034, ADR2 => Inst_txserie1_TX1_TXDATARDY, O => CHOICE41 ); bus_adr_9_IBUF_47 : X_BUF port map ( I => bus_adr(9), O => bus_adr_9_IBUF ); irqrxRX_OBUF_48 : X_BUF port map ( I => irqrxRX_OBUF, O => irqrxRX_OBUF_GTS_TRI ); bus_adr_10_IBUF_49 : X_BUF port map ( I => bus_adr(10), O => bus_adr_10_IBUF ); irqrxERR_OBUF_50 : X_BUF port map ( I => irqrxERR_OBUF, O => irqrxERR_OBUF_GTS_TRI ); bus_adr_11_IBUF_51 : X_BUF port map ( I => bus_adr(11), O => bus_adr_11_IBUF ); bus_adr_0_IBUF_52 : X_BUF port map ( I => bus_adr(0), O => bus_adr_0_IBUF ); bus_adr_12_IBUF_53 : X_BUF port map ( I => bus_adr(12), O => bus_adr_12_IBUF ); bus_adr_1_IBUF_54 : X_BUF port map ( I => bus_adr(1), O => bus_adr_1_IBUF ); bus_adr_13_IBUF_55 : X_BUF port map ( I => bus_adr(13), O => bus_adr_13_IBUF ); bus_adr_2_IBUF_56 : X_BUF port map ( I => bus_adr(2), O => bus_adr_2_IBUF ); bus_adr_14_IBUF_57 : X_BUF port map ( I => bus_adr(14), O => bus_adr_14_IBUF ); Inst_txserie1_CLOCK1_compteur_3_n00011 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_txserie1_CLOCK1_compteur_n0001(3), O => Inst_txserie1_CLOCK1_compteur_0_3_n0001 ); Inst_txserie1_CLOCK1_compteur_3_n00001 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur_n0001(3), ADR1 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_0_3_n0000 ); bus_adr_15_IBUF_58 : X_BUF port map ( I => bus_adr(15), O => bus_adr_15_IBUF ); Inst_txserie1_CLOCK1_compteur_2_n00011 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_txserie1_RCONF_REG(1), ADR1 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_0_2_n0001 ); Inst_txserie1_CLOCK1_compteur_1_n00011 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_txserie1_CLOCK1_compteur_n0001(1), O => Inst_txserie1_CLOCK1_compteur_0_1_n0001 ); Inst_txserie1_CLOCK1_compteur_1_n00001 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur_n0001(1), ADR1 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_0_1_n0000 ); Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_0_1 : X_LUT4 generic map( INIT => X"E444" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur_n0006, ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(0), ADR2 => Inst_txserie1_RCONF_REG(1), ADR3 => Inst_txserie1_RCONF_REG(0), O => Inst_txserie1_CLOCK1_compteur_n0001(0) ); Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_1_1 : X_LUT4 generic map( INIT => X"4EE4" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur_n0006, ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(1), ADR2 => Inst_txserie1_RCONF_REG(0), ADR3 => Inst_txserie1_RCONF_REG(1), O => Inst_txserie1_CLOCK1_compteur_n0001(1) ); Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_4_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_n0005, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(4), ADR2 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_n0001(4) ); Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_3_1 : X_LUT4 generic map( INIT => X"444E" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur_n0006, ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(3), ADR2 => Inst_txserie1_RCONF_REG(1), ADR3 => Inst_txserie1_RCONF_REG(0), O => Inst_txserie1_CLOCK1_compteur_n0001(3) ); Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_5_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_n0005, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(5), ADR2 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_n0001(5) ); Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_6_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_n0005, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(6), ADR2 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_n0001(6) ); Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_7_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_n0005, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(7), ADR2 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_n0001(7) ); Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_8_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_n0005, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(8), ADR2 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_n0001(8) ); Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_9_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_n0005, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(9), ADR2 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_n0001(9) ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_81 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(8), O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, ADR1 => GND ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6_59 : X_MUX2 port map ( IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, IA => Inst_txserie1_CLOCK1_compteur(6), SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6 ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_9 : X_XOR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8, O => Inst_txserie1_CLOCK1_compteur_n0005(9) ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0_60 : X_MUX2 port map ( IB => N6239, IA => Inst_rxserie1_RFLAG_output(7), SEL => Inst_txserie1_CLOCK1_compteur_0_rt, O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0 ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_0 : X_XOR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_0_rt, I1 => N6239, O => Inst_txserie1_CLOCK1_compteur_n0005(0) ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_11 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(1), O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, ADR1 => GND ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1_61 : X_MUX2 port map ( IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, IA => Inst_txserie1_CLOCK1_compteur(1), SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1 ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_1 : X_XOR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, O => Inst_txserie1_CLOCK1_compteur_n0005(1) ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_21 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(2), O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, ADR1 => GND ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2_62 : X_MUX2 port map ( IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, IA => Inst_txserie1_CLOCK1_compteur(2), SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2 ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_2 : X_XOR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, O => Inst_txserie1_CLOCK1_compteur_n0005(2) ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_31 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(3), O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, ADR1 => GND ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3_63 : X_MUX2 port map ( IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, IA => Inst_txserie1_CLOCK1_compteur(3), SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3 ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_3 : X_XOR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, O => Inst_txserie1_CLOCK1_compteur_n0005(3) ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_41 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(4), O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, ADR1 => GND ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4_64 : X_MUX2 port map ( IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, IA => Inst_txserie1_CLOCK1_compteur(4), SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_4 : X_XOR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, O => Inst_txserie1_CLOCK1_compteur_n0005(4) ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_51 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(5), O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, ADR1 => GND ); Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5_65 : X_MUX2 port map ( IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, IA => Inst_txserie1_CLOCK1_compteur(5), SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_8 : X_XOR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, O => Inst_rxserie1_CLOCK1_compteur_n0005(8) ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8_66 : X_MUX2 port map ( IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, IA => Inst_rxserie1_CLOCK1_compteur(8), SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8 ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_6 : X_XOR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, O => Inst_rxserie1_CLOCK1_compteur_n0005(6) ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7_67 : X_MUX2 port map ( IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, IA => Inst_rxserie1_CLOCK1_compteur(7), SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7 ); Inst_rxserie1_CLOCK1_compteur_0_n00011 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(0), O => Inst_rxserie1_CLOCK1_compteur_0_0_n0001 ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_7 : X_XOR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, O => Inst_rxserie1_CLOCK1_compteur_n0005(7) ); Inst_txserie1_TX1_n003417 : X_LUT4 generic map( INIT => X"FFFE" ) port map ( ADR0 => CHOICE144, ADR1 => Inst_txserie1_TX1_TSR(5), ADR2 => Inst_txserie1_TX1_TSR(4), ADR3 => N15433, O => Inst_txserie1_TX1_n0034 ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_61 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(6), O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, ADR1 => GND ); Inst_rxserie1_CLOCK1_ckout_68 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_n0005, RST => Inst_rxserie1_CLOCK1_ckout_GSR_OR, CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_ckout, CE => VCC, SET => GND ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_71 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(7), O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, ADR1 => GND ); Inst_rxserie1_CLOCK1_compteur_n00061 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_n0005, ADR1 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_n0006 ); Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_9_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_txserie1_CLOCK1_n0005, ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(9), ADR2 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_n0001(9) ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_91 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(9), O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, ADR1 => GND ); Inst_rxserie1_CLOCK1_compteur_0_n00001 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(0), ADR1 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_0_0_n0000 ); Inst_rxserie1_CLOCK1_compteur_9 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_compteur_n0001(9), RST => Inst_rxserie1_CLOCK1_compteur_9_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_compteur(9), CE => VCC ); Inst_rxserie1_CLOCK1_compteur_8 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_compteur_n0001(8), RST => Inst_rxserie1_CLOCK1_compteur_8_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_compteur(8), CE => VCC ); Inst_rxserie1_CLOCK1_compteur_0 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_compteur_n0001(0), RST => Inst_rxserie1_CLOCK1_compteur_0_GSR_OR, SET => Inst_rxserie1_CLOCK1_compteur_0_0_n0001, CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_compteur(0), CE => VCC ); Inst_rxserie1_CLOCK1_compteur_1 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_compteur_n0001(1), RST => Inst_rxserie1_CLOCK1_compteur_1_GSR_OR, SET => Inst_rxserie1_CLOCK1_compteur_0_1_n0001, CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_compteur(1), CE => VCC ); Inst_rxserie1_CLOCK1_compteur_2 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_compteur_n0001(2), RST => Inst_rxserie1_CLOCK1_compteur_2_GSR_OR, SET => Inst_rxserie1_CLOCK1_compteur_0_2_n0001, CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_compteur(2), CE => VCC ); Inst_rxserie1_CLOCK1_compteur_3 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_compteur_n0001(3), RST => Inst_rxserie1_CLOCK1_compteur_3_GSR_OR, SET => Inst_rxserie1_CLOCK1_compteur_0_3_n0001, CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_compteur(3), CE => VCC ); Inst_rxserie1_CLOCK1_compteur_4 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_compteur_n0001(4), RST => Inst_rxserie1_CLOCK1_compteur_4_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_compteur(4), CE => VCC ); Inst_rxserie1_CLOCK1_compteur_5 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_compteur_n0001(5), RST => Inst_rxserie1_CLOCK1_compteur_5_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_compteur(5), CE => VCC ); Inst_rxserie1_CLOCK1_compteur_6 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_compteur_n0001(6), RST => Inst_rxserie1_CLOCK1_compteur_6_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_compteur(6), CE => VCC ); Inst_rxserie1_CLOCK1_compteur_7 : X_FF generic map( INIT => '0' ) port map ( I => Inst_rxserie1_CLOCK1_compteur_n0001(7), RST => Inst_rxserie1_CLOCK1_compteur_7_GSR_OR, SET => Inst_rxserie1_RFLAG_output(7), CLK => Inst_rxserie1_geneck, O => Inst_rxserie1_CLOCK1_compteur(7), CE => VCC ); bus_adr_3_IBUF_69 : X_BUF port map ( I => bus_adr(3), O => bus_adr_3_IBUF ); Inst_txserie1_CLOCK1_compteur_2_n00001 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_txserie1_RCONF_REG(1), O => Inst_txserie1_CLOCK1_compteur_0_2_n0000 ); bus_adr_4_IBUF_70 : X_BUF port map ( I => bus_adr(4), O => bus_adr_4_IBUF ); IOW_IBUF_71 : X_BUF port map ( I => IOW, O => IOW_IBUF ); bus_adr_5_IBUF_72 : X_BUF port map ( I => bus_adr(5), O => bus_adr_5_IBUF ); IOR_IBUF_73 : X_BUF port map ( I => IOR, O => IOR_IBUF ); bus_adr_6_IBUF_74 : X_BUF port map ( I => bus_adr(6), O => bus_adr_6_IBUF ); AEN_IBUF_75 : X_BUF port map ( I => AEN, O => AEN_IBUF ); bus_adr_7_IBUF_76 : X_BUF port map ( I => bus_adr(7), O => bus_adr_7_IBUF ); rxin1_IBUF_77 : X_BUF port map ( I => rxin1, O => rxin1_IBUF ); bus_adr_8_IBUF_78 : X_BUF port map ( I => bus_adr(8), O => bus_adr_8_IBUF ); Inst_rxserie1_CLOCK1_compteur_3_n00011 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(3), O => Inst_rxserie1_CLOCK1_compteur_0_3_n0001 ); Inst_rxserie1_CLOCK1_compteur_3_n00001 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(3), ADR1 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_0_3_n0000 ); Inst_rxserie1_CLOCK1_compteur_2_n00011 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_rxserie1_RCONF_REG(1), ADR1 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_0_2_n0001 ); Inst_rxserie1_CLOCK1_compteur_1_n00011 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(1), O => Inst_rxserie1_CLOCK1_compteur_0_1_n0001 ); Inst_rxserie1_CLOCK1_compteur_1_n00001 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(1), ADR1 => rst_BUFGP, O => Inst_rxserie1_CLOCK1_compteur_0_1_n0000 ); Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_0_1 : X_LUT4 generic map( INIT => X"E444" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(0), ADR2 => Inst_rxserie1_RCONF_REG(1), ADR3 => Inst_rxserie1_RCONF_REG(0), O => Inst_rxserie1_CLOCK1_compteur_n0001(0) ); Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_1_1 : X_LUT4 generic map( INIT => X"4EE4" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(1), ADR2 => Inst_rxserie1_RCONF_REG(0), ADR3 => Inst_rxserie1_RCONF_REG(1), O => Inst_rxserie1_CLOCK1_compteur_n0001(1) ); Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_2_1 : X_LUT4 generic map( INIT => X"10FE" ) port map ( ADR0 => Inst_txserie1_CLOCK1_n0005, ADR1 => rst_BUFGP, ADR2 => Inst_txserie1_CLOCK1_compteur_n0005(2), ADR3 => Inst_txserie1_RCONF_REG(1), O => Inst_txserie1_CLOCK1_compteur_n0001(2) ); Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_3_1 : X_LUT4 generic map( INIT => X"444E" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(3), ADR2 => Inst_rxserie1_RCONF_REG(1), ADR3 => Inst_rxserie1_RCONF_REG(0), O => Inst_rxserie1_CLOCK1_compteur_n0001(3) ); Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_4_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_txserie1_CLOCK1_n0005, ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(4), ADR2 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_n0001(4) ); Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_5_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_txserie1_CLOCK1_n0005, ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(5), ADR2 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_n0001(5) ); Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_6_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_txserie1_CLOCK1_n0005, ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(6), ADR2 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_n0001(6) ); Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_7_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_txserie1_CLOCK1_n0005, ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(7), ADR2 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_n0001(7) ); Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_8_1 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => Inst_txserie1_CLOCK1_n0005, ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(8), ADR2 => rst_BUFGP, O => Inst_txserie1_CLOCK1_compteur_n0001(8) ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_81 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(8), O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, ADR1 => GND ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6_79 : X_MUX2 port map ( IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, IA => Inst_rxserie1_CLOCK1_compteur(6), SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6 ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_9 : X_XOR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8, O => Inst_rxserie1_CLOCK1_compteur_n0005(9) ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0_80 : X_MUX2 port map ( IB => N6239, IA => Inst_rxserie1_RFLAG_output(7), SEL => Inst_rxserie1_CLOCK1_compteur_0_rt, O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0 ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_0 : X_XOR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_0_rt, I1 => N6239, O => Inst_rxserie1_CLOCK1_compteur_n0005(0) ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_11 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(1), O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, ADR1 => GND ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1_81 : X_MUX2 port map ( IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, IA => Inst_rxserie1_CLOCK1_compteur(1), SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1 ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_1 : X_XOR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, O => Inst_rxserie1_CLOCK1_compteur_n0005(1) ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_21 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(2), O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, ADR1 => GND ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2_82 : X_MUX2 port map ( IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, IA => Inst_rxserie1_CLOCK1_compteur(2), SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2 ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_2 : X_XOR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, O => Inst_rxserie1_CLOCK1_compteur_n0005(2) ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_31 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(3), O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, ADR1 => GND ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3_83 : X_MUX2 port map ( IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, IA => Inst_rxserie1_CLOCK1_compteur(3), SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3 ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_3 : X_XOR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, O => Inst_rxserie1_CLOCK1_compteur_n0005(3) ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_41 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(4), O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, ADR1 => GND ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4_84 : X_MUX2 port map ( IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, IA => Inst_rxserie1_CLOCK1_compteur(4), SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_4 : X_XOR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, O => Inst_rxserie1_CLOCK1_compteur_n0005(4) ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_51 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(5), O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, ADR1 => GND ); Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5_85 : X_MUX2 port map ( IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, IA => Inst_rxserie1_CLOCK1_compteur(5), SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 ); Inst_rxserie1_RC1_n00511 : X_LUT3 generic map( INIT => X"DF" ) port map ( ADR0 => Inst_rxserie1_RC1_IDLE, ADR1 => rxin1_IBUF, ADR2 => Inst_rxserie1_RC1_RX1, O => Inst_rxserie1_RC1_n0051 ); Inst_txserie1_TX1_n00391 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_n0039, ADR1 => GND ); Inst_txserie1_TX1_THR_6 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_inter_data(6), RST => Inst_txserie1_TX1_THR_6_GSR_OR, CLK => Inst_txserie1_txload, O => Inst_txserie1_TX1_THR(6), CE => VCC, SET => GND ); Inst_txserie1_TX1_THR_5 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_inter_data(5), RST => Inst_txserie1_TX1_THR_5_GSR_OR, CLK => Inst_txserie1_txload, O => Inst_txserie1_TX1_THR(5), CE => VCC, SET => GND ); Inst_txserie1_TX1_THR_3 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_inter_data(3), RST => Inst_txserie1_TX1_THR_3_GSR_OR, CLK => Inst_txserie1_txload, O => Inst_txserie1_TX1_THR(3), CE => VCC, SET => GND ); Inst_rxserie1_CLOCK1_n000529 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(8), ADR1 => Inst_rxserie1_CLOCK1_compteur(9), ADR2 => Inst_rxserie1_CLOCK1_compteur(4), ADR3 => Inst_rxserie1_CLOCK1_compteur(5), O => CHOICE135 ); Inst_txserie1_TX1_n00339 : X_LUT4 generic map( INIT => X"FFFE" ) port map ( ADR0 => Inst_txserie1_TX1_TSR(3), ADR1 => Inst_txserie1_TX1_TSR(2), ADR2 => Inst_txserie1_TX1_TAG2, ADR3 => Inst_txserie1_TX1_TAG1, O => CHOICE98 ); Inst_txserie1_TX1_n00321 : X_LUT3 generic map( INIT => X"01" ) port map ( ADR0 => Inst_txserie1_TX1_CNT(2), ADR1 => Inst_txserie1_TX1_CNT(0), ADR2 => Inst_txserie1_TX1_CNT(1), O => Inst_txserie1_TX1_n0032 ); Inst_txserie1_TX1_n00311 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_txserie1_TX1_WRITE2, ADR1 => Inst_txserie1_TX1_WRITE1, O => Inst_txserie1_TX1_n0031 ); Inst_txserie1_TX1_n00301 : X_LUT2 generic map( INIT => X"4" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TXDATARDY, O => Inst_txserie1_TX1_n0030 ); Inst_txserie1_TX1_TSR_0 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0027, RST => Inst_txserie1_TX1_TSR_0_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TSR(0), CE => VCC, SET => GND ); Inst_rxserie1_RC1_RXCNT_3_rt_86 : X_LUT2 generic map( INIT => X"A" ) port map ( ADR0 => Inst_rxserie1_RC1_RXCNT(3), O => Inst_rxserie1_RC1_RXCNT_3_rt, ADR1 => GND ); Inst_rxserie1_RC1_RXCNT_2_rt_87 : X_LUT2 generic map( INIT => X"A" ) port map ( ADR0 => Inst_rxserie1_RC1_RXCNT(2), O => Inst_rxserie1_RC1_RXCNT_2_rt, ADR1 => GND ); Inst_txserie1_TX1_n00181 : X_LUT4 generic map( INIT => X"6F66" ) port map ( ADR0 => Inst_txserie1_TX1_TSR(0), ADR1 => Inst_txserie1_TX1_TXPARITY, ADR2 => Inst_txserie1_TX1_n0034, ADR3 => Inst_txserie1_TX1_TXDATARDY, O => Inst_txserie1_TX1_n0018 ); Inst_txserie1_TX1_TSR_1 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0026, RST => Inst_txserie1_TX1_TSR_1_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TSR(1), CE => VCC, SET => GND ); Inst_txserie1_TX1_TXRDY1 : X_LUT2 generic map( INIT => X"1" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TXDATARDY, O => Inst_txserie1_txready ); Inst_rxserie1_CLOCK1_compteur_2_n00001 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => rst_BUFGP, ADR1 => Inst_rxserie1_RCONF_REG(1), O => Inst_rxserie1_CLOCK1_compteur_0_2_n0000 ); Inst_txserie1_TX1_THR_4 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_inter_data(4), RST => Inst_txserie1_TX1_THR_4_GSR_OR, CLK => Inst_txserie1_txload, O => Inst_txserie1_TX1_THR(4), CE => VCC, SET => GND ); Inst_txserie1_TX1_CNT_Madd_n0000_n00061 : X_LUT2 generic map( INIT => X"5" ) port map ( ADR0 => Inst_txserie1_TX1_CNT(0), O => Inst_txserie1_TX1_CNT_n0000(0), ADR1 => GND ); Inst_txserie1_TX1_n00171 : X_LUT3 generic map( INIT => X"BA" ) port map ( ADR0 => Inst_txserie1_TX1_TAG2, ADR1 => Inst_txserie1_TX1_n0034, ADR2 => Inst_txserie1_TX1_TXDATARDY, O => Inst_txserie1_TX1_n0017 ); Inst_txserie1_TX1_Mmux_n0027_Result1 : X_LUT4 generic map( INIT => X"DC8C" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TSR(1), ADR2 => Inst_txserie1_TX1_TXDATARDY, ADR3 => Inst_txserie1_TX1_THR(0), O => Inst_txserie1_TX1_n0027 ); Inst_txserie1_TX1_Mmux_n0026_Result1 : X_LUT4 generic map( INIT => X"DC8C" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TSR(2), ADR2 => Inst_txserie1_TX1_TXDATARDY, ADR3 => Inst_txserie1_TX1_THR(1), O => Inst_txserie1_TX1_n0026 ); Inst_txserie1_TX1_Mmux_n0025_Result1 : X_LUT4 generic map( INIT => X"DC8C" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TSR(3), ADR2 => Inst_txserie1_TX1_TXDATARDY, ADR3 => Inst_txserie1_TX1_THR(2), O => Inst_txserie1_TX1_n0025 ); Inst_txserie1_TX1_Mmux_n0024_Result1 : X_LUT4 generic map( INIT => X"DC8C" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TSR(4), ADR2 => Inst_txserie1_TX1_TXDATARDY, ADR3 => Inst_txserie1_TX1_THR(3), O => Inst_txserie1_TX1_n0024 ); Inst_txserie1_TX1_Mmux_n0023_Result1 : X_LUT4 generic map( INIT => X"DC8C" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TSR(5), ADR2 => Inst_txserie1_TX1_TXDATARDY, ADR3 => Inst_txserie1_TX1_THR(4), O => Inst_txserie1_TX1_n0023 ); Inst_txserie1_TX1_Mmux_n0022_Result1 : X_LUT4 generic map( INIT => X"DC8C" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TSR(6), ADR2 => Inst_txserie1_TX1_TXDATARDY, ADR3 => Inst_txserie1_TX1_THR(5), O => Inst_txserie1_TX1_n0022 ); Inst_txserie1_TX1_Mmux_n0021_Result1 : X_LUT4 generic map( INIT => X"DC8C" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => Inst_txserie1_TX1_TSR(7), ADR2 => Inst_txserie1_TX1_TXDATARDY, ADR3 => Inst_txserie1_TX1_THR(6), O => Inst_txserie1_TX1_n0021 ); Inst_txserie1_TX1_TXDONE1_88 : X_FF generic map( INIT => '1' ) port map ( I => Inst_txserie1_TX1_TXDONE, SET => Inst_txserie1_TX1_TXDONE1_GSR_OR, CLK => Inst_txserie1_CLOCK1_ckout, O => Inst_txserie1_TX1_TXDONE1, CE => VCC, RST => GND ); Inst_txserie1_TX1_WRITE1_89 : X_FF generic map( INIT => '1' ) port map ( I => Inst_txserie1_txload, SET => Inst_txserie1_TX1_WRITE1_GSR_OR, CLK => Inst_txserie1_CLOCK1_ckout, O => Inst_txserie1_TX1_WRITE1, CE => VCC, RST => GND ); Inst_txserie1_TX1_WRITE2_90 : X_FF generic map( INIT => '1' ) port map ( I => Inst_txserie1_TX1_WRITE1, SET => Inst_txserie1_TX1_WRITE2_GSR_OR, CLK => Inst_txserie1_CLOCK1_ckout, O => Inst_txserie1_TX1_WRITE2, CE => VCC, RST => GND ); Inst_txserie1_TX1_TXDATARDY_91 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0031, CE => Inst_txserie1_TX1_n0048, RST => Inst_txserie1_TX1_TXDATARDY_GSR_OR, CLK => Inst_txserie1_CLOCK1_ckout, O => Inst_txserie1_TX1_TXDATARDY, SET => GND ); Inst_txserie1_TX1_THR_7 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_inter_data(7), RST => Inst_txserie1_TX1_THR_7_GSR_OR, CLK => Inst_txserie1_txload, O => Inst_txserie1_TX1_THR(7), CE => VCC, SET => GND ); Inst_txserie1_TX1_TXCLK_92 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0039, CE => Inst_txserie1_TX1_n0032, RST => Inst_txserie1_TX1_TXCLK_GSR_OR, CLK => Inst_txserie1_CLOCK1_ckout, O => Inst_txserie1_TX1_TXCLK, SET => GND ); Inst_txserie1_TX1_CNT_Madd_n0000_Mxor_Result_2_Result1 : X_LUT3 generic map( INIT => X"6A" ) port map ( ADR0 => Inst_txserie1_TX1_CNT(2), ADR1 => Inst_txserie1_TX1_CNT(0), ADR2 => Inst_txserie1_TX1_CNT(1), O => Inst_txserie1_TX1_CNT_n0000(2) ); Inst_txserie1_TX1_TAG2_93 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0030, RST => Inst_txserie1_TX1_TAG2_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TAG2, CE => VCC, SET => GND ); Inst_txserie1_TX1_TAG1_94 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0017, RST => Inst_txserie1_TX1_TAG1_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TAG1, CE => VCC, SET => GND ); Inst_txserie1_TX1_TXPARITY_95 : X_FF generic map( INIT => '1' ) port map ( I => Inst_txserie1_TX1_n0018, SET => Inst_txserie1_TX1_TXPARITY_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TXPARITY, CE => VCC, RST => GND ); Inst_txserie1_TX1_TX_96 : X_FF generic map( INIT => '1' ) port map ( I => Inst_txserie1_TX1_n0019, SET => Inst_txserie1_TX1_TX_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TX, CE => VCC, RST => GND ); Inst_txserie1_TX1_TSR_7 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0020, RST => Inst_txserie1_TX1_TSR_7_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TSR(7), CE => VCC, SET => GND ); Inst_txserie1_TX1_TSR_6 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0021, RST => Inst_txserie1_TX1_TSR_6_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TSR(6), CE => VCC, SET => GND ); Inst_txserie1_TX1_TSR_5 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0022, RST => Inst_txserie1_TX1_TSR_5_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TSR(5), CE => VCC, SET => GND ); Inst_txserie1_TX1_TSR_4 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0023, RST => Inst_txserie1_TX1_TSR_4_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TSR(4), CE => VCC, SET => GND ); Inst_txserie1_TX1_TSR_3 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0024, RST => Inst_txserie1_TX1_TSR_3_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TSR(3), CE => VCC, SET => GND ); Inst_txserie1_TX1_TSR_2 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_n0025, RST => Inst_txserie1_TX1_TSR_2_GSR_OR, CLK => Inst_txserie1_TX1_TXCLK, O => Inst_txserie1_TX1_TSR(2), CE => VCC, SET => GND ); Inst_txserie1_TX1_THR_0 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_inter_data(0), RST => Inst_txserie1_TX1_THR_0_GSR_OR, CLK => Inst_txserie1_txload, O => Inst_txserie1_TX1_THR(0), CE => VCC, SET => GND ); Inst_txserie1_TX1_THR_1 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_inter_data(1), RST => Inst_txserie1_TX1_THR_1_GSR_OR, CLK => Inst_txserie1_txload, O => Inst_txserie1_TX1_THR(1), CE => VCC, SET => GND ); Inst_txserie1_TX1_THR_2 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_inter_data(2), RST => Inst_txserie1_TX1_THR_2_GSR_OR, CLK => Inst_txserie1_txload, O => Inst_txserie1_TX1_THR(2), CE => VCC, SET => GND ); Inst_txserie1_TX1_CNT_2 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_CNT_n0000(2), RST => Inst_txserie1_TX1_CNT_2_GSR_OR, CLK => Inst_txserie1_CLOCK1_ckout, O => Inst_txserie1_TX1_CNT(2), CE => VCC, SET => GND ); Inst_txserie1_TX1_CNT_Madd_n0000_Mxor_Result_1_Result1 : X_LUT2 generic map( INIT => X"6" ) port map ( ADR0 => Inst_txserie1_TX1_CNT(0), ADR1 => Inst_txserie1_TX1_CNT(1), O => Inst_txserie1_TX1_CNT_n0000(1) ); Inst_txserie1_TX1_CNT_0 : X_FF generic map( INIT => '0' ) port map ( I => Inst_txserie1_TX1_CNT_n0000(0), RST => Inst_txserie1_TX1_CNT_0_GSR_OR, CLK => Inst_txserie1_CLOCK1_ckout, O => Inst_txserie1_TX1_CNT(0), CE => VCC, SET => GND ); Inst_txserie1_TX1_n003417_SW0 : X_LUT4 generic map( INIT => X"FFFE" ) port map ( ADR0 => Inst_txserie1_TX1_TSR(3), ADR1 => Inst_txserie1_TX1_TSR(2), ADR2 => Inst_txserie1_TX1_TSR(1), ADR3 => Inst_txserie1_TX1_TSR(0), O => N15433 ); Inst_rxserie1_CLOCK1_compteur_0_rt_97 : X_LUT2 generic map( INIT => X"A" ) port map ( ADR0 => Inst_rxserie1_CLOCK1_compteur(0), O => Inst_rxserie1_CLOCK1_compteur_0_rt, ADR1 => GND ); Inst_txserie1_TX1_n003310 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => CHOICE95, ADR1 => CHOICE98, O => Inst_txserie1_TX1_n0033 ); Inst_txserie1_CLOCK1_n000539_SW0 : X_LUT4 generic map( INIT => X"FFFE" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(6), ADR1 => Inst_txserie1_CLOCK1_compteur(7), ADR2 => Inst_txserie1_CLOCK1_compteur(8), ADR3 => Inst_txserie1_CLOCK1_compteur(9), O => N15429 ); Inst_txserie1_TX1_n00334 : X_LUT4 generic map( INIT => X"FFFE" ) port map ( ADR0 => Inst_txserie1_TX1_TSR(7), ADR1 => Inst_txserie1_TX1_TSR(6), ADR2 => Inst_txserie1_TX1_TSR(5), ADR3 => Inst_txserie1_TX1_TSR(4), O => CHOICE95 ); Inst_decodisa_reg_select24 : X_LUT3 generic map( INIT => X"04" ) port map ( ADR0 => bus_adr_15_IBUF, ADR1 => bus_adr_8_IBUF, ADR2 => AEN_IBUF, O => CHOICE68 ); Inst_txserie1_CLOCK1_n000529 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => Inst_txserie1_CLOCK1_compteur(0), ADR1 => Inst_txserie1_CLOCK1_compteur(1), ADR2 => Inst_txserie1_CLOCK1_compteur(2), ADR3 => Inst_txserie1_CLOCK1_compteur(3), O => CHOICE116 ); Inst_txserie1_TX1_n0019_98 : X_LUT3 generic map( INIT => X"8D" ) port map ( ADR0 => Inst_txserie1_TX1_n0034, ADR1 => N14920, ADR2 => Inst_txserie1_TX1_TXDATARDY, O => Inst_txserie1_TX1_n0019 ); Inst_txserie1_state_txload_0_SW112 : X_LUT2 generic map( INIT => X"E" ) port map ( ADR0 => rst_BUFGP, ADR1 => CHOICE36, O => Inst_txserie1_state_txload_0_Q ); Inst_txserie1_FIFO1_state_read_FFd4_In_99 : X_LUT4 generic map( INIT => X"AAA8" ) port map ( ADR0 => N15477, ADR1 => Inst_txserie1_flagreg(3), ADR2 => Inst_txserie1_TX1_n0034, ADR3 => Inst_txserie1_TX1_TXDATARDY, O => Inst_txserie1_FIFO1_state_read_FFd4_In ); Inst_txserie1_FIFO1_state_read_FFd4_In_SW1 : X_LUT3 generic map( INIT => X"FE" ) port map ( ADR0 => Inst_txserie1_FIFO1_dready, ADR1 => Inst_txserie1_FIFO1_state_read_FFd4, ADR2 => Inst_txserie1_FIFO1_state_read_FFd1, O => N15477 ); Inst_decodisa_reg_select32_SW0 : X_LUT4 generic map( INIT => X"FEFF" ) port map ( ADR0 => bus_adr_14_IBUF, ADR1 => bus_adr_13_IBUF, ADR2 => bus_adr_12_IBUF, ADR3 => CHOICE68, O => N15437 ); Inst_rxserie1_FIFO1_state_read_FFd1_In_100 : X_LUT4 generic map( INIT => X"0C08" ) port map ( ADR0 => Inst_rxserie1_FIFO1_state_read_FFd2, ADR1 => cs(1), ADR2 => N14869, ADR3 => Inst_rxserie1_FIFO1_state_read_FFd1, O => Inst_rxserie1_FIFO1_state_read_FFd1_In ); Inst_txserie1_RFLAG_n00071 : X_LUT4 generic map( INIT => X"FB00" ) port map ( ADR0 => IOR_IBUF, ADR1 => IOW_IBUF, ADR2 => AEN_IBUF, ADR3 => cs(6), O => Inst_txserie1_RFLAG_n0007 ); Inst_rxserie1_RC1_RXCNT_1_rt_101 : X_LUT2 generic map( INIT => X"A" ) port map ( ADR0 => Inst_rxserie1_RC1_RXCNT(1), O => Inst_rxserie1_RC1_RXCNT_1_rt, ADR1 => GND ); Inst_rxserie1_FIFO1_state_read_FFd1_In_SW0 : X_LUT4 generic map( INIT => X"FEFF" ) port map ( ADR0 => rst_BUFGP, ADR1 => IOR_IBUF, ADR2 => AEN_IBUF, ADR3 => IOW_IBUF, O => N14869 ); Inst_decodisa_reg_select32 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_9_IBUF, ADR1 => bus_adr_10_IBUF, ADR2 => bus_adr_11_IBUF, ADR3 => N15437, O => Inst_decodisa_reg_select ); N6828_102 : X_LUT4 generic map( INIT => X"F7F5" ) port map ( ADR0 => rw, ADR1 => cs(3), ADR2 => rst_BUFGP, ADR3 => N14659, O => N6828 ); Inst_txserie1_state_txload_0_SW111 : X_LUT4 generic map( INIT => X"4544" ) port map ( ADR0 => Inst_txserie1_txready, ADR1 => Inst_txserie1_state_txload_2_Q, ADR2 => Inst_txserie1_FIFO1_dready, ADR3 => Inst_txserie1_state_txload_0_Q, O => CHOICE36 ); N6828_SW0 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => cs(5), ADR1 => cs(6), ADR2 => cs(1), ADR3 => cs(2), O => N14659 ); Inst_txserie1_TX1_TXDONE2 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => CHOICE144, ADR1 => Inst_txserie1_TX1_TSR(5), ADR2 => Inst_txserie1_TX1_TSR(4), ADR3 => N15433, O => Inst_txserie1_TX1_TXDONE ); bus_data_6_IOBUF_PULLUP : X_PU port map ( O => bus_data_6_IOBUF ); bus_data_3_IOBUF_PULLUP : X_PU port map ( O => bus_data_3_IOBUF ); bus_data_2_IOBUF_PULLUP : X_PU port map ( O => bus_data_2_IOBUF ); bus_data_4_IOBUF_PULLUP : X_PU port map ( O => bus_data_4_IOBUF ); bus_data_5_IOBUF_PULLUP : X_PU port map ( O => bus_data_5_IOBUF ); bus_data_0_IOBUF_PULLUP : X_PU port map ( O => bus_data_0_IOBUF ); bus_data_7_IOBUF_PULLUP : X_PU port map ( O => bus_data_7_IOBUF ); bus_data_1_IOBUF_PULLUP : X_PU port map ( O => bus_data_1_IOBUF ); bus_data_6_IOBUF_OBUFT : X_TRI port map ( CTL => bus_data_6_IOBUF_OBUFT_GTS_AND, I => bus_data_6_IOBUF, O => bus_data(6) ); bus_data_6_IOBUF_IBUF : X_BUF port map ( I => bus_data(6), O => N15397 ); Inst_rxserie1_FIFO1_fifo0_BU232 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N47, O => Inst_rxserie1_inter_fifo(7), SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU230 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N48, O => Inst_rxserie1_inter_fifo(6), SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU228 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N49, O => Inst_rxserie1_inter_fifo(5), SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU226 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N50, O => Inst_rxserie1_inter_fifo(4), SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU224 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N51, O => Inst_rxserie1_inter_fifo(3), SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU222 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N52, O => Inst_rxserie1_inter_fifo(2), SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU220 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N53, O => Inst_rxserie1_inter_fifo(1), SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU218 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N54, O => Inst_rxserie1_inter_fifo(0), SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU214 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N38, D => Inst_rxserie1_RC1_RHR(7), Q => Inst_rxserie1_FIFO1_fifo0_N47, CLK => clk_speed_BUFGP, A0 => Inst_rxserie1_FIFO1_fifo0_N7, A1 => Inst_rxserie1_FIFO1_fifo0_N6, A2 => Inst_rxserie1_FIFO1_fifo0_N5, A3 => Inst_rxserie1_FIFO1_fifo0_N4 ); Inst_rxserie1_FIFO1_fifo0_BU213 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N38, D => Inst_rxserie1_RC1_RHR(6), Q => Inst_rxserie1_FIFO1_fifo0_N48, CLK => clk_speed_BUFGP, A0 => Inst_rxserie1_FIFO1_fifo0_N7, A1 => Inst_rxserie1_FIFO1_fifo0_N6, A2 => Inst_rxserie1_FIFO1_fifo0_N5, A3 => Inst_rxserie1_FIFO1_fifo0_N4 ); Inst_rxserie1_FIFO1_fifo0_BU212 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N38, D => Inst_rxserie1_RC1_RHR(5), Q => Inst_rxserie1_FIFO1_fifo0_N49, CLK => clk_speed_BUFGP, A0 => Inst_rxserie1_FIFO1_fifo0_N7, A1 => Inst_rxserie1_FIFO1_fifo0_N6, A2 => Inst_rxserie1_FIFO1_fifo0_N5, A3 => Inst_rxserie1_FIFO1_fifo0_N4 ); Inst_rxserie1_FIFO1_fifo0_BU211 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N38, D => Inst_rxserie1_RC1_RHR(4), Q => Inst_rxserie1_FIFO1_fifo0_N50, CLK => clk_speed_BUFGP, A0 => Inst_rxserie1_FIFO1_fifo0_N7, A1 => Inst_rxserie1_FIFO1_fifo0_N6, A2 => Inst_rxserie1_FIFO1_fifo0_N5, A3 => Inst_rxserie1_FIFO1_fifo0_N4 ); Inst_rxserie1_FIFO1_fifo0_BU210 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N38, D => Inst_rxserie1_RC1_RHR(3), Q => Inst_rxserie1_FIFO1_fifo0_N51, CLK => clk_speed_BUFGP, A0 => Inst_rxserie1_FIFO1_fifo0_N7, A1 => Inst_rxserie1_FIFO1_fifo0_N6, A2 => Inst_rxserie1_FIFO1_fifo0_N5, A3 => Inst_rxserie1_FIFO1_fifo0_N4 ); Inst_rxserie1_FIFO1_fifo0_BU209 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N38, D => Inst_rxserie1_RC1_RHR(2), Q => Inst_rxserie1_FIFO1_fifo0_N52, CLK => clk_speed_BUFGP, A0 => Inst_rxserie1_FIFO1_fifo0_N7, A1 => Inst_rxserie1_FIFO1_fifo0_N6, A2 => Inst_rxserie1_FIFO1_fifo0_N5, A3 => Inst_rxserie1_FIFO1_fifo0_N4 ); Inst_rxserie1_FIFO1_fifo0_BU208 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N38, D => Inst_rxserie1_RC1_RHR(1), Q => Inst_rxserie1_FIFO1_fifo0_N53, CLK => clk_speed_BUFGP, A0 => Inst_rxserie1_FIFO1_fifo0_N7, A1 => Inst_rxserie1_FIFO1_fifo0_N6, A2 => Inst_rxserie1_FIFO1_fifo0_N5, A3 => Inst_rxserie1_FIFO1_fifo0_N4 ); Inst_rxserie1_FIFO1_fifo0_BU207 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N38, D => Inst_rxserie1_RC1_RHR(0), Q => Inst_rxserie1_FIFO1_fifo0_N54, CLK => clk_speed_BUFGP, A0 => Inst_rxserie1_FIFO1_fifo0_N7, A1 => Inst_rxserie1_FIFO1_fifo0_N6, A2 => Inst_rxserie1_FIFO1_fifo0_N5, A3 => Inst_rxserie1_FIFO1_fifo0_N4 ); Inst_rxserie1_FIFO1_fifo0_BU204 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N1271, O => Inst_rxserie1_flagreg(3), SSET => rst_BUFGP, SET => GSR, RST => GND, SRST => GND ); Inst_rxserie1_FIFO1_fifo0_BU203 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N1143, ADR1 => Inst_rxserie1_FIFO1_fifo0_N1142, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N1271 ); Inst_rxserie1_FIFO1_fifo0_BU196 : X_LUT4 generic map( INIT => X"2222" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N73, ADR1 => Inst_rxserie1_FIFO1_wr_en, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N1143 ); Inst_rxserie1_FIFO1_fifo0_BU190 : X_LUT4 generic map( INIT => X"4040" ) port map ( ADR0 => Inst_rxserie1_FIFO1_wr_en, ADR1 => Inst_rxserie1_FIFO1_rd_en, ADR2 => Inst_rxserie1_FIFO1_fifo0_N74, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N1142 ); Inst_rxserie1_FIFO1_fifo0_BU183 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N1110, IA => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N74, SEL => Inst_rxserie1_FIFO1_fifo0_N1113 ); Inst_rxserie1_FIFO1_fifo0_BU182 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, ADR1 => Inst_rxserie1_flagreg(2), ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N1113 ); Inst_rxserie1_FIFO1_fifo0_BU180 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N1104, IA => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N1110, SEL => Inst_rxserie1_FIFO1_fifo0_N1107 ); Inst_rxserie1_FIFO1_fifo0_BU179 : X_LUT4 generic map( INIT => X"9009" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N17, O => Inst_rxserie1_FIFO1_fifo0_N1107 ); Inst_rxserie1_FIFO1_fifo0_BU177 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N1, IA => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N1104, SEL => Inst_rxserie1_FIFO1_fifo0_N1101 ); Inst_rxserie1_FIFO1_fifo0_BU176 : X_LUT4 generic map( INIT => X"9009" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N1, ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N19, O => Inst_rxserie1_FIFO1_fifo0_N1101 ); Inst_rxserie1_FIFO1_fifo0_BU172 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N1037, IA => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N73, SEL => Inst_rxserie1_FIFO1_fifo0_N1040 ); Inst_rxserie1_FIFO1_fifo0_BU171 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, ADR1 => Inst_rxserie1_flagreg(2), ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N1040 ); Inst_rxserie1_FIFO1_fifo0_BU169 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N1031, IA => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N1037, SEL => Inst_rxserie1_FIFO1_fifo0_N1034 ); Inst_rxserie1_FIFO1_fifo0_BU168 : X_LUT4 generic map( INIT => X"9009" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N17, O => Inst_rxserie1_FIFO1_fifo0_N1034 ); Inst_rxserie1_FIFO1_fifo0_BU166 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N1, IA => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N1031, SEL => Inst_rxserie1_FIFO1_fifo0_N1028 ); Inst_rxserie1_FIFO1_fifo0_BU165 : X_LUT4 generic map( INIT => X"9009" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N19, O => Inst_rxserie1_FIFO1_fifo0_N1028 ); Inst_rxserie1_FIFO1_fifo0_BU161 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), ADR1 => Inst_rxserie1_flagreg(2), ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => NLW_Inst_rxserie1_FIFO1_fifo0_BU161_O_UNCONNECTED ); Inst_rxserie1_FIFO1_fifo0_BU155 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), ADR1 => Inst_rxserie1_FIFO1_fifo0_N17, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_flagreg(1) ); Inst_rxserie1_FIFO1_fifo0_BU149 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_flagreg(0) ); Inst_rxserie1_FIFO1_fifo0_BU143 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), ADR1 => Inst_rxserie1_FIFO1_fifo0_N19, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => NLW_Inst_rxserie1_FIFO1_fifo0_BU143_O_UNCONNECTED ); Inst_rxserie1_FIFO1_fifo0_BU137 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => NLW_Inst_rxserie1_FIFO1_fifo0_BU137_O_UNCONNECTED ); Inst_rxserie1_FIFO1_fifo0_BU131 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N716, O => Inst_rxserie1_flagreg(2), SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU129 : X_XOR2 port map ( I0 => Inst_rxserie1_FIFO1_fifo0_N735, I1 => Inst_rxserie1_FIFO1_fifo0_N738, O => Inst_rxserie1_FIFO1_fifo0_N716 ); Inst_rxserie1_FIFO1_fifo0_BU128 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N738 ); Inst_rxserie1_FIFO1_fifo0_BU126 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N715, O => Inst_rxserie1_FIFO1_fifo0_N17, SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU124 : X_XOR2 port map ( I0 => Inst_rxserie1_FIFO1_fifo0_N730, I1 => Inst_rxserie1_FIFO1_fifo0_N733, O => Inst_rxserie1_FIFO1_fifo0_N715 ); Inst_rxserie1_FIFO1_fifo0_BU123 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N730, IA => Inst_rxserie1_FIFO1_fifo0_N17, O => Inst_rxserie1_FIFO1_fifo0_N735, SEL => Inst_rxserie1_FIFO1_fifo0_N733 ); Inst_rxserie1_FIFO1_fifo0_BU122 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N17, ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N733 ); Inst_rxserie1_FIFO1_fifo0_BU120 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N714, O => Inst_rxserie1_FIFO1_fifo0_N18, SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU118 : X_XOR2 port map ( I0 => Inst_rxserie1_FIFO1_fifo0_N725, I1 => Inst_rxserie1_FIFO1_fifo0_N728, O => Inst_rxserie1_FIFO1_fifo0_N714 ); Inst_rxserie1_FIFO1_fifo0_BU117 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N725, IA => Inst_rxserie1_FIFO1_fifo0_N18, O => Inst_rxserie1_FIFO1_fifo0_N730, SEL => Inst_rxserie1_FIFO1_fifo0_N728 ); Inst_rxserie1_FIFO1_fifo0_BU116 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N18, ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N728 ); Inst_rxserie1_FIFO1_fifo0_BU114 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N713, O => Inst_rxserie1_FIFO1_fifo0_N19, SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU112 : X_XOR2 port map ( I0 => Inst_rxserie1_FIFO1_fifo0_N720, I1 => Inst_rxserie1_FIFO1_fifo0_N723, O => Inst_rxserie1_FIFO1_fifo0_N713 ); Inst_rxserie1_FIFO1_fifo0_BU111 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N720, IA => Inst_rxserie1_FIFO1_fifo0_N19, O => Inst_rxserie1_FIFO1_fifo0_N725, SEL => Inst_rxserie1_FIFO1_fifo0_N723 ); Inst_rxserie1_FIFO1_fifo0_BU110 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N19, ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N723 ); Inst_rxserie1_FIFO1_fifo0_BU108 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N712, O => Inst_rxserie1_FIFO1_fifo0_N20, SRST => rst_BUFGP, SET => GND, RST => GSR, SSET => GND ); Inst_rxserie1_FIFO1_fifo0_BU106 : X_XOR2 port map ( I0 => Inst_rxserie1_FIFO1_fifo0_N718, I1 => Inst_rxserie1_FIFO1_fifo0_N717, O => Inst_rxserie1_FIFO1_fifo0_N712 ); Inst_rxserie1_FIFO1_fifo0_BU105 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N718, IA => Inst_rxserie1_FIFO1_fifo0_N20, O => Inst_rxserie1_FIFO1_fifo0_N720, SEL => Inst_rxserie1_FIFO1_fifo0_N717 ); Inst_rxserie1_FIFO1_fifo0_BU104 : X_LUT4 generic map( INIT => X"6666" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N20, ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N717 ); Inst_rxserie1_FIFO1_fifo0_BU102 : X_LUT4 generic map( INIT => X"5555" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N3, ADR1 => Inst_rxserie1_FIFO1_fifo0_N0, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N718 ); Inst_rxserie1_FIFO1_fifo0_BU97 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N592, O => Inst_rxserie1_FIFO1_fifo0_N4, SSET => rst_BUFGP, SET => GSR, RST => GND, SRST => GND ); Inst_rxserie1_FIFO1_fifo0_BU95 : X_XOR2 port map ( I0 => Inst_rxserie1_FIFO1_fifo0_N606, I1 => Inst_rxserie1_FIFO1_fifo0_N609, O => Inst_rxserie1_FIFO1_fifo0_N592 ); Inst_rxserie1_FIFO1_fifo0_BU94 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N4, ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N609 ); Inst_rxserie1_FIFO1_fifo0_BU92 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N591, O => Inst_rxserie1_FIFO1_fifo0_N5, SSET => rst_BUFGP, SET => GSR, RST => GND, SRST => GND ); Inst_rxserie1_FIFO1_fifo0_BU90 : X_XOR2 port map ( I0 => Inst_rxserie1_FIFO1_fifo0_N601, I1 => Inst_rxserie1_FIFO1_fifo0_N604, O => Inst_rxserie1_FIFO1_fifo0_N591 ); Inst_rxserie1_FIFO1_fifo0_BU89 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N601, IA => Inst_rxserie1_FIFO1_fifo0_N5, O => Inst_rxserie1_FIFO1_fifo0_N606, SEL => Inst_rxserie1_FIFO1_fifo0_N604 ); Inst_rxserie1_FIFO1_fifo0_BU88 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N5, ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N604 ); Inst_rxserie1_FIFO1_fifo0_BU86 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N590, O => Inst_rxserie1_FIFO1_fifo0_N6, SSET => rst_BUFGP, SET => GSR, RST => GND, SRST => GND ); Inst_rxserie1_FIFO1_fifo0_BU84 : X_XOR2 port map ( I0 => Inst_rxserie1_FIFO1_fifo0_N596, I1 => Inst_rxserie1_FIFO1_fifo0_N599, O => Inst_rxserie1_FIFO1_fifo0_N590 ); Inst_rxserie1_FIFO1_fifo0_BU83 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N596, IA => Inst_rxserie1_FIFO1_fifo0_N6, O => Inst_rxserie1_FIFO1_fifo0_N601, SEL => Inst_rxserie1_FIFO1_fifo0_N599 ); Inst_rxserie1_FIFO1_fifo0_BU82 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N6, ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N599 ); Inst_rxserie1_FIFO1_fifo0_BU80 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N589, O => Inst_rxserie1_FIFO1_fifo0_N7, SSET => rst_BUFGP, SET => GSR, RST => GND, SRST => GND ); Inst_rxserie1_FIFO1_fifo0_BU78 : X_XOR2 port map ( I0 => Inst_rxserie1_FIFO1_fifo0_N594, I1 => Inst_rxserie1_FIFO1_fifo0_N593, O => Inst_rxserie1_FIFO1_fifo0_N589 ); Inst_rxserie1_FIFO1_fifo0_BU77 : X_MUX2 port map ( IB => Inst_rxserie1_FIFO1_fifo0_N594, IA => Inst_rxserie1_FIFO1_fifo0_N7, O => Inst_rxserie1_FIFO1_fifo0_N596, SEL => Inst_rxserie1_FIFO1_fifo0_N593 ); Inst_rxserie1_FIFO1_fifo0_BU76 : X_LUT4 generic map( INIT => X"6666" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N7, ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N593 ); Inst_rxserie1_FIFO1_fifo0_BU74 : X_LUT4 generic map( INIT => X"5555" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N3, ADR1 => Inst_rxserie1_FIFO1_fifo0_N0, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N594 ); Inst_rxserie1_FIFO1_fifo0_BU69 : X_LUT4 generic map( INIT => X"6666" ) port map ( ADR0 => Inst_rxserie1_FIFO1_fifo0_N2, ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N33 ); Inst_rxserie1_FIFO1_fifo0_BU63 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N505, O => Inst_rxserie1_FIFO1_fifo0_wr_ack, SSET => rst_BUFGP, SET => GSR, RST => GND, SRST => GND ); Inst_rxserie1_FIFO1_fifo0_BU62 : X_LUT4 generic map( INIT => X"bbbb" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), ADR1 => Inst_rxserie1_FIFO1_wr_en, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N505 ); Inst_rxserie1_FIFO1_fifo0_BU55 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N456, O => Inst_rxserie1_FIFO1_fifo0_wr_err, SSET => rst_BUFGP, SET => GSR, RST => GND, SRST => GND ); Inst_rxserie1_FIFO1_fifo0_BU54 : X_LUT4 generic map( INIT => X"7777" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), ADR1 => Inst_rxserie1_FIFO1_wr_en, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N456 ); Inst_rxserie1_FIFO1_fifo0_BU47 : X_LUT4 generic map( INIT => X"2222" ) port map ( ADR0 => Inst_rxserie1_FIFO1_wr_en, ADR1 => Inst_rxserie1_flagreg(2), ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N38 ); Inst_rxserie1_FIFO1_fifo0_BU41 : X_LUT4 generic map( INIT => X"2222" ) port map ( ADR0 => Inst_rxserie1_FIFO1_wr_en, ADR1 => Inst_rxserie1_flagreg(2), ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N3 ); Inst_rxserie1_FIFO1_fifo0_BU35 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N333, O => Inst_rxserie1_FIFO1_fifo0_rd_ack, SSET => rst_BUFGP, SET => GSR, RST => GND, SRST => GND ); Inst_rxserie1_FIFO1_fifo0_BU34 : X_LUT4 generic map( INIT => X"bbbb" ) port map ( ADR0 => Inst_rxserie1_flagreg(3), ADR1 => Inst_rxserie1_FIFO1_rd_en, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N333 ); Inst_rxserie1_FIFO1_fifo0_BU27 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_rxserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, I => Inst_rxserie1_FIFO1_fifo0_N284, O => Inst_rxserie1_FIFO1_fifo0_rd_err, SSET => rst_BUFGP, SET => GSR, RST => GND, SRST => GND ); Inst_rxserie1_FIFO1_fifo0_BU26 : X_LUT4 generic map( INIT => X"7777" ) port map ( ADR0 => Inst_rxserie1_flagreg(3), ADR1 => Inst_rxserie1_FIFO1_rd_en, ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N284 ); Inst_rxserie1_FIFO1_fifo0_BU19 : X_LUT4 generic map( INIT => X"2222" ) port map ( ADR0 => Inst_rxserie1_FIFO1_rd_en, ADR1 => Inst_rxserie1_flagreg(3), ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N37 ); Inst_rxserie1_FIFO1_fifo0_BU13 : X_LUT4 generic map( INIT => X"2222" ) port map ( ADR0 => Inst_rxserie1_FIFO1_rd_en, ADR1 => Inst_rxserie1_flagreg(3), ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => Inst_rxserie1_FIFO1_fifo0_N2 ); Inst_rxserie1_FIFO1_fifo0_BU7 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_rxserie1_flagreg(2), ADR1 => Inst_rxserie1_flagreg(2), ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, O => NLW_Inst_rxserie1_FIFO1_fifo0_BU7_O_UNCONNECTED ); Inst_rxserie1_FIFO1_fifo0_GND : X_ZERO port map ( O => Inst_rxserie1_FIFO1_fifo0_N0 ); Inst_rxserie1_FIFO1_fifo0_VCC : X_ONE port map ( O => Inst_rxserie1_FIFO1_fifo0_N1 ); bus_data_5_IOBUF_OBUFT : X_TRI port map ( CTL => bus_data_5_IOBUF_OBUFT_GTS_AND, I => bus_data_5_IOBUF, O => bus_data(5) ); bus_data_5_IOBUF_IBUF : X_BUF port map ( I => bus_data(5), O => N15395 ); bus_data_2_IOBUF_OBUFT : X_TRI port map ( CTL => bus_data_2_IOBUF_OBUFT_GTS_AND, I => bus_data_2_IOBUF, O => bus_data(2) ); bus_data_2_IOBUF_IBUF : X_BUF port map ( I => bus_data(2), O => N15389 ); Inst_txserie1_FIFO1_fifo0_BU232 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N47, O => Inst_txserie1_inter_data(7), SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU230 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N48, O => Inst_txserie1_inter_data(6), SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU228 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N49, O => Inst_txserie1_inter_data(5), SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU226 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N50, O => Inst_txserie1_inter_data(4), SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU224 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N51, O => Inst_txserie1_inter_data(3), SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU222 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N52, O => Inst_txserie1_inter_data(2), SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU220 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N53, O => Inst_txserie1_inter_data(1), SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU218 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N54, O => Inst_txserie1_inter_data(0), SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU214 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N38, D => N15399, Q => Inst_txserie1_FIFO1_fifo0_N47, CLK => clk_speed_BUFGP, A0 => Inst_txserie1_FIFO1_fifo0_N7, A1 => Inst_txserie1_FIFO1_fifo0_N6, A2 => Inst_txserie1_FIFO1_fifo0_N5, A3 => Inst_txserie1_FIFO1_fifo0_N4 ); Inst_txserie1_FIFO1_fifo0_BU213 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N38, D => N15397, Q => Inst_txserie1_FIFO1_fifo0_N48, CLK => clk_speed_BUFGP, A0 => Inst_txserie1_FIFO1_fifo0_N7, A1 => Inst_txserie1_FIFO1_fifo0_N6, A2 => Inst_txserie1_FIFO1_fifo0_N5, A3 => Inst_txserie1_FIFO1_fifo0_N4 ); Inst_txserie1_FIFO1_fifo0_BU212 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N38, D => N15395, Q => Inst_txserie1_FIFO1_fifo0_N49, CLK => clk_speed_BUFGP, A0 => Inst_txserie1_FIFO1_fifo0_N7, A1 => Inst_txserie1_FIFO1_fifo0_N6, A2 => Inst_txserie1_FIFO1_fifo0_N5, A3 => Inst_txserie1_FIFO1_fifo0_N4 ); Inst_txserie1_FIFO1_fifo0_BU211 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N38, D => N15393, Q => Inst_txserie1_FIFO1_fifo0_N50, CLK => clk_speed_BUFGP, A0 => Inst_txserie1_FIFO1_fifo0_N7, A1 => Inst_txserie1_FIFO1_fifo0_N6, A2 => Inst_txserie1_FIFO1_fifo0_N5, A3 => Inst_txserie1_FIFO1_fifo0_N4 ); Inst_txserie1_FIFO1_fifo0_BU210 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N38, D => N15391, Q => Inst_txserie1_FIFO1_fifo0_N51, CLK => clk_speed_BUFGP, A0 => Inst_txserie1_FIFO1_fifo0_N7, A1 => Inst_txserie1_FIFO1_fifo0_N6, A2 => Inst_txserie1_FIFO1_fifo0_N5, A3 => Inst_txserie1_FIFO1_fifo0_N4 ); Inst_txserie1_FIFO1_fifo0_BU209 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N38, D => N15389, Q => Inst_txserie1_FIFO1_fifo0_N52, CLK => clk_speed_BUFGP, A0 => Inst_txserie1_FIFO1_fifo0_N7, A1 => Inst_txserie1_FIFO1_fifo0_N6, A2 => Inst_txserie1_FIFO1_fifo0_N5, A3 => Inst_txserie1_FIFO1_fifo0_N4 ); Inst_txserie1_FIFO1_fifo0_BU208 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N38, D => N15387, Q => Inst_txserie1_FIFO1_fifo0_N53, CLK => clk_speed_BUFGP, A0 => Inst_txserie1_FIFO1_fifo0_N7, A1 => Inst_txserie1_FIFO1_fifo0_N6, A2 => Inst_txserie1_FIFO1_fifo0_N5, A3 => Inst_txserie1_FIFO1_fifo0_N4 ); Inst_txserie1_FIFO1_fifo0_BU207 : X_SRL16E generic map( INIT => X"0000" ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N38, D => N15385, Q => Inst_txserie1_FIFO1_fifo0_N54, CLK => clk_speed_BUFGP, A0 => Inst_txserie1_FIFO1_fifo0_N7, A1 => Inst_txserie1_FIFO1_fifo0_N6, A2 => Inst_txserie1_FIFO1_fifo0_N5, A3 => Inst_txserie1_FIFO1_fifo0_N4 ); Inst_txserie1_FIFO1_fifo0_BU204 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N1271, O => Inst_txserie1_flagreg(3), SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); Inst_txserie1_FIFO1_fifo0_BU203 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N1143, ADR1 => Inst_txserie1_FIFO1_fifo0_N1142, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N1271 ); Inst_txserie1_FIFO1_fifo0_BU196 : X_LUT4 generic map( INIT => X"2222" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N73, ADR1 => Inst_txserie1_FIFO1_wr_en, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N1143 ); Inst_txserie1_FIFO1_fifo0_BU190 : X_LUT4 generic map( INIT => X"4040" ) port map ( ADR0 => Inst_txserie1_FIFO1_wr_en, ADR1 => Inst_txserie1_FIFO1_rd_en, ADR2 => Inst_txserie1_FIFO1_fifo0_N74, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N1142 ); Inst_txserie1_FIFO1_fifo0_BU183 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N1110, IA => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N74, SEL => Inst_txserie1_FIFO1_fifo0_N1113 ); Inst_txserie1_FIFO1_fifo0_BU182 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N0, ADR1 => Inst_txserie1_flagreg(2), ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N1113 ); Inst_txserie1_FIFO1_fifo0_BU180 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N1104, IA => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N1110, SEL => Inst_txserie1_FIFO1_fifo0_N1107 ); Inst_txserie1_FIFO1_fifo0_BU179 : X_LUT4 generic map( INIT => X"9009" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N0, ADR1 => Inst_txserie1_FIFO1_fifo0_N18, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N17, O => Inst_txserie1_FIFO1_fifo0_N1107 ); Inst_txserie1_FIFO1_fifo0_BU177 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N1, IA => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N1104, SEL => Inst_txserie1_FIFO1_fifo0_N1101 ); Inst_txserie1_FIFO1_fifo0_BU176 : X_LUT4 generic map( INIT => X"9009" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N1, ADR1 => Inst_txserie1_FIFO1_fifo0_N20, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N19, O => Inst_txserie1_FIFO1_fifo0_N1101 ); Inst_txserie1_FIFO1_fifo0_BU172 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N1037, IA => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N73, SEL => Inst_txserie1_FIFO1_fifo0_N1040 ); Inst_txserie1_FIFO1_fifo0_BU171 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N0, ADR1 => Inst_txserie1_flagreg(2), ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N1040 ); Inst_txserie1_FIFO1_fifo0_BU169 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N1031, IA => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N1037, SEL => Inst_txserie1_FIFO1_fifo0_N1034 ); Inst_txserie1_FIFO1_fifo0_BU168 : X_LUT4 generic map( INIT => X"9009" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N0, ADR1 => Inst_txserie1_FIFO1_fifo0_N18, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N17, O => Inst_txserie1_FIFO1_fifo0_N1034 ); Inst_txserie1_FIFO1_fifo0_BU166 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N1, IA => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N1031, SEL => Inst_txserie1_FIFO1_fifo0_N1028 ); Inst_txserie1_FIFO1_fifo0_BU165 : X_LUT4 generic map( INIT => X"9009" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N0, ADR1 => Inst_txserie1_FIFO1_fifo0_N20, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N19, O => Inst_txserie1_FIFO1_fifo0_N1028 ); Inst_txserie1_FIFO1_fifo0_BU161 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_txserie1_flagreg(2), ADR1 => Inst_txserie1_flagreg(2), ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => NLW_Inst_txserie1_FIFO1_fifo0_BU161_O_UNCONNECTED ); Inst_txserie1_FIFO1_fifo0_BU155 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_txserie1_flagreg(2), ADR1 => Inst_txserie1_FIFO1_fifo0_N17, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_fifoLevel(1) ); Inst_txserie1_FIFO1_fifo0_BU149 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_txserie1_flagreg(2), ADR1 => Inst_txserie1_FIFO1_fifo0_N18, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_fifoLevel(0) ); Inst_txserie1_FIFO1_fifo0_BU143 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_txserie1_flagreg(2), ADR1 => Inst_txserie1_FIFO1_fifo0_N19, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => NLW_Inst_txserie1_FIFO1_fifo0_BU143_O_UNCONNECTED ); Inst_txserie1_FIFO1_fifo0_BU137 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_txserie1_flagreg(2), ADR1 => Inst_txserie1_FIFO1_fifo0_N20, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => NLW_Inst_txserie1_FIFO1_fifo0_BU137_O_UNCONNECTED ); Inst_txserie1_FIFO1_fifo0_BU131 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N716, O => Inst_txserie1_flagreg(2), SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU129 : X_XOR2 port map ( I0 => Inst_txserie1_FIFO1_fifo0_N735, I1 => Inst_txserie1_FIFO1_fifo0_N738, O => Inst_txserie1_FIFO1_fifo0_N716 ); Inst_txserie1_FIFO1_fifo0_BU128 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_txserie1_flagreg(2), ADR1 => Inst_txserie1_FIFO1_fifo0_N3, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N738 ); Inst_txserie1_FIFO1_fifo0_BU126 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N715, O => Inst_txserie1_FIFO1_fifo0_N17, SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU124 : X_XOR2 port map ( I0 => Inst_txserie1_FIFO1_fifo0_N730, I1 => Inst_txserie1_FIFO1_fifo0_N733, O => Inst_txserie1_FIFO1_fifo0_N715 ); Inst_txserie1_FIFO1_fifo0_BU123 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N730, IA => Inst_txserie1_FIFO1_fifo0_N17, O => Inst_txserie1_FIFO1_fifo0_N735, SEL => Inst_txserie1_FIFO1_fifo0_N733 ); Inst_txserie1_FIFO1_fifo0_BU122 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N17, ADR1 => Inst_txserie1_FIFO1_fifo0_N3, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N733 ); Inst_txserie1_FIFO1_fifo0_BU120 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N714, O => Inst_txserie1_FIFO1_fifo0_N18, SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU118 : X_XOR2 port map ( I0 => Inst_txserie1_FIFO1_fifo0_N725, I1 => Inst_txserie1_FIFO1_fifo0_N728, O => Inst_txserie1_FIFO1_fifo0_N714 ); Inst_txserie1_FIFO1_fifo0_BU117 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N725, IA => Inst_txserie1_FIFO1_fifo0_N18, O => Inst_txserie1_FIFO1_fifo0_N730, SEL => Inst_txserie1_FIFO1_fifo0_N728 ); Inst_txserie1_FIFO1_fifo0_BU116 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N18, ADR1 => Inst_txserie1_FIFO1_fifo0_N3, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N728 ); Inst_txserie1_FIFO1_fifo0_BU114 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N713, O => Inst_txserie1_FIFO1_fifo0_N19, SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU112 : X_XOR2 port map ( I0 => Inst_txserie1_FIFO1_fifo0_N720, I1 => Inst_txserie1_FIFO1_fifo0_N723, O => Inst_txserie1_FIFO1_fifo0_N713 ); Inst_txserie1_FIFO1_fifo0_BU111 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N720, IA => Inst_txserie1_FIFO1_fifo0_N19, O => Inst_txserie1_FIFO1_fifo0_N725, SEL => Inst_txserie1_FIFO1_fifo0_N723 ); Inst_txserie1_FIFO1_fifo0_BU110 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N19, ADR1 => Inst_txserie1_FIFO1_fifo0_N3, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N723 ); Inst_txserie1_FIFO1_fifo0_BU108 : X_SFF generic map( INIT => '0' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N712, O => Inst_txserie1_FIFO1_fifo0_N20, SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); Inst_txserie1_FIFO1_fifo0_BU106 : X_XOR2 port map ( I0 => Inst_txserie1_FIFO1_fifo0_N718, I1 => Inst_txserie1_FIFO1_fifo0_N717, O => Inst_txserie1_FIFO1_fifo0_N712 ); Inst_txserie1_FIFO1_fifo0_BU105 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N718, IA => Inst_txserie1_FIFO1_fifo0_N20, O => Inst_txserie1_FIFO1_fifo0_N720, SEL => Inst_txserie1_FIFO1_fifo0_N717 ); Inst_txserie1_FIFO1_fifo0_BU104 : X_LUT4 generic map( INIT => X"6666" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N20, ADR1 => Inst_txserie1_FIFO1_fifo0_N3, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N717 ); Inst_txserie1_FIFO1_fifo0_BU102 : X_LUT4 generic map( INIT => X"5555" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N3, ADR1 => Inst_txserie1_FIFO1_fifo0_N0, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N718 ); Inst_txserie1_FIFO1_fifo0_BU97 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N592, O => Inst_txserie1_FIFO1_fifo0_N4, SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); Inst_txserie1_FIFO1_fifo0_BU95 : X_XOR2 port map ( I0 => Inst_txserie1_FIFO1_fifo0_N606, I1 => Inst_txserie1_FIFO1_fifo0_N609, O => Inst_txserie1_FIFO1_fifo0_N592 ); Inst_txserie1_FIFO1_fifo0_BU94 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N4, ADR1 => Inst_txserie1_FIFO1_fifo0_N3, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N609 ); Inst_txserie1_FIFO1_fifo0_BU92 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N591, O => Inst_txserie1_FIFO1_fifo0_N5, SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); Inst_txserie1_FIFO1_fifo0_BU90 : X_XOR2 port map ( I0 => Inst_txserie1_FIFO1_fifo0_N601, I1 => Inst_txserie1_FIFO1_fifo0_N604, O => Inst_txserie1_FIFO1_fifo0_N591 ); Inst_txserie1_FIFO1_fifo0_BU89 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N601, IA => Inst_txserie1_FIFO1_fifo0_N5, O => Inst_txserie1_FIFO1_fifo0_N606, SEL => Inst_txserie1_FIFO1_fifo0_N604 ); Inst_txserie1_FIFO1_fifo0_BU88 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N5, ADR1 => Inst_txserie1_FIFO1_fifo0_N3, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N604 ); Inst_txserie1_FIFO1_fifo0_BU86 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N590, O => Inst_txserie1_FIFO1_fifo0_N6, SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); Inst_txserie1_FIFO1_fifo0_BU84 : X_XOR2 port map ( I0 => Inst_txserie1_FIFO1_fifo0_N596, I1 => Inst_txserie1_FIFO1_fifo0_N599, O => Inst_txserie1_FIFO1_fifo0_N590 ); Inst_txserie1_FIFO1_fifo0_BU83 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N596, IA => Inst_txserie1_FIFO1_fifo0_N6, O => Inst_txserie1_FIFO1_fifo0_N601, SEL => Inst_txserie1_FIFO1_fifo0_N599 ); Inst_txserie1_FIFO1_fifo0_BU82 : X_LUT4 generic map( INIT => X"9999" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N6, ADR1 => Inst_txserie1_FIFO1_fifo0_N3, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N599 ); Inst_txserie1_FIFO1_fifo0_BU80 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N589, O => Inst_txserie1_FIFO1_fifo0_N7, SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); Inst_txserie1_FIFO1_fifo0_BU78 : X_XOR2 port map ( I0 => Inst_txserie1_FIFO1_fifo0_N594, I1 => Inst_txserie1_FIFO1_fifo0_N593, O => Inst_txserie1_FIFO1_fifo0_N589 ); Inst_txserie1_FIFO1_fifo0_BU77 : X_MUX2 port map ( IB => Inst_txserie1_FIFO1_fifo0_N594, IA => Inst_txserie1_FIFO1_fifo0_N7, O => Inst_txserie1_FIFO1_fifo0_N596, SEL => Inst_txserie1_FIFO1_fifo0_N593 ); Inst_txserie1_FIFO1_fifo0_BU76 : X_LUT4 generic map( INIT => X"6666" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N7, ADR1 => Inst_txserie1_FIFO1_fifo0_N3, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N593 ); Inst_txserie1_FIFO1_fifo0_BU74 : X_LUT4 generic map( INIT => X"5555" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N3, ADR1 => Inst_txserie1_FIFO1_fifo0_N0, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N594 ); Inst_txserie1_FIFO1_fifo0_BU69 : X_LUT4 generic map( INIT => X"6666" ) port map ( ADR0 => Inst_txserie1_FIFO1_fifo0_N2, ADR1 => Inst_txserie1_FIFO1_fifo0_N3, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N33 ); Inst_txserie1_FIFO1_fifo0_BU63 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N505, O => Inst_txserie1_FIFO1_fifo0_wr_ack, SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); Inst_txserie1_FIFO1_fifo0_BU62 : X_LUT4 generic map( INIT => X"bbbb" ) port map ( ADR0 => Inst_txserie1_flagreg(2), ADR1 => Inst_txserie1_FIFO1_wr_en, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N505 ); Inst_txserie1_FIFO1_fifo0_BU55 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N456, O => Inst_txserie1_FIFO1_fifo0_wr_err, SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); Inst_txserie1_FIFO1_fifo0_BU54 : X_LUT4 generic map( INIT => X"7777" ) port map ( ADR0 => Inst_txserie1_flagreg(2), ADR1 => Inst_txserie1_FIFO1_wr_en, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N456 ); Inst_txserie1_FIFO1_fifo0_BU47 : X_LUT4 generic map( INIT => X"2222" ) port map ( ADR0 => Inst_txserie1_FIFO1_wr_en, ADR1 => Inst_txserie1_flagreg(2), ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N38 ); Inst_txserie1_FIFO1_fifo0_BU41 : X_LUT4 generic map( INIT => X"2222" ) port map ( ADR0 => Inst_txserie1_FIFO1_wr_en, ADR1 => Inst_txserie1_flagreg(2), ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N3 ); Inst_txserie1_FIFO1_fifo0_BU35 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N333, O => Inst_txserie1_FIFO1_fifo0_rd_ack, SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); Inst_txserie1_FIFO1_fifo0_BU34 : X_LUT4 generic map( INIT => X"bbbb" ) port map ( ADR0 => Inst_txserie1_flagreg(3), ADR1 => Inst_txserie1_FIFO1_rd_en, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N333 ); Inst_txserie1_FIFO1_fifo0_BU27 : X_SFF generic map( INIT => '1' ) port map ( CE => Inst_txserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, I => Inst_txserie1_FIFO1_fifo0_N284, O => Inst_txserie1_FIFO1_fifo0_rd_err, SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); Inst_txserie1_FIFO1_fifo0_BU26 : X_LUT4 generic map( INIT => X"7777" ) port map ( ADR0 => Inst_txserie1_flagreg(3), ADR1 => Inst_txserie1_FIFO1_rd_en, ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N284 ); Inst_txserie1_FIFO1_fifo0_BU19 : X_LUT4 generic map( INIT => X"2222" ) port map ( ADR0 => Inst_txserie1_FIFO1_rd_en, ADR1 => Inst_txserie1_flagreg(3), ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N37 ); Inst_txserie1_FIFO1_fifo0_BU13 : X_LUT4 generic map( INIT => X"2222" ) port map ( ADR0 => Inst_txserie1_FIFO1_rd_en, ADR1 => Inst_txserie1_flagreg(3), ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => Inst_txserie1_FIFO1_fifo0_N2 ); Inst_txserie1_FIFO1_fifo0_BU7 : X_LUT4 generic map( INIT => X"eeee" ) port map ( ADR0 => Inst_txserie1_flagreg(2), ADR1 => Inst_txserie1_flagreg(2), ADR2 => Inst_txserie1_FIFO1_fifo0_N0, ADR3 => Inst_txserie1_FIFO1_fifo0_N0, O => NLW_Inst_txserie1_FIFO1_fifo0_BU7_O_UNCONNECTED ); Inst_txserie1_FIFO1_fifo0_GND : X_ZERO port map ( O => Inst_txserie1_FIFO1_fifo0_N0 ); Inst_txserie1_FIFO1_fifo0_VCC : X_ONE port map ( O => Inst_txserie1_FIFO1_fifo0_N1 ); bus_data_4_IOBUF_OBUFT : X_TRI port map ( CTL => bus_data_4_IOBUF_OBUFT_GTS_AND, I => bus_data_4_IOBUF, O => bus_data(4) ); bus_data_4_IOBUF_IBUF : X_BUF port map ( I => bus_data(4), O => N15393 ); bus_data_3_IOBUF_OBUFT : X_TRI port map ( CTL => bus_data_3_IOBUF_OBUFT_GTS_AND, I => bus_data_3_IOBUF, O => bus_data(3) ); bus_data_3_IOBUF_IBUF : X_BUF port map ( I => bus_data(3), O => N15391 ); bus_data_0_IOBUF_OBUFT : X_TRI port map ( CTL => bus_data_0_IOBUF_OBUFT_GTS_AND, I => bus_data_0_IOBUF, O => bus_data(0) ); bus_data_0_IOBUF_IBUF : X_BUF port map ( I => bus_data(0), O => N15385 ); bus_data_7_IOBUF_OBUFT : X_TRI port map ( CTL => bus_data_7_IOBUF_OBUFT_GTS_AND, I => bus_data_7_IOBUF, O => bus_data(7) ); bus_data_7_IOBUF_IBUF : X_BUF port map ( I => bus_data(7), O => N15399 ); bus_data_1_IOBUF_OBUFT : X_TRI port map ( CTL => bus_data_1_IOBUF_OBUFT_GTS_AND, I => bus_data_1_IOBUF, O => bus_data(1) ); bus_data_1_IOBUF_IBUF : X_BUF port map ( I => bus_data(1), O => N15387 ); Inst_decodisa_dadrL_BU2826 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N18684, ADR2 => Inst_decodisa_dadrL_N18685, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_255_Q ); Inst_decodisa_dadrL_BU2823 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N18685 ); Inst_decodisa_dadrL_BU2820 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N18684 ); Inst_decodisa_dadrL_BU2815 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N18613, ADR2 => Inst_decodisa_dadrL_N18614, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_254_Q ); Inst_decodisa_dadrL_BU2812 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N18614 ); Inst_decodisa_dadrL_BU2809 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N18613 ); Inst_decodisa_dadrL_BU2804 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N18542, ADR2 => Inst_decodisa_dadrL_N18543, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_253_Q ); Inst_decodisa_dadrL_BU2801 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N18543 ); Inst_decodisa_dadrL_BU2798 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N18542 ); Inst_decodisa_dadrL_BU2793 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N18471, ADR2 => Inst_decodisa_dadrL_N18472, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_252_Q ); Inst_decodisa_dadrL_BU2790 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N18472 ); Inst_decodisa_dadrL_BU2787 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N18471 ); Inst_decodisa_dadrL_BU2782 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N18400, ADR2 => Inst_decodisa_dadrL_N18401, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_251_Q ); Inst_decodisa_dadrL_BU2779 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N18401 ); Inst_decodisa_dadrL_BU2776 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N18400 ); Inst_decodisa_dadrL_BU2771 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N18329, ADR2 => Inst_decodisa_dadrL_N18330, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_250_Q ); Inst_decodisa_dadrL_BU2768 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N18330 ); Inst_decodisa_dadrL_BU2765 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N18329 ); Inst_decodisa_dadrL_BU2760 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N18258, ADR2 => Inst_decodisa_dadrL_N18259, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_249_Q ); Inst_decodisa_dadrL_BU2757 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N18259 ); Inst_decodisa_dadrL_BU2754 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N18258 ); Inst_decodisa_dadrL_BU2749 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N18187, ADR2 => Inst_decodisa_dadrL_N18188, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_248_Q ); Inst_decodisa_dadrL_BU2746 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N18188 ); Inst_decodisa_dadrL_BU2743 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N18187 ); Inst_decodisa_dadrL_BU2738 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N18116, ADR2 => Inst_decodisa_dadrL_N18117, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_247_Q ); Inst_decodisa_dadrL_BU2735 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N18117 ); Inst_decodisa_dadrL_BU2732 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N18116 ); Inst_decodisa_dadrL_BU2727 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N18045, ADR2 => Inst_decodisa_dadrL_N18046, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_246_Q ); Inst_decodisa_dadrL_BU2724 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N18046 ); Inst_decodisa_dadrL_BU2721 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N18045 ); Inst_decodisa_dadrL_BU2716 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17974, ADR2 => Inst_decodisa_dadrL_N17975, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_245_Q ); Inst_decodisa_dadrL_BU2713 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17975 ); Inst_decodisa_dadrL_BU2710 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17974 ); Inst_decodisa_dadrL_BU2705 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17903, ADR2 => Inst_decodisa_dadrL_N17904, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_244_Q ); Inst_decodisa_dadrL_BU2702 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17904 ); Inst_decodisa_dadrL_BU2699 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17903 ); Inst_decodisa_dadrL_BU2694 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17832, ADR2 => Inst_decodisa_dadrL_N17833, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_243_Q ); Inst_decodisa_dadrL_BU2691 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17833 ); Inst_decodisa_dadrL_BU2688 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17832 ); Inst_decodisa_dadrL_BU2683 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17761, ADR2 => Inst_decodisa_dadrL_N17762, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_242_Q ); Inst_decodisa_dadrL_BU2680 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17762 ); Inst_decodisa_dadrL_BU2677 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17761 ); Inst_decodisa_dadrL_BU2672 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17690, ADR2 => Inst_decodisa_dadrL_N17691, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_241_Q ); Inst_decodisa_dadrL_BU2669 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17691 ); Inst_decodisa_dadrL_BU2666 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17690 ); Inst_decodisa_dadrL_BU2661 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17619, ADR2 => Inst_decodisa_dadrL_N17620, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_240_Q ); Inst_decodisa_dadrL_BU2658 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17620 ); Inst_decodisa_dadrL_BU2655 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17619 ); Inst_decodisa_dadrL_BU2650 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17548, ADR2 => Inst_decodisa_dadrL_N17549, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_239_Q ); Inst_decodisa_dadrL_BU2647 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17549 ); Inst_decodisa_dadrL_BU2644 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17548 ); Inst_decodisa_dadrL_BU2639 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17477, ADR2 => Inst_decodisa_dadrL_N17478, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_238_Q ); Inst_decodisa_dadrL_BU2636 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17478 ); Inst_decodisa_dadrL_BU2633 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17477 ); Inst_decodisa_dadrL_BU2628 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17406, ADR2 => Inst_decodisa_dadrL_N17407, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_237_Q ); Inst_decodisa_dadrL_BU2625 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17407 ); Inst_decodisa_dadrL_BU2622 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17406 ); Inst_decodisa_dadrL_BU2617 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17335, ADR2 => Inst_decodisa_dadrL_N17336, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_236_Q ); Inst_decodisa_dadrL_BU2614 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17336 ); Inst_decodisa_dadrL_BU2611 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17335 ); Inst_decodisa_dadrL_BU2606 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17264, ADR2 => Inst_decodisa_dadrL_N17265, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_235_Q ); Inst_decodisa_dadrL_BU2603 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17265 ); Inst_decodisa_dadrL_BU2600 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17264 ); Inst_decodisa_dadrL_BU2595 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17193, ADR2 => Inst_decodisa_dadrL_N17194, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_234_Q ); Inst_decodisa_dadrL_BU2592 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17194 ); Inst_decodisa_dadrL_BU2589 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17193 ); Inst_decodisa_dadrL_BU2584 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17122, ADR2 => Inst_decodisa_dadrL_N17123, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_233_Q ); Inst_decodisa_dadrL_BU2581 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17123 ); Inst_decodisa_dadrL_BU2578 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17122 ); Inst_decodisa_dadrL_BU2573 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N17051, ADR2 => Inst_decodisa_dadrL_N17052, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_232_Q ); Inst_decodisa_dadrL_BU2570 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N17052 ); Inst_decodisa_dadrL_BU2567 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N17051 ); Inst_decodisa_dadrL_BU2562 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16980, ADR2 => Inst_decodisa_dadrL_N16981, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_231_Q ); Inst_decodisa_dadrL_BU2559 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16981 ); Inst_decodisa_dadrL_BU2556 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16980 ); Inst_decodisa_dadrL_BU2551 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16909, ADR2 => Inst_decodisa_dadrL_N16910, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_230_Q ); Inst_decodisa_dadrL_BU2548 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16910 ); Inst_decodisa_dadrL_BU2545 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16909 ); Inst_decodisa_dadrL_BU2540 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16838, ADR2 => Inst_decodisa_dadrL_N16839, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_229_Q ); Inst_decodisa_dadrL_BU2537 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16839 ); Inst_decodisa_dadrL_BU2534 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16838 ); Inst_decodisa_dadrL_BU2529 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16767, ADR2 => Inst_decodisa_dadrL_N16768, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_228_Q ); Inst_decodisa_dadrL_BU2526 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16768 ); Inst_decodisa_dadrL_BU2523 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16767 ); Inst_decodisa_dadrL_BU2518 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16696, ADR2 => Inst_decodisa_dadrL_N16697, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_227_Q ); Inst_decodisa_dadrL_BU2515 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16697 ); Inst_decodisa_dadrL_BU2512 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16696 ); Inst_decodisa_dadrL_BU2507 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16625, ADR2 => Inst_decodisa_dadrL_N16626, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_226_Q ); Inst_decodisa_dadrL_BU2504 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16626 ); Inst_decodisa_dadrL_BU2501 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16625 ); Inst_decodisa_dadrL_BU2496 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16554, ADR2 => Inst_decodisa_dadrL_N16555, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_225_Q ); Inst_decodisa_dadrL_BU2493 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16555 ); Inst_decodisa_dadrL_BU2490 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16554 ); Inst_decodisa_dadrL_BU2485 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16483, ADR2 => Inst_decodisa_dadrL_N16484, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_224_Q ); Inst_decodisa_dadrL_BU2482 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16484 ); Inst_decodisa_dadrL_BU2479 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16483 ); Inst_decodisa_dadrL_BU2474 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16412, ADR2 => Inst_decodisa_dadrL_N16413, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_223_Q ); Inst_decodisa_dadrL_BU2471 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16413 ); Inst_decodisa_dadrL_BU2468 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16412 ); Inst_decodisa_dadrL_BU2463 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16341, ADR2 => Inst_decodisa_dadrL_N16342, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_222_Q ); Inst_decodisa_dadrL_BU2460 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16342 ); Inst_decodisa_dadrL_BU2457 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16341 ); Inst_decodisa_dadrL_BU2452 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16270, ADR2 => Inst_decodisa_dadrL_N16271, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_221_Q ); Inst_decodisa_dadrL_BU2449 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16271 ); Inst_decodisa_dadrL_BU2446 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16270 ); Inst_decodisa_dadrL_BU2441 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16199, ADR2 => Inst_decodisa_dadrL_N16200, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_220_Q ); Inst_decodisa_dadrL_BU2438 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16200 ); Inst_decodisa_dadrL_BU2435 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16199 ); Inst_decodisa_dadrL_BU2430 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16128, ADR2 => Inst_decodisa_dadrL_N16129, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_219_Q ); Inst_decodisa_dadrL_BU2427 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16129 ); Inst_decodisa_dadrL_BU2424 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16128 ); Inst_decodisa_dadrL_BU2419 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N16057, ADR2 => Inst_decodisa_dadrL_N16058, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_218_Q ); Inst_decodisa_dadrL_BU2416 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N16058 ); Inst_decodisa_dadrL_BU2413 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N16057 ); Inst_decodisa_dadrL_BU2408 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15986, ADR2 => Inst_decodisa_dadrL_N15987, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_217_Q ); Inst_decodisa_dadrL_BU2405 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15987 ); Inst_decodisa_dadrL_BU2402 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15986 ); Inst_decodisa_dadrL_BU2397 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15915, ADR2 => Inst_decodisa_dadrL_N15916, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_216_Q ); Inst_decodisa_dadrL_BU2394 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15916 ); Inst_decodisa_dadrL_BU2391 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15915 ); Inst_decodisa_dadrL_BU2386 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15844, ADR2 => Inst_decodisa_dadrL_N15845, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_215_Q ); Inst_decodisa_dadrL_BU2383 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15845 ); Inst_decodisa_dadrL_BU2380 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15844 ); Inst_decodisa_dadrL_BU2375 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15773, ADR2 => Inst_decodisa_dadrL_N15774, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_214_Q ); Inst_decodisa_dadrL_BU2372 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15774 ); Inst_decodisa_dadrL_BU2369 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15773 ); Inst_decodisa_dadrL_BU2364 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15702, ADR2 => Inst_decodisa_dadrL_N15703, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_213_Q ); Inst_decodisa_dadrL_BU2361 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15703 ); Inst_decodisa_dadrL_BU2358 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15702 ); Inst_decodisa_dadrL_BU2353 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15631, ADR2 => Inst_decodisa_dadrL_N15632, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_212_Q ); Inst_decodisa_dadrL_BU2350 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15632 ); Inst_decodisa_dadrL_BU2347 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15631 ); Inst_decodisa_dadrL_BU2342 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15560, ADR2 => Inst_decodisa_dadrL_N15561, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_211_Q ); Inst_decodisa_dadrL_BU2339 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15561 ); Inst_decodisa_dadrL_BU2336 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15560 ); Inst_decodisa_dadrL_BU2331 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15489, ADR2 => Inst_decodisa_dadrL_N15490, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_210_Q ); Inst_decodisa_dadrL_BU2328 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15490 ); Inst_decodisa_dadrL_BU2325 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15489 ); Inst_decodisa_dadrL_BU2320 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15418, ADR2 => Inst_decodisa_dadrL_N15419, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_209_Q ); Inst_decodisa_dadrL_BU2317 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15419 ); Inst_decodisa_dadrL_BU2314 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15418 ); Inst_decodisa_dadrL_BU2309 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15347, ADR2 => Inst_decodisa_dadrL_N15348, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_208_Q ); Inst_decodisa_dadrL_BU2306 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15348 ); Inst_decodisa_dadrL_BU2303 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15347 ); Inst_decodisa_dadrL_BU2298 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15276, ADR2 => Inst_decodisa_dadrL_N15277, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_207_Q ); Inst_decodisa_dadrL_BU2295 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15277 ); Inst_decodisa_dadrL_BU2292 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15276 ); Inst_decodisa_dadrL_BU2287 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15205, ADR2 => Inst_decodisa_dadrL_N15206, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_206_Q ); Inst_decodisa_dadrL_BU2284 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15206 ); Inst_decodisa_dadrL_BU2281 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15205 ); Inst_decodisa_dadrL_BU2276 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15134, ADR2 => Inst_decodisa_dadrL_N15135, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_205_Q ); Inst_decodisa_dadrL_BU2273 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15135 ); Inst_decodisa_dadrL_BU2270 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15134 ); Inst_decodisa_dadrL_BU2265 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N15063, ADR2 => Inst_decodisa_dadrL_N15064, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_204_Q ); Inst_decodisa_dadrL_BU2262 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N15064 ); Inst_decodisa_dadrL_BU2259 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N15063 ); Inst_decodisa_dadrL_BU2254 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14992, ADR2 => Inst_decodisa_dadrL_N14993, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_203_Q ); Inst_decodisa_dadrL_BU2251 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14993 ); Inst_decodisa_dadrL_BU2248 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14992 ); Inst_decodisa_dadrL_BU2243 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14921, ADR2 => Inst_decodisa_dadrL_N14922, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_202_Q ); Inst_decodisa_dadrL_BU2240 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14922 ); Inst_decodisa_dadrL_BU2237 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14921 ); Inst_decodisa_dadrL_BU2232 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14850, ADR2 => Inst_decodisa_dadrL_N14851, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_201_Q ); Inst_decodisa_dadrL_BU2229 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14851 ); Inst_decodisa_dadrL_BU2226 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14850 ); Inst_decodisa_dadrL_BU2221 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14779, ADR2 => Inst_decodisa_dadrL_N14780, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_200_Q ); Inst_decodisa_dadrL_BU2218 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14780 ); Inst_decodisa_dadrL_BU2215 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14779 ); Inst_decodisa_dadrL_BU2210 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14708, ADR2 => Inst_decodisa_dadrL_N14709, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_199_Q ); Inst_decodisa_dadrL_BU2207 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14709 ); Inst_decodisa_dadrL_BU2204 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14708 ); Inst_decodisa_dadrL_BU2199 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14637, ADR2 => Inst_decodisa_dadrL_N14638, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_198_Q ); Inst_decodisa_dadrL_BU2196 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14638 ); Inst_decodisa_dadrL_BU2193 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14637 ); Inst_decodisa_dadrL_BU2188 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14566, ADR2 => Inst_decodisa_dadrL_N14567, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_197_Q ); Inst_decodisa_dadrL_BU2185 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14567 ); Inst_decodisa_dadrL_BU2182 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14566 ); Inst_decodisa_dadrL_BU2177 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14495, ADR2 => Inst_decodisa_dadrL_N14496, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_196_Q ); Inst_decodisa_dadrL_BU2174 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14496 ); Inst_decodisa_dadrL_BU2171 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14495 ); Inst_decodisa_dadrL_BU2166 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14424, ADR2 => Inst_decodisa_dadrL_N14425, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_195_Q ); Inst_decodisa_dadrL_BU2163 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14425 ); Inst_decodisa_dadrL_BU2160 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14424 ); Inst_decodisa_dadrL_BU2155 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14353, ADR2 => Inst_decodisa_dadrL_N14354, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_194_Q ); Inst_decodisa_dadrL_BU2152 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14354 ); Inst_decodisa_dadrL_BU2149 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14353 ); Inst_decodisa_dadrL_BU2144 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14282, ADR2 => Inst_decodisa_dadrL_N14283, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_193_Q ); Inst_decodisa_dadrL_BU2141 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14283 ); Inst_decodisa_dadrL_BU2138 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14282 ); Inst_decodisa_dadrL_BU2133 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14211, ADR2 => Inst_decodisa_dadrL_N14212, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_192_Q ); Inst_decodisa_dadrL_BU2130 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14212 ); Inst_decodisa_dadrL_BU2127 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14211 ); Inst_decodisa_dadrL_BU2122 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14140, ADR2 => Inst_decodisa_dadrL_N14141, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_191_Q ); Inst_decodisa_dadrL_BU2119 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14141 ); Inst_decodisa_dadrL_BU2116 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14140 ); Inst_decodisa_dadrL_BU2111 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N14069, ADR2 => Inst_decodisa_dadrL_N14070, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_190_Q ); Inst_decodisa_dadrL_BU2108 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N14070 ); Inst_decodisa_dadrL_BU2105 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N14069 ); Inst_decodisa_dadrL_BU2100 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13998, ADR2 => Inst_decodisa_dadrL_N13999, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_189_Q ); Inst_decodisa_dadrL_BU2097 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13999 ); Inst_decodisa_dadrL_BU2094 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13998 ); Inst_decodisa_dadrL_BU2089 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13927, ADR2 => Inst_decodisa_dadrL_N13928, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_188_Q ); Inst_decodisa_dadrL_BU2086 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13928 ); Inst_decodisa_dadrL_BU2083 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13927 ); Inst_decodisa_dadrL_BU2078 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13856, ADR2 => Inst_decodisa_dadrL_N13857, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_187_Q ); Inst_decodisa_dadrL_BU2075 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13857 ); Inst_decodisa_dadrL_BU2072 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13856 ); Inst_decodisa_dadrL_BU2067 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13785, ADR2 => Inst_decodisa_dadrL_N13786, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_186_Q ); Inst_decodisa_dadrL_BU2064 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13786 ); Inst_decodisa_dadrL_BU2061 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13785 ); Inst_decodisa_dadrL_BU2056 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13714, ADR2 => Inst_decodisa_dadrL_N13715, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_185_Q ); Inst_decodisa_dadrL_BU2053 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13715 ); Inst_decodisa_dadrL_BU2050 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13714 ); Inst_decodisa_dadrL_BU2045 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13643, ADR2 => Inst_decodisa_dadrL_N13644, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_184_Q ); Inst_decodisa_dadrL_BU2042 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13644 ); Inst_decodisa_dadrL_BU2039 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13643 ); Inst_decodisa_dadrL_BU2034 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13572, ADR2 => Inst_decodisa_dadrL_N13573, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_183_Q ); Inst_decodisa_dadrL_BU2031 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13573 ); Inst_decodisa_dadrL_BU2028 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13572 ); Inst_decodisa_dadrL_BU2023 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13501, ADR2 => Inst_decodisa_dadrL_N13502, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_182_Q ); Inst_decodisa_dadrL_BU2020 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13502 ); Inst_decodisa_dadrL_BU2017 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13501 ); Inst_decodisa_dadrL_BU2012 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13430, ADR2 => Inst_decodisa_dadrL_N13431, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_181_Q ); Inst_decodisa_dadrL_BU2009 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13431 ); Inst_decodisa_dadrL_BU2006 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13430 ); Inst_decodisa_dadrL_BU2001 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13359, ADR2 => Inst_decodisa_dadrL_N13360, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_180_Q ); Inst_decodisa_dadrL_BU1998 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13360 ); Inst_decodisa_dadrL_BU1995 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13359 ); Inst_decodisa_dadrL_BU1990 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13288, ADR2 => Inst_decodisa_dadrL_N13289, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_179_Q ); Inst_decodisa_dadrL_BU1987 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13289 ); Inst_decodisa_dadrL_BU1984 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13288 ); Inst_decodisa_dadrL_BU1979 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13217, ADR2 => Inst_decodisa_dadrL_N13218, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_178_Q ); Inst_decodisa_dadrL_BU1976 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13218 ); Inst_decodisa_dadrL_BU1973 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13217 ); Inst_decodisa_dadrL_BU1968 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13146, ADR2 => Inst_decodisa_dadrL_N13147, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_177_Q ); Inst_decodisa_dadrL_BU1965 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13147 ); Inst_decodisa_dadrL_BU1962 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13146 ); Inst_decodisa_dadrL_BU1957 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13075, ADR2 => Inst_decodisa_dadrL_N13076, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_176_Q ); Inst_decodisa_dadrL_BU1954 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13076 ); Inst_decodisa_dadrL_BU1951 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13075 ); Inst_decodisa_dadrL_BU1946 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N13004, ADR2 => Inst_decodisa_dadrL_N13005, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_175_Q ); Inst_decodisa_dadrL_BU1943 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N13005 ); Inst_decodisa_dadrL_BU1940 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N13004 ); Inst_decodisa_dadrL_BU1935 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12933, ADR2 => Inst_decodisa_dadrL_N12934, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_174_Q ); Inst_decodisa_dadrL_BU1932 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12934 ); Inst_decodisa_dadrL_BU1929 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12933 ); Inst_decodisa_dadrL_BU1924 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12862, ADR2 => Inst_decodisa_dadrL_N12863, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_173_Q ); Inst_decodisa_dadrL_BU1921 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12863 ); Inst_decodisa_dadrL_BU1918 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12862 ); Inst_decodisa_dadrL_BU1913 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12791, ADR2 => Inst_decodisa_dadrL_N12792, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_172_Q ); Inst_decodisa_dadrL_BU1910 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12792 ); Inst_decodisa_dadrL_BU1907 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12791 ); Inst_decodisa_dadrL_BU1902 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12720, ADR2 => Inst_decodisa_dadrL_N12721, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_171_Q ); Inst_decodisa_dadrL_BU1899 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12721 ); Inst_decodisa_dadrL_BU1896 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12720 ); Inst_decodisa_dadrL_BU1891 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12649, ADR2 => Inst_decodisa_dadrL_N12650, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_170_Q ); Inst_decodisa_dadrL_BU1888 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12650 ); Inst_decodisa_dadrL_BU1885 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12649 ); Inst_decodisa_dadrL_BU1880 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12578, ADR2 => Inst_decodisa_dadrL_N12579, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_169_Q ); Inst_decodisa_dadrL_BU1877 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12579 ); Inst_decodisa_dadrL_BU1874 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12578 ); Inst_decodisa_dadrL_BU1869 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12507, ADR2 => Inst_decodisa_dadrL_N12508, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_168_Q ); Inst_decodisa_dadrL_BU1866 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12508 ); Inst_decodisa_dadrL_BU1863 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12507 ); Inst_decodisa_dadrL_BU1858 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12436, ADR2 => Inst_decodisa_dadrL_N12437, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_167_Q ); Inst_decodisa_dadrL_BU1855 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12437 ); Inst_decodisa_dadrL_BU1852 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12436 ); Inst_decodisa_dadrL_BU1847 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12365, ADR2 => Inst_decodisa_dadrL_N12366, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_166_Q ); Inst_decodisa_dadrL_BU1844 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12366 ); Inst_decodisa_dadrL_BU1841 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12365 ); Inst_decodisa_dadrL_BU1836 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12294, ADR2 => Inst_decodisa_dadrL_N12295, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_165_Q ); Inst_decodisa_dadrL_BU1833 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12295 ); Inst_decodisa_dadrL_BU1830 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12294 ); Inst_decodisa_dadrL_BU1825 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12223, ADR2 => Inst_decodisa_dadrL_N12224, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_164_Q ); Inst_decodisa_dadrL_BU1822 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12224 ); Inst_decodisa_dadrL_BU1819 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12223 ); Inst_decodisa_dadrL_BU1814 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12152, ADR2 => Inst_decodisa_dadrL_N12153, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_163_Q ); Inst_decodisa_dadrL_BU1811 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12153 ); Inst_decodisa_dadrL_BU1808 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12152 ); Inst_decodisa_dadrL_BU1803 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12081, ADR2 => Inst_decodisa_dadrL_N12082, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_162_Q ); Inst_decodisa_dadrL_BU1800 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12082 ); Inst_decodisa_dadrL_BU1797 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12081 ); Inst_decodisa_dadrL_BU1792 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N12010, ADR2 => Inst_decodisa_dadrL_N12011, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_161_Q ); Inst_decodisa_dadrL_BU1789 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N12011 ); Inst_decodisa_dadrL_BU1786 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N12010 ); Inst_decodisa_dadrL_BU1781 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11939, ADR2 => Inst_decodisa_dadrL_N11940, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_160_Q ); Inst_decodisa_dadrL_BU1778 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11940 ); Inst_decodisa_dadrL_BU1775 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11939 ); Inst_decodisa_dadrL_BU1770 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11868, ADR2 => Inst_decodisa_dadrL_N11869, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_159_Q ); Inst_decodisa_dadrL_BU1767 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11869 ); Inst_decodisa_dadrL_BU1764 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11868 ); Inst_decodisa_dadrL_BU1759 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11797, ADR2 => Inst_decodisa_dadrL_N11798, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_158_Q ); Inst_decodisa_dadrL_BU1756 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11798 ); Inst_decodisa_dadrL_BU1753 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11797 ); Inst_decodisa_dadrL_BU1748 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11726, ADR2 => Inst_decodisa_dadrL_N11727, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_157_Q ); Inst_decodisa_dadrL_BU1745 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11727 ); Inst_decodisa_dadrL_BU1742 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11726 ); Inst_decodisa_dadrL_BU1737 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11655, ADR2 => Inst_decodisa_dadrL_N11656, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_156_Q ); Inst_decodisa_dadrL_BU1734 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11656 ); Inst_decodisa_dadrL_BU1731 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11655 ); Inst_decodisa_dadrL_BU1726 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11584, ADR2 => Inst_decodisa_dadrL_N11585, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_155_Q ); Inst_decodisa_dadrL_BU1723 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11585 ); Inst_decodisa_dadrL_BU1720 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11584 ); Inst_decodisa_dadrL_BU1715 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11513, ADR2 => Inst_decodisa_dadrL_N11514, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_154_Q ); Inst_decodisa_dadrL_BU1712 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11514 ); Inst_decodisa_dadrL_BU1709 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11513 ); Inst_decodisa_dadrL_BU1704 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11442, ADR2 => Inst_decodisa_dadrL_N11443, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_153_Q ); Inst_decodisa_dadrL_BU1701 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11443 ); Inst_decodisa_dadrL_BU1698 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11442 ); Inst_decodisa_dadrL_BU1693 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11371, ADR2 => Inst_decodisa_dadrL_N11372, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_152_Q ); Inst_decodisa_dadrL_BU1690 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11372 ); Inst_decodisa_dadrL_BU1687 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11371 ); Inst_decodisa_dadrL_BU1682 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11300, ADR2 => Inst_decodisa_dadrL_N11301, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_151_Q ); Inst_decodisa_dadrL_BU1679 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11301 ); Inst_decodisa_dadrL_BU1676 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11300 ); Inst_decodisa_dadrL_BU1671 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11229, ADR2 => Inst_decodisa_dadrL_N11230, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_150_Q ); Inst_decodisa_dadrL_BU1668 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11230 ); Inst_decodisa_dadrL_BU1665 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11229 ); Inst_decodisa_dadrL_BU1660 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11158, ADR2 => Inst_decodisa_dadrL_N11159, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_149_Q ); Inst_decodisa_dadrL_BU1657 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11159 ); Inst_decodisa_dadrL_BU1654 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11158 ); Inst_decodisa_dadrL_BU1649 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11087, ADR2 => Inst_decodisa_dadrL_N11088, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_148_Q ); Inst_decodisa_dadrL_BU1646 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11088 ); Inst_decodisa_dadrL_BU1643 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11087 ); Inst_decodisa_dadrL_BU1638 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N11016, ADR2 => Inst_decodisa_dadrL_N11017, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_147_Q ); Inst_decodisa_dadrL_BU1635 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N11017 ); Inst_decodisa_dadrL_BU1632 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N11016 ); Inst_decodisa_dadrL_BU1627 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10945, ADR2 => Inst_decodisa_dadrL_N10946, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_146_Q ); Inst_decodisa_dadrL_BU1624 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10946 ); Inst_decodisa_dadrL_BU1621 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10945 ); Inst_decodisa_dadrL_BU1616 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10874, ADR2 => Inst_decodisa_dadrL_N10875, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_145_Q ); Inst_decodisa_dadrL_BU1613 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10875 ); Inst_decodisa_dadrL_BU1610 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10874 ); Inst_decodisa_dadrL_BU1605 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10803, ADR2 => Inst_decodisa_dadrL_N10804, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_144_Q ); Inst_decodisa_dadrL_BU1602 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10804 ); Inst_decodisa_dadrL_BU1599 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10803 ); Inst_decodisa_dadrL_BU1594 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10732, ADR2 => Inst_decodisa_dadrL_N10733, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_143_Q ); Inst_decodisa_dadrL_BU1591 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10733 ); Inst_decodisa_dadrL_BU1588 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10732 ); Inst_decodisa_dadrL_BU1583 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10661, ADR2 => Inst_decodisa_dadrL_N10662, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_142_Q ); Inst_decodisa_dadrL_BU1580 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10662 ); Inst_decodisa_dadrL_BU1577 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10661 ); Inst_decodisa_dadrL_BU1572 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10590, ADR2 => Inst_decodisa_dadrL_N10591, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_141_Q ); Inst_decodisa_dadrL_BU1569 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10591 ); Inst_decodisa_dadrL_BU1566 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10590 ); Inst_decodisa_dadrL_BU1561 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10519, ADR2 => Inst_decodisa_dadrL_N10520, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_140_Q ); Inst_decodisa_dadrL_BU1558 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10520 ); Inst_decodisa_dadrL_BU1555 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10519 ); Inst_decodisa_dadrL_BU1550 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10448, ADR2 => Inst_decodisa_dadrL_N10449, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_139_Q ); Inst_decodisa_dadrL_BU1547 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10449 ); Inst_decodisa_dadrL_BU1544 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10448 ); Inst_decodisa_dadrL_BU1539 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10377, ADR2 => Inst_decodisa_dadrL_N10378, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_138_Q ); Inst_decodisa_dadrL_BU1536 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10378 ); Inst_decodisa_dadrL_BU1533 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10377 ); Inst_decodisa_dadrL_BU1528 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10306, ADR2 => Inst_decodisa_dadrL_N10307, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_137_Q ); Inst_decodisa_dadrL_BU1525 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10307 ); Inst_decodisa_dadrL_BU1522 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10306 ); Inst_decodisa_dadrL_BU1517 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10235, ADR2 => Inst_decodisa_dadrL_N10236, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_136_Q ); Inst_decodisa_dadrL_BU1514 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10236 ); Inst_decodisa_dadrL_BU1511 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10235 ); Inst_decodisa_dadrL_BU1506 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10164, ADR2 => Inst_decodisa_dadrL_N10165, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_135_Q ); Inst_decodisa_dadrL_BU1503 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10165 ); Inst_decodisa_dadrL_BU1500 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10164 ); Inst_decodisa_dadrL_BU1495 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10093, ADR2 => Inst_decodisa_dadrL_N10094, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_134_Q ); Inst_decodisa_dadrL_BU1492 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10094 ); Inst_decodisa_dadrL_BU1489 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10093 ); Inst_decodisa_dadrL_BU1484 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N10022, ADR2 => Inst_decodisa_dadrL_N10023, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_133_Q ); Inst_decodisa_dadrL_BU1481 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N10023 ); Inst_decodisa_dadrL_BU1478 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N10022 ); Inst_decodisa_dadrL_BU1473 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9951, ADR2 => Inst_decodisa_dadrL_N9952, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_132_Q ); Inst_decodisa_dadrL_BU1470 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9952 ); Inst_decodisa_dadrL_BU1467 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9951 ); Inst_decodisa_dadrL_BU1462 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9880, ADR2 => Inst_decodisa_dadrL_N9881, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_131_Q ); Inst_decodisa_dadrL_BU1459 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9881 ); Inst_decodisa_dadrL_BU1456 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9880 ); Inst_decodisa_dadrL_BU1451 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9809, ADR2 => Inst_decodisa_dadrL_N9810, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_130_Q ); Inst_decodisa_dadrL_BU1448 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9810 ); Inst_decodisa_dadrL_BU1445 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9809 ); Inst_decodisa_dadrL_BU1440 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9738, ADR2 => Inst_decodisa_dadrL_N9739, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_129_Q ); Inst_decodisa_dadrL_BU1437 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9739 ); Inst_decodisa_dadrL_BU1434 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9738 ); Inst_decodisa_dadrL_BU1429 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9667, ADR2 => Inst_decodisa_dadrL_N9668, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_128_Q ); Inst_decodisa_dadrL_BU1426 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9668 ); Inst_decodisa_dadrL_BU1423 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9667 ); Inst_decodisa_dadrL_BU1418 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9596, ADR2 => Inst_decodisa_dadrL_N9597, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_127_Q ); Inst_decodisa_dadrL_BU1415 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9597 ); Inst_decodisa_dadrL_BU1412 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9596 ); Inst_decodisa_dadrL_BU1407 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9525, ADR2 => Inst_decodisa_dadrL_N9526, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_126_Q ); Inst_decodisa_dadrL_BU1404 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9526 ); Inst_decodisa_dadrL_BU1401 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9525 ); Inst_decodisa_dadrL_BU1396 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9454, ADR2 => Inst_decodisa_dadrL_N9455, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_125_Q ); Inst_decodisa_dadrL_BU1393 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9455 ); Inst_decodisa_dadrL_BU1390 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9454 ); Inst_decodisa_dadrL_BU1385 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9383, ADR2 => Inst_decodisa_dadrL_N9384, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_124_Q ); Inst_decodisa_dadrL_BU1382 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9384 ); Inst_decodisa_dadrL_BU1379 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9383 ); Inst_decodisa_dadrL_BU1374 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9312, ADR2 => Inst_decodisa_dadrL_N9313, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_123_Q ); Inst_decodisa_dadrL_BU1371 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9313 ); Inst_decodisa_dadrL_BU1368 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9312 ); Inst_decodisa_dadrL_BU1363 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9241, ADR2 => Inst_decodisa_dadrL_N9242, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_122_Q ); Inst_decodisa_dadrL_BU1360 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9242 ); Inst_decodisa_dadrL_BU1357 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9241 ); Inst_decodisa_dadrL_BU1352 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9170, ADR2 => Inst_decodisa_dadrL_N9171, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_121_Q ); Inst_decodisa_dadrL_BU1349 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9171 ); Inst_decodisa_dadrL_BU1346 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9170 ); Inst_decodisa_dadrL_BU1341 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9099, ADR2 => Inst_decodisa_dadrL_N9100, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_120_Q ); Inst_decodisa_dadrL_BU1338 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9100 ); Inst_decodisa_dadrL_BU1335 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9099 ); Inst_decodisa_dadrL_BU1330 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N9028, ADR2 => Inst_decodisa_dadrL_N9029, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_119_Q ); Inst_decodisa_dadrL_BU1327 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N9029 ); Inst_decodisa_dadrL_BU1324 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N9028 ); Inst_decodisa_dadrL_BU1319 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8957, ADR2 => Inst_decodisa_dadrL_N8958, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_118_Q ); Inst_decodisa_dadrL_BU1316 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8958 ); Inst_decodisa_dadrL_BU1313 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8957 ); Inst_decodisa_dadrL_BU1308 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8886, ADR2 => Inst_decodisa_dadrL_N8887, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_117_Q ); Inst_decodisa_dadrL_BU1305 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8887 ); Inst_decodisa_dadrL_BU1302 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8886 ); Inst_decodisa_dadrL_BU1297 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8815, ADR2 => Inst_decodisa_dadrL_N8816, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_116_Q ); Inst_decodisa_dadrL_BU1294 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8816 ); Inst_decodisa_dadrL_BU1291 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8815 ); Inst_decodisa_dadrL_BU1286 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8744, ADR2 => Inst_decodisa_dadrL_N8745, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_115_Q ); Inst_decodisa_dadrL_BU1283 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8745 ); Inst_decodisa_dadrL_BU1280 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8744 ); Inst_decodisa_dadrL_BU1275 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8673, ADR2 => Inst_decodisa_dadrL_N8674, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_114_Q ); Inst_decodisa_dadrL_BU1272 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8674 ); Inst_decodisa_dadrL_BU1269 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8673 ); Inst_decodisa_dadrL_BU1264 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8602, ADR2 => Inst_decodisa_dadrL_N8603, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_113_Q ); Inst_decodisa_dadrL_BU1261 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8603 ); Inst_decodisa_dadrL_BU1258 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8602 ); Inst_decodisa_dadrL_BU1253 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8531, ADR2 => Inst_decodisa_dadrL_N8532, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_112_Q ); Inst_decodisa_dadrL_BU1250 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8532 ); Inst_decodisa_dadrL_BU1247 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8531 ); Inst_decodisa_dadrL_BU1242 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8460, ADR2 => Inst_decodisa_dadrL_N8461, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_111_Q ); Inst_decodisa_dadrL_BU1239 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8461 ); Inst_decodisa_dadrL_BU1236 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8460 ); Inst_decodisa_dadrL_BU1231 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8389, ADR2 => Inst_decodisa_dadrL_N8390, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_110_Q ); Inst_decodisa_dadrL_BU1228 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8390 ); Inst_decodisa_dadrL_BU1225 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8389 ); Inst_decodisa_dadrL_BU1220 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8318, ADR2 => Inst_decodisa_dadrL_N8319, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_109_Q ); Inst_decodisa_dadrL_BU1217 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8319 ); Inst_decodisa_dadrL_BU1214 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8318 ); Inst_decodisa_dadrL_BU1209 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8247, ADR2 => Inst_decodisa_dadrL_N8248, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_108_Q ); Inst_decodisa_dadrL_BU1206 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8248 ); Inst_decodisa_dadrL_BU1203 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8247 ); Inst_decodisa_dadrL_BU1198 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8176, ADR2 => Inst_decodisa_dadrL_N8177, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_107_Q ); Inst_decodisa_dadrL_BU1195 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8177 ); Inst_decodisa_dadrL_BU1192 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8176 ); Inst_decodisa_dadrL_BU1187 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8105, ADR2 => Inst_decodisa_dadrL_N8106, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_106_Q ); Inst_decodisa_dadrL_BU1184 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8106 ); Inst_decodisa_dadrL_BU1181 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8105 ); Inst_decodisa_dadrL_BU1176 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N8034, ADR2 => Inst_decodisa_dadrL_N8035, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_105_Q ); Inst_decodisa_dadrL_BU1173 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N8035 ); Inst_decodisa_dadrL_BU1170 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N8034 ); Inst_decodisa_dadrL_BU1165 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7963, ADR2 => Inst_decodisa_dadrL_N7964, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_104_Q ); Inst_decodisa_dadrL_BU1162 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7964 ); Inst_decodisa_dadrL_BU1159 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7963 ); Inst_decodisa_dadrL_BU1154 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7892, ADR2 => Inst_decodisa_dadrL_N7893, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_103_Q ); Inst_decodisa_dadrL_BU1151 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7893 ); Inst_decodisa_dadrL_BU1148 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7892 ); Inst_decodisa_dadrL_BU1143 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7821, ADR2 => Inst_decodisa_dadrL_N7822, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_102_Q ); Inst_decodisa_dadrL_BU1140 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7822 ); Inst_decodisa_dadrL_BU1137 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7821 ); Inst_decodisa_dadrL_BU1132 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7750, ADR2 => Inst_decodisa_dadrL_N7751, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_101_Q ); Inst_decodisa_dadrL_BU1129 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7751 ); Inst_decodisa_dadrL_BU1126 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7750 ); Inst_decodisa_dadrL_BU1121 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7679, ADR2 => Inst_decodisa_dadrL_N7680, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_100_Q ); Inst_decodisa_dadrL_BU1118 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7680 ); Inst_decodisa_dadrL_BU1115 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7679 ); Inst_decodisa_dadrL_BU1110 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7608, ADR2 => Inst_decodisa_dadrL_N7609, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_99_Q ); Inst_decodisa_dadrL_BU1107 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7609 ); Inst_decodisa_dadrL_BU1104 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7608 ); Inst_decodisa_dadrL_BU1099 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7537, ADR2 => Inst_decodisa_dadrL_N7538, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_98_Q ); Inst_decodisa_dadrL_BU1096 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7538 ); Inst_decodisa_dadrL_BU1093 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7537 ); Inst_decodisa_dadrL_BU1088 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7466, ADR2 => Inst_decodisa_dadrL_N7467, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_97_Q ); Inst_decodisa_dadrL_BU1085 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7467 ); Inst_decodisa_dadrL_BU1082 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7466 ); Inst_decodisa_dadrL_BU1077 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7395, ADR2 => Inst_decodisa_dadrL_N7396, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_96_Q ); Inst_decodisa_dadrL_BU1074 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7396 ); Inst_decodisa_dadrL_BU1071 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7395 ); Inst_decodisa_dadrL_BU1066 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7324, ADR2 => Inst_decodisa_dadrL_N7325, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_95_Q ); Inst_decodisa_dadrL_BU1063 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7325 ); Inst_decodisa_dadrL_BU1060 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7324 ); Inst_decodisa_dadrL_BU1055 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7253, ADR2 => Inst_decodisa_dadrL_N7254, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_94_Q ); Inst_decodisa_dadrL_BU1052 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7254 ); Inst_decodisa_dadrL_BU1049 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7253 ); Inst_decodisa_dadrL_BU1044 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7182, ADR2 => Inst_decodisa_dadrL_N7183, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_93_Q ); Inst_decodisa_dadrL_BU1041 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7183 ); Inst_decodisa_dadrL_BU1038 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7182 ); Inst_decodisa_dadrL_BU1033 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7111, ADR2 => Inst_decodisa_dadrL_N7112, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_92_Q ); Inst_decodisa_dadrL_BU1030 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7112 ); Inst_decodisa_dadrL_BU1027 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7111 ); Inst_decodisa_dadrL_BU1022 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N7040, ADR2 => Inst_decodisa_dadrL_N7041, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_91_Q ); Inst_decodisa_dadrL_BU1019 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N7041 ); Inst_decodisa_dadrL_BU1016 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N7040 ); Inst_decodisa_dadrL_BU1011 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6969, ADR2 => Inst_decodisa_dadrL_N6970, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_90_Q ); Inst_decodisa_dadrL_BU1008 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6970 ); Inst_decodisa_dadrL_BU1005 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6969 ); Inst_decodisa_dadrL_BU1000 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6898, ADR2 => Inst_decodisa_dadrL_N6899, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_89_Q ); Inst_decodisa_dadrL_BU997 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6899 ); Inst_decodisa_dadrL_BU994 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6898 ); Inst_decodisa_dadrL_BU989 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6827, ADR2 => Inst_decodisa_dadrL_N6828, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_88_Q ); Inst_decodisa_dadrL_BU986 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6828 ); Inst_decodisa_dadrL_BU983 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6827 ); Inst_decodisa_dadrL_BU978 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6756, ADR2 => Inst_decodisa_dadrL_N6757, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_87_Q ); Inst_decodisa_dadrL_BU975 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6757 ); Inst_decodisa_dadrL_BU972 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6756 ); Inst_decodisa_dadrL_BU967 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6685, ADR2 => Inst_decodisa_dadrL_N6686, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_86_Q ); Inst_decodisa_dadrL_BU964 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6686 ); Inst_decodisa_dadrL_BU961 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6685 ); Inst_decodisa_dadrL_BU956 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6614, ADR2 => Inst_decodisa_dadrL_N6615, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_85_Q ); Inst_decodisa_dadrL_BU953 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6615 ); Inst_decodisa_dadrL_BU950 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6614 ); Inst_decodisa_dadrL_BU945 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6543, ADR2 => Inst_decodisa_dadrL_N6544, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_84_Q ); Inst_decodisa_dadrL_BU942 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6544 ); Inst_decodisa_dadrL_BU939 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6543 ); Inst_decodisa_dadrL_BU934 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6472, ADR2 => Inst_decodisa_dadrL_N6473, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_83_Q ); Inst_decodisa_dadrL_BU931 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6473 ); Inst_decodisa_dadrL_BU928 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6472 ); Inst_decodisa_dadrL_BU923 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6401, ADR2 => Inst_decodisa_dadrL_N6402, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_82_Q ); Inst_decodisa_dadrL_BU920 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6402 ); Inst_decodisa_dadrL_BU917 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6401 ); Inst_decodisa_dadrL_BU912 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6330, ADR2 => Inst_decodisa_dadrL_N6331, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_81_Q ); Inst_decodisa_dadrL_BU909 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6331 ); Inst_decodisa_dadrL_BU906 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6330 ); Inst_decodisa_dadrL_BU901 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6259, ADR2 => Inst_decodisa_dadrL_N6260, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_80_Q ); Inst_decodisa_dadrL_BU898 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6260 ); Inst_decodisa_dadrL_BU895 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6259 ); Inst_decodisa_dadrL_BU890 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6188, ADR2 => Inst_decodisa_dadrL_N6189, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_79_Q ); Inst_decodisa_dadrL_BU887 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6189 ); Inst_decodisa_dadrL_BU884 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6188 ); Inst_decodisa_dadrL_BU879 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6117, ADR2 => Inst_decodisa_dadrL_N6118, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_78_Q ); Inst_decodisa_dadrL_BU876 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6118 ); Inst_decodisa_dadrL_BU873 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6117 ); Inst_decodisa_dadrL_BU868 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N6046, ADR2 => Inst_decodisa_dadrL_N6047, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_77_Q ); Inst_decodisa_dadrL_BU865 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N6047 ); Inst_decodisa_dadrL_BU862 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N6046 ); Inst_decodisa_dadrL_BU857 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5975, ADR2 => Inst_decodisa_dadrL_N5976, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_76_Q ); Inst_decodisa_dadrL_BU854 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5976 ); Inst_decodisa_dadrL_BU851 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5975 ); Inst_decodisa_dadrL_BU846 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5904, ADR2 => Inst_decodisa_dadrL_N5905, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_75_Q ); Inst_decodisa_dadrL_BU843 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5905 ); Inst_decodisa_dadrL_BU840 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5904 ); Inst_decodisa_dadrL_BU835 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5833, ADR2 => Inst_decodisa_dadrL_N5834, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_74_Q ); Inst_decodisa_dadrL_BU832 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5834 ); Inst_decodisa_dadrL_BU829 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5833 ); Inst_decodisa_dadrL_BU824 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5762, ADR2 => Inst_decodisa_dadrL_N5763, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_73_Q ); Inst_decodisa_dadrL_BU821 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5763 ); Inst_decodisa_dadrL_BU818 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5762 ); Inst_decodisa_dadrL_BU813 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5691, ADR2 => Inst_decodisa_dadrL_N5692, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_72_Q ); Inst_decodisa_dadrL_BU810 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5692 ); Inst_decodisa_dadrL_BU807 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5691 ); Inst_decodisa_dadrL_BU802 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5620, ADR2 => Inst_decodisa_dadrL_N5621, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_71_Q ); Inst_decodisa_dadrL_BU799 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5621 ); Inst_decodisa_dadrL_BU796 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5620 ); Inst_decodisa_dadrL_BU791 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5549, ADR2 => Inst_decodisa_dadrL_N5550, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_70_Q ); Inst_decodisa_dadrL_BU788 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5550 ); Inst_decodisa_dadrL_BU785 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5549 ); Inst_decodisa_dadrL_BU780 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5478, ADR2 => Inst_decodisa_dadrL_N5479, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_69_Q ); Inst_decodisa_dadrL_BU777 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5479 ); Inst_decodisa_dadrL_BU774 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5478 ); Inst_decodisa_dadrL_BU769 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5407, ADR2 => Inst_decodisa_dadrL_N5408, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_68_Q ); Inst_decodisa_dadrL_BU766 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5408 ); Inst_decodisa_dadrL_BU763 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5407 ); Inst_decodisa_dadrL_BU758 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5336, ADR2 => Inst_decodisa_dadrL_N5337, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_67_Q ); Inst_decodisa_dadrL_BU755 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5337 ); Inst_decodisa_dadrL_BU752 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5336 ); Inst_decodisa_dadrL_BU747 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5265, ADR2 => Inst_decodisa_dadrL_N5266, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_66_Q ); Inst_decodisa_dadrL_BU744 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5266 ); Inst_decodisa_dadrL_BU741 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5265 ); Inst_decodisa_dadrL_BU736 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5194, ADR2 => Inst_decodisa_dadrL_N5195, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_65_Q ); Inst_decodisa_dadrL_BU733 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5195 ); Inst_decodisa_dadrL_BU730 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5194 ); Inst_decodisa_dadrL_BU725 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5123, ADR2 => Inst_decodisa_dadrL_N5124, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_64_Q ); Inst_decodisa_dadrL_BU722 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5124 ); Inst_decodisa_dadrL_BU719 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5123 ); Inst_decodisa_dadrL_BU714 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N5052, ADR2 => Inst_decodisa_dadrL_N5053, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_63_Q ); Inst_decodisa_dadrL_BU711 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N5053 ); Inst_decodisa_dadrL_BU708 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N5052 ); Inst_decodisa_dadrL_BU703 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4981, ADR2 => Inst_decodisa_dadrL_N4982, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_62_Q ); Inst_decodisa_dadrL_BU700 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4982 ); Inst_decodisa_dadrL_BU697 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4981 ); Inst_decodisa_dadrL_BU692 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4910, ADR2 => Inst_decodisa_dadrL_N4911, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_61_Q ); Inst_decodisa_dadrL_BU689 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4911 ); Inst_decodisa_dadrL_BU686 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4910 ); Inst_decodisa_dadrL_BU681 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4839, ADR2 => Inst_decodisa_dadrL_N4840, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_60_Q ); Inst_decodisa_dadrL_BU678 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4840 ); Inst_decodisa_dadrL_BU675 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4839 ); Inst_decodisa_dadrL_BU670 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4768, ADR2 => Inst_decodisa_dadrL_N4769, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_59_Q ); Inst_decodisa_dadrL_BU667 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4769 ); Inst_decodisa_dadrL_BU664 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4768 ); Inst_decodisa_dadrL_BU659 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4697, ADR2 => Inst_decodisa_dadrL_N4698, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_58_Q ); Inst_decodisa_dadrL_BU656 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4698 ); Inst_decodisa_dadrL_BU653 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4697 ); Inst_decodisa_dadrL_BU648 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4626, ADR2 => Inst_decodisa_dadrL_N4627, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_57_Q ); Inst_decodisa_dadrL_BU645 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4627 ); Inst_decodisa_dadrL_BU642 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4626 ); Inst_decodisa_dadrL_BU637 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4555, ADR2 => Inst_decodisa_dadrL_N4556, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_56_Q ); Inst_decodisa_dadrL_BU634 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4556 ); Inst_decodisa_dadrL_BU631 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4555 ); Inst_decodisa_dadrL_BU626 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4484, ADR2 => Inst_decodisa_dadrL_N4485, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_55_Q ); Inst_decodisa_dadrL_BU623 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4485 ); Inst_decodisa_dadrL_BU620 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4484 ); Inst_decodisa_dadrL_BU615 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4413, ADR2 => Inst_decodisa_dadrL_N4414, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_54_Q ); Inst_decodisa_dadrL_BU612 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4414 ); Inst_decodisa_dadrL_BU609 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4413 ); Inst_decodisa_dadrL_BU604 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4342, ADR2 => Inst_decodisa_dadrL_N4343, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_53_Q ); Inst_decodisa_dadrL_BU601 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4343 ); Inst_decodisa_dadrL_BU598 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4342 ); Inst_decodisa_dadrL_BU593 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4271, ADR2 => Inst_decodisa_dadrL_N4272, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_52_Q ); Inst_decodisa_dadrL_BU590 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4272 ); Inst_decodisa_dadrL_BU587 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4271 ); Inst_decodisa_dadrL_BU582 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4200, ADR2 => Inst_decodisa_dadrL_N4201, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_51_Q ); Inst_decodisa_dadrL_BU579 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4201 ); Inst_decodisa_dadrL_BU576 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4200 ); Inst_decodisa_dadrL_BU571 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4129, ADR2 => Inst_decodisa_dadrL_N4130, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_50_Q ); Inst_decodisa_dadrL_BU568 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4130 ); Inst_decodisa_dadrL_BU565 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4129 ); Inst_decodisa_dadrL_BU560 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N4058, ADR2 => Inst_decodisa_dadrL_N4059, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_49_Q ); Inst_decodisa_dadrL_BU557 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N4059 ); Inst_decodisa_dadrL_BU554 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N4058 ); Inst_decodisa_dadrL_BU549 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3987, ADR2 => Inst_decodisa_dadrL_N3988, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_48_Q ); Inst_decodisa_dadrL_BU546 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3988 ); Inst_decodisa_dadrL_BU543 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3987 ); Inst_decodisa_dadrL_BU538 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3916, ADR2 => Inst_decodisa_dadrL_N3917, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_47_Q ); Inst_decodisa_dadrL_BU535 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3917 ); Inst_decodisa_dadrL_BU532 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3916 ); Inst_decodisa_dadrL_BU527 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3845, ADR2 => Inst_decodisa_dadrL_N3846, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_46_Q ); Inst_decodisa_dadrL_BU524 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3846 ); Inst_decodisa_dadrL_BU521 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3845 ); Inst_decodisa_dadrL_BU516 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3774, ADR2 => Inst_decodisa_dadrL_N3775, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_45_Q ); Inst_decodisa_dadrL_BU513 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3775 ); Inst_decodisa_dadrL_BU510 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3774 ); Inst_decodisa_dadrL_BU505 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3703, ADR2 => Inst_decodisa_dadrL_N3704, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_44_Q ); Inst_decodisa_dadrL_BU502 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3704 ); Inst_decodisa_dadrL_BU499 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3703 ); Inst_decodisa_dadrL_BU494 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3632, ADR2 => Inst_decodisa_dadrL_N3633, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_43_Q ); Inst_decodisa_dadrL_BU491 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3633 ); Inst_decodisa_dadrL_BU488 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3632 ); Inst_decodisa_dadrL_BU483 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3561, ADR2 => Inst_decodisa_dadrL_N3562, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_42_Q ); Inst_decodisa_dadrL_BU480 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3562 ); Inst_decodisa_dadrL_BU477 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3561 ); Inst_decodisa_dadrL_BU472 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3490, ADR2 => Inst_decodisa_dadrL_N3491, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_41_Q ); Inst_decodisa_dadrL_BU469 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3491 ); Inst_decodisa_dadrL_BU466 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3490 ); Inst_decodisa_dadrL_BU461 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3419, ADR2 => Inst_decodisa_dadrL_N3420, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_40_Q ); Inst_decodisa_dadrL_BU458 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3420 ); Inst_decodisa_dadrL_BU455 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3419 ); Inst_decodisa_dadrL_BU450 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3348, ADR2 => Inst_decodisa_dadrL_N3349, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_39_Q ); Inst_decodisa_dadrL_BU447 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3349 ); Inst_decodisa_dadrL_BU444 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3348 ); Inst_decodisa_dadrL_BU439 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3277, ADR2 => Inst_decodisa_dadrL_N3278, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_38_Q ); Inst_decodisa_dadrL_BU436 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3278 ); Inst_decodisa_dadrL_BU433 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3277 ); Inst_decodisa_dadrL_BU428 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3206, ADR2 => Inst_decodisa_dadrL_N3207, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_37_Q ); Inst_decodisa_dadrL_BU425 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3207 ); Inst_decodisa_dadrL_BU422 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3206 ); Inst_decodisa_dadrL_BU417 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3135, ADR2 => Inst_decodisa_dadrL_N3136, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_36_Q ); Inst_decodisa_dadrL_BU414 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3136 ); Inst_decodisa_dadrL_BU411 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3135 ); Inst_decodisa_dadrL_BU406 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N3064, ADR2 => Inst_decodisa_dadrL_N3065, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_35_Q ); Inst_decodisa_dadrL_BU403 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N3065 ); Inst_decodisa_dadrL_BU400 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N3064 ); Inst_decodisa_dadrL_BU395 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2993, ADR2 => Inst_decodisa_dadrL_N2994, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_34_Q ); Inst_decodisa_dadrL_BU392 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2994 ); Inst_decodisa_dadrL_BU389 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2993 ); Inst_decodisa_dadrL_BU384 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2922, ADR2 => Inst_decodisa_dadrL_N2923, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_33_Q ); Inst_decodisa_dadrL_BU381 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2923 ); Inst_decodisa_dadrL_BU378 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2922 ); Inst_decodisa_dadrL_BU373 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2851, ADR2 => Inst_decodisa_dadrL_N2852, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_32_Q ); Inst_decodisa_dadrL_BU370 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2852 ); Inst_decodisa_dadrL_BU367 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2851 ); Inst_decodisa_dadrL_BU362 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2780, ADR2 => Inst_decodisa_dadrL_N2781, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_31_Q ); Inst_decodisa_dadrL_BU359 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2781 ); Inst_decodisa_dadrL_BU356 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2780 ); Inst_decodisa_dadrL_BU351 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2709, ADR2 => Inst_decodisa_dadrL_N2710, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_30_Q ); Inst_decodisa_dadrL_BU348 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2710 ); Inst_decodisa_dadrL_BU345 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2709 ); Inst_decodisa_dadrL_BU340 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2638, ADR2 => Inst_decodisa_dadrL_N2639, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_29_Q ); Inst_decodisa_dadrL_BU337 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2639 ); Inst_decodisa_dadrL_BU334 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2638 ); Inst_decodisa_dadrL_BU329 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2567, ADR2 => Inst_decodisa_dadrL_N2568, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_28_Q ); Inst_decodisa_dadrL_BU326 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2568 ); Inst_decodisa_dadrL_BU323 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2567 ); Inst_decodisa_dadrL_BU318 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2496, ADR2 => Inst_decodisa_dadrL_N2497, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_27_Q ); Inst_decodisa_dadrL_BU315 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2497 ); Inst_decodisa_dadrL_BU312 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2496 ); Inst_decodisa_dadrL_BU307 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2425, ADR2 => Inst_decodisa_dadrL_N2426, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_26_Q ); Inst_decodisa_dadrL_BU304 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2426 ); Inst_decodisa_dadrL_BU301 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2425 ); Inst_decodisa_dadrL_BU296 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2354, ADR2 => Inst_decodisa_dadrL_N2355, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_25_Q ); Inst_decodisa_dadrL_BU293 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2355 ); Inst_decodisa_dadrL_BU290 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2354 ); Inst_decodisa_dadrL_BU285 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2283, ADR2 => Inst_decodisa_dadrL_N2284, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_24_Q ); Inst_decodisa_dadrL_BU282 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2284 ); Inst_decodisa_dadrL_BU279 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2283 ); Inst_decodisa_dadrL_BU274 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2212, ADR2 => Inst_decodisa_dadrL_N2213, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_23_Q ); Inst_decodisa_dadrL_BU271 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2213 ); Inst_decodisa_dadrL_BU268 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2212 ); Inst_decodisa_dadrL_BU263 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2141, ADR2 => Inst_decodisa_dadrL_N2142, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_22_Q ); Inst_decodisa_dadrL_BU260 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2142 ); Inst_decodisa_dadrL_BU257 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2141 ); Inst_decodisa_dadrL_BU252 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N2070, ADR2 => Inst_decodisa_dadrL_N2071, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_21_Q ); Inst_decodisa_dadrL_BU249 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2071 ); Inst_decodisa_dadrL_BU246 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N2070 ); Inst_decodisa_dadrL_BU241 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1999, ADR2 => Inst_decodisa_dadrL_N2000, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_20_Q ); Inst_decodisa_dadrL_BU238 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N2000 ); Inst_decodisa_dadrL_BU235 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1999 ); Inst_decodisa_dadrL_BU230 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1928, ADR2 => Inst_decodisa_dadrL_N1929, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_19_Q ); Inst_decodisa_dadrL_BU227 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1929 ); Inst_decodisa_dadrL_BU224 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1928 ); Inst_decodisa_dadrL_BU219 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1857, ADR2 => Inst_decodisa_dadrL_N1858, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_18_Q ); Inst_decodisa_dadrL_BU216 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1858 ); Inst_decodisa_dadrL_BU213 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1857 ); Inst_decodisa_dadrL_BU208 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1786, ADR2 => Inst_decodisa_dadrL_N1787, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_17_Q ); Inst_decodisa_dadrL_BU205 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1787 ); Inst_decodisa_dadrL_BU202 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1786 ); Inst_decodisa_dadrL_BU197 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1715, ADR2 => Inst_decodisa_dadrL_N1716, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_16_Q ); Inst_decodisa_dadrL_BU194 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1716 ); Inst_decodisa_dadrL_BU191 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1715 ); Inst_decodisa_dadrL_BU186 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1644, ADR2 => Inst_decodisa_dadrL_N1645, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_15_Q ); Inst_decodisa_dadrL_BU183 : X_LUT4 generic map( INIT => X"8000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1645 ); Inst_decodisa_dadrL_BU180 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1644 ); Inst_decodisa_dadrL_BU175 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1573, ADR2 => Inst_decodisa_dadrL_N1574, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_14_Q ); Inst_decodisa_dadrL_BU172 : X_LUT4 generic map( INIT => X"0080" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1574 ); Inst_decodisa_dadrL_BU169 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1573 ); Inst_decodisa_dadrL_BU164 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1502, ADR2 => Inst_decodisa_dadrL_N1503, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_13_Q ); Inst_decodisa_dadrL_BU161 : X_LUT4 generic map( INIT => X"0800" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1503 ); Inst_decodisa_dadrL_BU158 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1502 ); Inst_decodisa_dadrL_BU153 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1431, ADR2 => Inst_decodisa_dadrL_N1432, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_12_Q ); Inst_decodisa_dadrL_BU150 : X_LUT4 generic map( INIT => X"0008" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1432 ); Inst_decodisa_dadrL_BU147 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1431 ); Inst_decodisa_dadrL_BU142 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1360, ADR2 => Inst_decodisa_dadrL_N1361, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_11_Q ); Inst_decodisa_dadrL_BU139 : X_LUT4 generic map( INIT => X"2000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1361 ); Inst_decodisa_dadrL_BU136 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1360 ); Inst_decodisa_dadrL_BU131 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1289, ADR2 => Inst_decodisa_dadrL_N1290, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_10_Q ); Inst_decodisa_dadrL_BU128 : X_LUT4 generic map( INIT => X"0020" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1290 ); Inst_decodisa_dadrL_BU125 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1289 ); Inst_decodisa_dadrL_BU120 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1218, ADR2 => Inst_decodisa_dadrL_N1219, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_9_Q ); Inst_decodisa_dadrL_BU117 : X_LUT4 generic map( INIT => X"0200" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1219 ); Inst_decodisa_dadrL_BU114 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1218 ); Inst_decodisa_dadrL_BU109 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1147, ADR2 => Inst_decodisa_dadrL_N1148, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_8_Q ); Inst_decodisa_dadrL_BU106 : X_LUT4 generic map( INIT => X"0002" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1148 ); Inst_decodisa_dadrL_BU103 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1147 ); Inst_decodisa_dadrL_BU98 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1076, ADR2 => Inst_decodisa_dadrL_N1077, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_7_Q ); Inst_decodisa_dadrL_BU95 : X_LUT4 generic map( INIT => X"4000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1077 ); Inst_decodisa_dadrL_BU92 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1076 ); Inst_decodisa_dadrL_BU87 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N1005, ADR2 => Inst_decodisa_dadrL_N1006, ADR3 => Inst_decodisa_dadrL_N0, O => cs(6) ); Inst_decodisa_dadrL_BU84 : X_LUT4 generic map( INIT => X"0040" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N1006 ); Inst_decodisa_dadrL_BU81 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N1005 ); Inst_decodisa_dadrL_BU76 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N934, ADR2 => Inst_decodisa_dadrL_N935, ADR3 => Inst_decodisa_dadrL_N0, O => cs(5) ); Inst_decodisa_dadrL_BU73 : X_LUT4 generic map( INIT => X"0400" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N935 ); Inst_decodisa_dadrL_BU70 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N934 ); Inst_decodisa_dadrL_BU65 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N863, ADR2 => Inst_decodisa_dadrL_N864, ADR3 => Inst_decodisa_dadrL_N0, O => cs(4) ); Inst_decodisa_dadrL_BU62 : X_LUT4 generic map( INIT => X"0004" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N864 ); Inst_decodisa_dadrL_BU59 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N863 ); Inst_decodisa_dadrL_BU54 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N792, ADR2 => Inst_decodisa_dadrL_N793, ADR3 => Inst_decodisa_dadrL_N0, O => cs(3) ); Inst_decodisa_dadrL_BU51 : X_LUT4 generic map( INIT => X"1000" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N793 ); Inst_decodisa_dadrL_BU48 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N792 ); Inst_decodisa_dadrL_BU43 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N721, ADR2 => Inst_decodisa_dadrL_N722, ADR3 => Inst_decodisa_dadrL_N0, O => cs(2) ); Inst_decodisa_dadrL_BU40 : X_LUT4 generic map( INIT => X"0010" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N722 ); Inst_decodisa_dadrL_BU37 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N721 ); Inst_decodisa_dadrL_BU32 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N650, ADR2 => Inst_decodisa_dadrL_N651, ADR3 => Inst_decodisa_dadrL_N0, O => cs(1) ); Inst_decodisa_dadrL_BU29 : X_LUT4 generic map( INIT => X"0100" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N651 ); Inst_decodisa_dadrL_BU26 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N650 ); Inst_decodisa_dadrL_BU21 : X_LUT4 generic map( INIT => X"8080" ) port map ( ADR0 => Inst_decodisa_reg_select, ADR1 => Inst_decodisa_dadrL_N579, ADR2 => Inst_decodisa_dadrL_N580, ADR3 => Inst_decodisa_dadrL_N0, O => Inst_decodisa_dadrL_O_0_Q ); Inst_decodisa_dadrL_BU18 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_3_IBUF, ADR1 => bus_adr_2_IBUF, ADR2 => bus_adr_1_IBUF, ADR3 => bus_adr_0_IBUF, O => Inst_decodisa_dadrL_N580 ); Inst_decodisa_dadrL_BU15 : X_LUT4 generic map( INIT => X"0001" ) port map ( ADR0 => bus_adr_7_IBUF, ADR1 => bus_adr_6_IBUF, ADR2 => bus_adr_5_IBUF, ADR3 => bus_adr_4_IBUF, O => Inst_decodisa_dadrL_N579 ); Inst_decodisa_dadrL_GND : X_ZERO port map ( O => Inst_decodisa_dadrL_N0 ); Inst_decodisa_dadrL_VCC : X_ONE port map ( O => NLW_Inst_decodisa_dadrL_VCC_O_UNCONNECTED ); clk_ref_BUFGP_BUFG : X_CKBUF port map ( I => clk_ref_BUFGP_IBUFG, O => clk_ref_BUFGP ); clk_ref_BUFGP_IBUFG_115 : X_CKBUF port map ( I => clk_ref, O => clk_ref_BUFGP_IBUFG ); clk_speed_BUFGP_BUFG : X_CKBUF port map ( I => clk_speed_BUFGP_IBUFG, O => clk_speed_BUFGP ); clk_speed_BUFGP_IBUFG_116 : X_CKBUF port map ( I => clk_speed, O => clk_speed_BUFGP_IBUFG ); rst_BUFGP_BUFG : X_CKBUF port map ( I => rst_BUFGP_IBUFG, O => rst_BUFGP ); rst_BUFGP_IBUFG_117 : X_CKBUF port map ( I => rst, O => rst_BUFGP_IBUFG ); Inst_txserie1_RFLAG_REG_2_GSR_OR_118 : X_OR2 port map ( I0 => Inst_txserie1_RFLAG_REG_2_n0000, I1 => GSR, O => Inst_txserie1_RFLAG_REG_2_GSR_OR ); Inst_txserie1_RFLAG_REG_1_GSR_OR_119 : X_OR2 port map ( I0 => Inst_txserie1_RFLAG_REG_1_n0000, I1 => GSR, O => Inst_txserie1_RFLAG_REG_1_GSR_OR ); Inst_rxserie1_RFLAG_REG_0_GSR_OR_120 : X_OR2 port map ( I0 => Inst_rxserie1_RFLAG_REG_0_n0000, I1 => GSR, O => Inst_rxserie1_RFLAG_REG_0_GSR_OR ); Inst_rxserie1_RCONF_REG_0_GSR_OR_121 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_0_GSR_OR ); Inst_rxserie1_FIFO1_wr_en_GSR_OR_122 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_FIFO1_wr_en_GSR_OR ); Inst_rxserie1_FIFO1_rd_en_GSR_OR_123 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_FIFO1_rd_en_GSR_OR ); Inst_rxserie1_RFLAG_REG_6_GSR_OR_124 : X_OR2 port map ( I0 => Inst_rxserie1_RFLAG_REG_6_n0000, I1 => GSR, O => Inst_rxserie1_RFLAG_REG_6_GSR_OR ); Inst_rxserie1_RFLAG_REG_5_GSR_OR_125 : X_OR2 port map ( I0 => Inst_rxserie1_RFLAG_REG_5_n0000, I1 => GSR, O => Inst_rxserie1_RFLAG_REG_5_GSR_OR ); Inst_rxserie1_RFLAG_REG_4_GSR_OR_126 : X_OR2 port map ( I0 => Inst_rxserie1_RFLAG_REG_4_n0000, I1 => GSR, O => Inst_rxserie1_RFLAG_REG_4_GSR_OR ); Inst_rxserie1_RFLAG_REG_3_GSR_OR_127 : X_OR2 port map ( I0 => irqrxRX_OBUF, I1 => GSR, O => Inst_rxserie1_RFLAG_REG_3_GSR_OR ); Inst_rxserie1_RFLAG_REG_2_GSR_OR_128 : X_OR2 port map ( I0 => Inst_rxserie1_RFLAG_REG_2_n0000, I1 => GSR, O => Inst_rxserie1_RFLAG_REG_2_GSR_OR ); Inst_rxserie1_RFLAG_REG_1_GSR_OR_129 : X_OR2 port map ( I0 => Inst_rxserie1_RFLAG_REG_1_n0000, I1 => GSR, O => Inst_rxserie1_RFLAG_REG_1_GSR_OR ); Inst_txserie1_RFLAG_REG_3_GSR_OR_130 : X_OR2 port map ( I0 => Inst_txserie1_RFLAG_REG_3_n0000, I1 => GSR, O => Inst_txserie1_RFLAG_REG_3_GSR_OR ); Inst_txserie1_RCONF_REG_2_GSR_OR_131 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_RCONF_REG_2_GSR_OR ); Inst_txserie1_RCONF_REG_7_GSR_OR_132 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_RCONF_REG_7_GSR_OR ); Inst_txserie1_RCONF_REG_3_GSR_OR_133 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_RCONF_REG_3_GSR_OR ); Inst_txserie1_RCONF_REG_5_GSR_OR_134 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_RCONF_REG_5_GSR_OR ); Inst_txserie1_RCONF_REG_4_GSR_OR_135 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_RCONF_REG_4_GSR_OR ); Inst_rxserie1_RCONF_REG_7_GSR_OR_136 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_7_GSR_OR ); Inst_txserie1_RCONF_REG_6_GSR_OR_137 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_RCONF_REG_6_GSR_OR ); Inst_rxserie1_RCONF_REG_6_GSR_OR_138 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_6_GSR_OR ); Inst_rxserie1_RCONF_REG_5_GSR_OR_139 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_5_GSR_OR ); Inst_rxserie1_RCONF_REG_4_GSR_OR_140 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_4_GSR_OR ); Inst_rxserie1_RCONF_REG_3_GSR_OR_141 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_3_GSR_OR ); Inst_rxserie1_RCONF_REG_2_GSR_OR_142 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_2_GSR_OR ); Inst_rxserie1_RCONF_REG_1_GSR_OR_143 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_1_GSR_OR ); Inst_txserie1_RCONF_REG_1_GSR_OR_144 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_RCONF_REG_1_GSR_OR ); Inst_txserie1_RFLAG_REG_0_GSR_OR_145 : X_OR2 port map ( I0 => Inst_txserie1_RFLAG_REG_0_n0000, I1 => GSR, O => Inst_txserie1_RFLAG_REG_0_GSR_OR ); Inst_txserie1_RCONF_REG_0_GSR_OR_146 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_RCONF_REG_0_GSR_OR ); Inst_txserie1_TX1_CNT_1_GSR_OR_147 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_CNT_1_GSR_OR ); Inst_txserie1_FIFO1_wr_en_GSR_OR_148 : X_OR2 port map ( I0 => Inst_txserie1_fifopurge, I1 => GSR, O => Inst_txserie1_FIFO1_wr_en_GSR_OR ); Inst_txserie1_FIFO1_rd_en_GSR_OR_149 : X_OR2 port map ( I0 => Inst_txserie1_fifopurge, I1 => GSR, O => Inst_txserie1_FIFO1_rd_en_GSR_OR ); Inst_rxserie1_RC1_RHR_6_GSR_OR_150 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_6_GSR_OR ); Inst_rxserie1_RC1_RHR_3_GSR_OR_151 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_3_GSR_OR ); Inst_rxserie1_RC1_RHR_5_GSR_OR_152 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_5_GSR_OR ); Inst_rxserie1_RC1_RHR_4_GSR_OR_153 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_4_GSR_OR ); Inst_rxserie1_RC1_RHR_0_GSR_OR_154 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_0_GSR_OR ); Inst_rxserie1_RC1_RHR_2_GSR_OR_155 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_2_GSR_OR ); Inst_rxserie1_RC1_RHR_1_GSR_OR_156 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_1_GSR_OR ); Inst_rxserie1_RC1_READ2_GSR_OR_157 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_READ2_GSR_OR ); Inst_rxserie1_RC1_IDLE1_GSR_OR_158 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_IDLE1_GSR_OR ); Inst_rxserie1_RC1_READ1_GSR_OR_159 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_READ1_GSR_OR ); Inst_rxserie1_RC1_IDLE_GSR_OR_160 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_IDLE_GSR_OR ); Inst_rxserie1_RC1_HUNT_GSR_OR_161 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_HUNT_GSR_OR ); Inst_rxserie1_RC1_RXCNT_1_GSR_OR_162 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXCNT_1_GSR_OR ); Inst_rxserie1_RC1_RX1_GSR_OR_163 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RX1_GSR_OR ); Inst_rxserie1_RC1_RXCLK_GSR_OR_164 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXCLK_GSR_OR ); Inst_rxserie1_RC1_RXPARITY_GSR_OR_165 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXPARITY_GSR_OR ); Inst_rxserie1_RC1_PARITYGEN_GSR_OR_166 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_PARITYGEN_GSR_OR ); Inst_rxserie1_RC1_RXSTOP_GSR_OR_167 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXSTOP_GSR_OR ); Inst_rxserie1_RC1_RSR_7_GSR_OR_168 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_7_GSR_OR ); Inst_rxserie1_RC1_RSR_6_GSR_OR_169 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_6_GSR_OR ); Inst_rxserie1_RC1_RSR_5_GSR_OR_170 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_5_GSR_OR ); Inst_rxserie1_RC1_RSR_4_GSR_OR_171 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_4_GSR_OR ); Inst_rxserie1_RC1_RSR_3_GSR_OR_172 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_3_GSR_OR ); Inst_rxserie1_RC1_RSR_2_GSR_OR_173 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_2_GSR_OR ); Inst_rxserie1_RC1_RSR_1_GSR_OR_174 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_1_GSR_OR ); Inst_rxserie1_RC1_RSR_0_GSR_OR_175 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_0_GSR_OR ); Inst_rxserie1_RC1_RHR_7_GSR_OR_176 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_7_GSR_OR ); Inst_rxserie1_RC1_RXDATARDY_GSR_OR_177 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXDATARDY_GSR_OR ); Inst_rxserie1_RC1_OVERRUN_GSR_OR_178 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_OVERRUN_GSR_OR ); Inst_rxserie1_RC1_PARITY_ERR_GSR_OR_179 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_PARITY_ERR_GSR_OR ); Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR_180 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR ); Inst_rxserie1_RC1_RXCNT_3_GSR_OR_181 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXCNT_3_GSR_OR ); Inst_rxserie1_RC1_RXCNT_2_GSR_OR_182 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXCNT_2_GSR_OR ); Inst_rxserie1_RC1_RXCNT_0_GSR_OR_183 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXCNT_0_GSR_OR ); Inst_txserie1_CLOCK1_ckout_GSR_OR_184 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_CLOCK1_ckout_GSR_OR ); Inst_txserie1_CLOCK1_compteur_9_GSR_OR_185 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_CLOCK1_compteur_9_GSR_OR ); Inst_txserie1_CLOCK1_compteur_8_GSR_OR_186 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_CLOCK1_compteur_8_GSR_OR ); Inst_txserie1_CLOCK1_compteur_0_GSR_OR_187 : X_OR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_0_0_n0000, I1 => GSR, O => Inst_txserie1_CLOCK1_compteur_0_GSR_OR ); Inst_txserie1_CLOCK1_compteur_1_GSR_OR_188 : X_OR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_0_1_n0000, I1 => GSR, O => Inst_txserie1_CLOCK1_compteur_1_GSR_OR ); Inst_txserie1_CLOCK1_compteur_2_GSR_OR_189 : X_OR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_0_2_n0000, I1 => GSR, O => Inst_txserie1_CLOCK1_compteur_2_GSR_OR ); Inst_txserie1_CLOCK1_compteur_3_GSR_OR_190 : X_OR2 port map ( I0 => Inst_txserie1_CLOCK1_compteur_0_3_n0000, I1 => GSR, O => Inst_txserie1_CLOCK1_compteur_3_GSR_OR ); Inst_txserie1_CLOCK1_compteur_4_GSR_OR_191 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_CLOCK1_compteur_4_GSR_OR ); Inst_txserie1_CLOCK1_compteur_5_GSR_OR_192 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_CLOCK1_compteur_5_GSR_OR ); Inst_txserie1_CLOCK1_compteur_6_GSR_OR_193 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_CLOCK1_compteur_6_GSR_OR ); Inst_txserie1_CLOCK1_compteur_7_GSR_OR_194 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_CLOCK1_compteur_7_GSR_OR ); Inst_rxserie1_CLOCK1_ckout_GSR_OR_195 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_ckout_GSR_OR ); Inst_rxserie1_CLOCK1_compteur_9_GSR_OR_196 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_9_GSR_OR ); Inst_rxserie1_CLOCK1_compteur_8_GSR_OR_197 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_8_GSR_OR ); Inst_rxserie1_CLOCK1_compteur_0_GSR_OR_198 : X_OR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_0_0_n0000, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_0_GSR_OR ); Inst_rxserie1_CLOCK1_compteur_1_GSR_OR_199 : X_OR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_0_1_n0000, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_1_GSR_OR ); Inst_rxserie1_CLOCK1_compteur_2_GSR_OR_200 : X_OR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_0_2_n0000, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_2_GSR_OR ); Inst_rxserie1_CLOCK1_compteur_3_GSR_OR_201 : X_OR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_0_3_n0000, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_3_GSR_OR ); Inst_rxserie1_CLOCK1_compteur_4_GSR_OR_202 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_4_GSR_OR ); Inst_rxserie1_CLOCK1_compteur_5_GSR_OR_203 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_5_GSR_OR ); Inst_rxserie1_CLOCK1_compteur_6_GSR_OR_204 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_6_GSR_OR ); Inst_rxserie1_CLOCK1_compteur_7_GSR_OR_205 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_7_GSR_OR ); Inst_txserie1_TX1_THR_6_GSR_OR_206 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_THR_6_GSR_OR ); Inst_txserie1_TX1_THR_5_GSR_OR_207 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_THR_5_GSR_OR ); Inst_txserie1_TX1_THR_3_GSR_OR_208 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_THR_3_GSR_OR ); Inst_txserie1_TX1_TSR_0_GSR_OR_209 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TSR_0_GSR_OR ); Inst_txserie1_TX1_TSR_1_GSR_OR_210 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TSR_1_GSR_OR ); Inst_txserie1_TX1_THR_4_GSR_OR_211 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_THR_4_GSR_OR ); Inst_txserie1_TX1_TXDONE1_GSR_OR_212 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TXDONE1_GSR_OR ); Inst_txserie1_TX1_WRITE1_GSR_OR_213 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_WRITE1_GSR_OR ); Inst_txserie1_TX1_WRITE2_GSR_OR_214 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_WRITE2_GSR_OR ); Inst_txserie1_TX1_TXDATARDY_GSR_OR_215 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TXDATARDY_GSR_OR ); Inst_txserie1_TX1_THR_7_GSR_OR_216 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_THR_7_GSR_OR ); Inst_txserie1_TX1_TXCLK_GSR_OR_217 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TXCLK_GSR_OR ); Inst_txserie1_TX1_TAG2_GSR_OR_218 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TAG2_GSR_OR ); Inst_txserie1_TX1_TAG1_GSR_OR_219 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TAG1_GSR_OR ); Inst_txserie1_TX1_TXPARITY_GSR_OR_220 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TXPARITY_GSR_OR ); Inst_txserie1_TX1_TX_GSR_OR_221 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TX_GSR_OR ); Inst_txserie1_TX1_TSR_7_GSR_OR_222 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TSR_7_GSR_OR ); Inst_txserie1_TX1_TSR_6_GSR_OR_223 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TSR_6_GSR_OR ); Inst_txserie1_TX1_TSR_5_GSR_OR_224 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TSR_5_GSR_OR ); Inst_txserie1_TX1_TSR_4_GSR_OR_225 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TSR_4_GSR_OR ); Inst_txserie1_TX1_TSR_3_GSR_OR_226 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TSR_3_GSR_OR ); Inst_txserie1_TX1_TSR_2_GSR_OR_227 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_TSR_2_GSR_OR ); Inst_txserie1_TX1_THR_0_GSR_OR_228 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_THR_0_GSR_OR ); Inst_txserie1_TX1_THR_1_GSR_OR_229 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_THR_1_GSR_OR ); Inst_txserie1_TX1_THR_2_GSR_OR_230 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_THR_2_GSR_OR ); Inst_txserie1_TX1_CNT_2_GSR_OR_231 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_CNT_2_GSR_OR ); Inst_txserie1_TX1_CNT_0_GSR_OR_232 : X_OR2 port map ( I0 => rst_BUFGP, I1 => GSR, O => Inst_txserie1_TX1_CNT_0_GSR_OR ); bus_data_0_IOBUF_OBUFT_GTS_AND_233 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_0_IOBUF_OBUFT_GTS_AND ); bus_data_1_IOBUF_OBUFT_GTS_AND_234 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_1_IOBUF_OBUFT_GTS_AND ); bus_data_2_IOBUF_OBUFT_GTS_AND_235 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_2_IOBUF_OBUFT_GTS_AND ); bus_data_3_IOBUF_OBUFT_GTS_AND_236 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_3_IOBUF_OBUFT_GTS_AND ); bus_data_4_IOBUF_OBUFT_GTS_AND_237 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_4_IOBUF_OBUFT_GTS_AND ); bus_data_5_IOBUF_OBUFT_GTS_AND_238 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_5_IOBUF_OBUFT_GTS_AND ); bus_data_6_IOBUF_OBUFT_GTS_AND_239 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_6_IOBUF_OBUFT_GTS_AND ); bus_data_7_IOBUF_OBUFT_GTS_AND_240 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_7_IOBUF_OBUFT_GTS_AND ); txout1_OBUF_GTS_TRI_241 : X_TRI port map ( I => txout1_OBUF_GTS_TRI, CTL => NlwInverterSignal_txout1_OBUF_GTS_TRI_CTL, O => txout1 ); irqtx_OBUF_GTS_TRI_242 : X_TRI port map ( I => irqtx_OBUF_GTS_TRI, CTL => NlwInverterSignal_irqtx_OBUF_GTS_TRI_CTL, O => irqtx ); irqrxFIFO_OBUF_GTS_TRI_243 : X_TRI port map ( I => irqrxFIFO_OBUF_GTS_TRI, CTL => NlwInverterSignal_irqrxFIFO_OBUF_GTS_TRI_CTL, O => irqrxFIFO ); irqrxRX_OBUF_GTS_TRI_244 : X_TRI port map ( I => irqrxRX_OBUF_GTS_TRI, CTL => NlwInverterSignal_irqrxRX_OBUF_GTS_TRI_CTL, O => irqrxRX ); irqrxERR_OBUF_GTS_TRI_245 : X_TRI port map ( I => irqrxERR_OBUF_GTS_TRI, CTL => NlwInverterSignal_irqrxERR_OBUF_GTS_TRI_CTL, O => irqrxERR ); NlwBlock_fpga_GND : X_ZERO port map ( O => GND ); NlwInverterBlock_Inst_rxserie1_I7_0_T : X_INV port map ( I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_0_T ); NlwBlock_fpga_VCC : X_ONE port map ( O => VCC ); NlwInverterBlock_Inst_rxserie1_I7_7_T : X_INV port map ( I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_7_T ); NlwInverterBlock_Inst_rxserie1_I7_6_T : X_INV port map ( I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_6_T ); NlwInverterBlock_Inst_rxserie1_I7_5_T : X_INV port map ( I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_5_T ); NlwInverterBlock_Inst_rxserie1_I7_4_T : X_INV port map ( I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_4_T ); NlwInverterBlock_Inst_rxserie1_I7_3_T : X_INV port map ( I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_3_T ); NlwInverterBlock_Inst_rxserie1_I7_2_T : X_INV port map ( I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_2_T ); NlwInverterBlock_Inst_rxserie1_I7_1_T : X_INV port map ( I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_1_T ); NlwInverterBlock_Inst_rxserie1_FIFO1_wr_en_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_rxserie1_FIFO1_wr_en_C ); NlwInverterBlock_Inst_rxserie1_FIFO1_rd_en_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_rxserie1_FIFO1_rd_en_C ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_1_T : X_INV port map ( I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_1_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_2_T : X_INV port map ( I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_2_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_0_T : X_INV port map ( I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_0_T ); NlwInverterBlock_Inst_txserie1_RCONF_I1_1_T : X_INV port map ( I => Inst_txserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RCONF_I1_1_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_7_T : X_INV port map ( I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_7_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_6_T : X_INV port map ( I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_6_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_5_T : X_INV port map ( I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_5_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_4_T : X_INV port map ( I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_4_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_3_T : X_INV port map ( I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_3_T ); NlwInverterBlock_Inst_txserie1_RCONF_I1_2_T : X_INV port map ( I => Inst_txserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RCONF_I1_2_T ); NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd1_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C ); NlwInverterBlock_Inst_txserie1_RCONF_I1_0_T : X_INV port map ( I => Inst_txserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RCONF_I1_0_T ); NlwInverterBlock_Inst_txserie1_RCONF_I1_7_T : X_INV port map ( I => Inst_txserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RCONF_I1_7_T ); NlwInverterBlock_Inst_txserie1_RCONF_I1_6_T : X_INV port map ( I => Inst_txserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RCONF_I1_6_T ); NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd2_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C ); NlwInverterBlock_Inst_txserie1_FIFO1_state_write_FFd2_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd2_C ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_1_T : X_INV port map ( I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_1_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_2_T : X_INV port map ( I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_2_T ); NlwInverterBlock_Inst_txserie1_RCONF_I1_5_T : X_INV port map ( I => Inst_txserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RCONF_I1_5_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_0_T : X_INV port map ( I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_0_T ); NlwInverterBlock_Inst_txserie1_RCONF_I1_4_T : X_INV port map ( I => Inst_txserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RCONF_I1_4_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_7_T : X_INV port map ( I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_7_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_6_T : X_INV port map ( I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_6_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_5_T : X_INV port map ( I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_5_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_4_T : X_INV port map ( I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_4_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_3_T : X_INV port map ( I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_3_T ); NlwInverterBlock_Inst_txserie1_RCONF_I1_3_T : X_INV port map ( I => Inst_txserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RCONF_I1_3_T ); NlwInverterBlock_Inst_rxserie1_FIFO1_state_read_FFd3_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd3_C ); NlwInverterBlock_Inst_rxserie1_FIFO1_state_read_FFd2_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd2_C ); NlwInverterBlock_Inst_rxserie1_FIFO1_state_read_FFd1_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd1_C ); NlwInverterBlock_Inst_txserie1_FIFO1_state_write_FFd1_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd1_C ); NlwInverterBlock_Inst_txserie1_txload_G : X_INV port map ( I => rst_BUFGP, O => NlwInverterSignal_Inst_txserie1_txload_G ); NlwInverterBlock_Inst_rxserie1_FIFO1_state_read_FFd4_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd4_C ); NlwInverterBlock_Inst_txserie1_FIFO1_wr_en_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_txserie1_FIFO1_wr_en_C ); NlwInverterBlock_Inst_txserie1_FIFO1_dready_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_txserie1_FIFO1_dready_C ); NlwInverterBlock_Inst_txserie1_FIFO1_state_write_FFd3_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd3_C ); NlwInverterBlock_Inst_txserie1_FIFO1_rd_en_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_txserie1_FIFO1_rd_en_C ); NlwInverterBlock_Inst_txserie1_RFLAG_I1_1_T : X_INV port map ( I => Inst_txserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_1_T ); NlwInverterBlock_Inst_txserie1_RFLAG_I1_2_T : X_INV port map ( I => Inst_txserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_2_T ); NlwInverterBlock_Inst_txserie1_FIFO1_state_read_FFd3_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd3_C ); NlwInverterBlock_Inst_txserie1_RFLAG_I1_0_T : X_INV port map ( I => Inst_txserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_0_T ); NlwInverterBlock_Inst_txserie1_RFLAG_I1_7_T : X_INV port map ( I => Inst_txserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_7_T ); NlwInverterBlock_Inst_txserie1_RFLAG_I1_6_T : X_INV port map ( I => Inst_txserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_6_T ); NlwInverterBlock_Inst_txserie1_RFLAG_I1_5_T : X_INV port map ( I => Inst_txserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_5_T ); NlwInverterBlock_Inst_txserie1_RFLAG_I1_4_T : X_INV port map ( I => Inst_txserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_4_T ); NlwInverterBlock_Inst_txserie1_RFLAG_I1_3_T : X_INV port map ( I => Inst_txserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_3_T ); NlwInverterBlock_Inst_txserie1_FIFO1_state_read_FFd1_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd1_C ); NlwInverterBlock_Inst_txserie1_FIFO1_state_read_FFd4_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd4_C ); NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd3_C : X_INV port map ( I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C ); NlwInverterBlock_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( I => N6828, O => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1 : X_INV port map ( I => GTS, O => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1 ); NlwInverterBlock_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( I => N6828, O => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_1_IOBUF_OBUFT_GTS_AND_IN1 : X_INV port map ( I => GTS, O => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN1 ); NlwInverterBlock_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( I => N6828, O => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_2_IOBUF_OBUFT_GTS_AND_IN1 : X_INV port map ( I => GTS, O => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN1 ); NlwInverterBlock_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( I => N6828, O => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_3_IOBUF_OBUFT_GTS_AND_IN1 : X_INV port map ( I => GTS, O => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN1 ); NlwInverterBlock_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( I => N6828, O => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_4_IOBUF_OBUFT_GTS_AND_IN1 : X_INV port map ( I => GTS, O => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN1 ); NlwInverterBlock_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( I => N6828, O => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_5_IOBUF_OBUFT_GTS_AND_IN1 : X_INV port map ( I => GTS, O => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN1 ); NlwInverterBlock_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( I => N6828, O => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1 : X_INV port map ( I => GTS, O => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1 ); NlwInverterBlock_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( I => N6828, O => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1 : X_INV port map ( I => GTS, O => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1 ); NlwInverterBlock_txout1_OBUF_GTS_TRI_CTL : X_INV port map ( I => GTS, O => NlwInverterSignal_txout1_OBUF_GTS_TRI_CTL ); NlwInverterBlock_irqtx_OBUF_GTS_TRI_CTL : X_INV port map ( I => GTS, O => NlwInverterSignal_irqtx_OBUF_GTS_TRI_CTL ); NlwInverterBlock_irqrxFIFO_OBUF_GTS_TRI_CTL : X_INV port map ( I => GTS, O => NlwInverterSignal_irqrxFIFO_OBUF_GTS_TRI_CTL ); NlwInverterBlock_irqrxRX_OBUF_GTS_TRI_CTL : X_INV port map ( I => GTS, O => NlwInverterSignal_irqrxRX_OBUF_GTS_TRI_CTL ); NlwInverterBlock_irqrxERR_OBUF_GTS_TRI_CTL : X_INV port map ( I => GTS, O => NlwInverterSignal_irqrxERR_OBUF_GTS_TRI_CTL ); NlwBlockROC : X_ROC generic map (ROC_WIDTH => 100 ns) port map (O => GSR); NlwBlockTOC : X_TOC port map (O => GTS); end Structure;