-- VHDL Test Bench Created from source file fpga.vhd -- 17:38:53 03/30/2004 -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_arith.all; USE ieee.numeric_std.ALL; use work.nono_const.all; use work.isa_const.all; ENTITY bch_fpga IS END bch_fpga; ARCHITECTURE behavior OF bch_fpga IS COMPONENT fpga PORT( rst : IN std_logic; clk_speed : IN std_logic; clk_ref : IN std_logic; AEN : IN std_logic; IOR : IN std_logic; IOW : IN std_logic; bus_adr : IN std_logic_vector(23 downto 0); rxin1 : IN std_logic; bus_data : INOUT std_logic_vector(7 downto 0); irq : OUT std_logic; irqrxFIFO : OUT std_logic; irqrxRX : OUT std_logic; irqrxERR : OUT std_logic; irqtx : OUT std_logic; txout1 : OUT std_logic ); END COMPONENT; SIGNAL rst : std_logic:='0'; SIGNAL clk_speed : std_logic:='0'; SIGNAL clk_ref : std_logic:='0'; SIGNAL AEN : std_logic:='1'; SIGNAL IOR : std_logic:='1'; SIGNAL IOW : std_logic:='1'; SIGNAL bus_adr : std_logic_vector(23 downto 0); SIGNAL bus_data : std_logic_vector(7 downto 0); SIGNAL irq : std_logic:='0'; SIGNAL irqrxFIFO,irqrxRX,irqrxERR,irqtx : std_logic:='0'; SIGNAL rxin1 : std_logic:='0'; SIGNAL txout1 : std_logic:='0'; signal data : integer; signal data_received : std_logic_vector(7 downto 0); BEGIN uut: fpga PORT MAP( rst => rst, clk_speed => clk_speed, clk_ref => clk_ref, AEN => AEN, IOR => IOR, IOW => IOW, bus_adr => bus_adr, bus_data => bus_data, irq => irq, irqrxFIFO => irqrxFIFO , irqrxRX => irqrxRX, irqrxERR => irqrxERR , irqtx => irqtx , rxin1 => rxin1, txout1 => txout1 ); -- master clock clk_speed <= (Not clk_speed) after (CK_PERIOD/2); -- Reset rst <= '1','0' after (100 ns); -- baudrate/(16*2) used to generate half clock cycle; clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz -- feeding back output from transmitter to the input of receiver rxin1 <= txout1; check:process -- procedure declaration -- declared in process due to assignment to read -- this procedure reads out data from the receiver -- timing can be modified to model any CPU read cycle PROCEDURE read_bus(address : in integer) IS variable adr : std_logic_vector(23 downto 0); BEGIN adr:=conv_std_logic_vector(address,24); bus_data<="ZZZZZZZZ"; AEN<='0'; WAIT FOR 20 ns; bus_adr<=adr; WAIT FOR 20 ns; IOR<='0'; WAIT FOR 150 ns; data_received <= bus_data; IOR<='1'; WAIT FOR 20 ns; AEN<='1'; WAIT FOR 20 ns; END read_bus; PROCEDURE write_bus(address : IN integer) IS variable adr : std_logic_vector(23 downto 0); variable dat : std_logic_vector(7 downto 0); BEGIN -- adr:=conv_std_logic_vector(address,24); -- dat:=conv_std_logic_vector(data,8); AEN<='0'; WAIT FOR 20 ns; bus_adr<=conv_std_logic_vector(address,24); bus_data <= conv_std_logic_vector(data,8); WAIT FOR 20 ns; IOW<='0'; WAIT FOR 100 ns; IOW<='1'; WAIT FOR 20 ns; bus_data <= "ZZZZZZZZ"; AEN<='1'; WAIT FOR 20 ns; END write_bus; -- RX -- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0) -- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 ) -- TX -- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) -- Flag : (x ! x ! x ! x ! Empty ! Full ! FLI1 ! FLI0 ) begin -- RX -- data : 257 -- config : 258 -- flag : 259 -- TX -- data : 260 -- config : 261 -- flag : 262 wait for 500 ns; -- configuration du RX (RX_config) data<=255; write_bus(258); read_bus(258); wait for 500 ns; -- configuration du TX data<=119; write_bus(261); read_bus(261); wait for 1 us; -- transmission par le TX data<=177; write_bus(260); wait for 100 ns; -- transmission par le TX data<=52; write_bus(260); wait for 100 ns; -- transmission par le TX data<=22; write_bus(260); wait for 100 ns; wait for 400 ns; end process; END behavior;