library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decodisa is port( adr_bus: in std_logic_vector(23 downto 0); AEN:in std_logic; IOR:in std_logic; IOW:in std_logic; cs: out std_logic_vector(255 downto 0); rw: out std_logic; clk: out std_logic ); constant adr_reseau:std_logic_vector:="0000000000000001"; constant W_reseau:integer:=16; constant W_sous_reseau:integer:=8; -- Attention : si changement sur ces valeurs,=> modifier le core !!! end decodisa; architecture rtl of decodisa is component decodadr port ( S: IN std_logic_VECTOR((W_sous_reseau-1) downto 0); O: OUT std_logic_VECTOR(255 downto 0); EN: IN std_logic); end component; component decodsig port( AEN:in std_logic; IOR:in std_logic; IOW:in std_logic; rw: out std_logic; clk: out std_logic); end component; signal reg_select : std_logic; begin dsig:decodsig port map( AEN=>AEN, IOR=>IOR, IOW=>IOW, rw=>rw, clk=>clk); dadrL:decodadr port map( S=>adr_bus((W_sous_reseau - 1) downto 0), O=>cs, EN=>reg_select); reg_select<='1' when (adr_bus((W_reseau - 1) downto W_sous_reseau)=adr_reseau) else '0'; end rtl;