-- Décodeur de bus ISA pour le fpga robot library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decodisa is generic( myISA_adress: integer :=1234; adr_bus_bit: integer :=10 ); port( ISA_clk: in std_logic; ISA_RW: in std_logic; -- 1=read 0=write ISA_adr_bus: in std_logic_vector(20 downto 0); clk: out std_logic; RW: out std_logic; adr_bus: out std_logic_vector(20 downto 0); ); end entity; -- architecture rtl of decodisa is signal myAdr: std_logic_vector(10 downto 0) := conv_std_logic_vector(integer(myISA_adress)); begin process(ISA_adr_bus) if(ISA_adr_bus=myAdr) then adr_bus<=ISA_adr_bus; else adr_bus<=(others <= '0'); end if; end process;