-- VHDL Test Bench Created from source file decodisa.vhd -- 02:25:56 03/17/2004 -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -- LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY decodisa_bch IS END decodisa_bch; ARCHITECTURE behavior OF decodisa_bch IS COMPONENT decodisa PORT( adr_bus : IN std_logic_vector(23 downto 0); AEN : IN std_logic; IOR : IN std_logic; IOW : IN std_logic; cs : OUT std_logic_vector(255 downto 0); rw : OUT std_logic; clk : OUT std_logic ); END COMPONENT; SIGNAL adr_bus : std_logic_vector(23 downto 0):=(others => '0'); SIGNAL AEN : std_logic:='0'; SIGNAL IORosc : std_logic:='0'; SIGNAL IOWosc : std_logic:='0'; SIGNAL IOR : std_logic:='0'; SIGNAL IOW : std_logic:='0'; SIGNAL cs : std_logic_vector(255 downto 0); SIGNAL rw : std_logic; SIGNAL clk : std_logic; BEGIN uut: decodisa PORT MAP( adr_bus => adr_bus, AEN => AEN, IOR => IOR, IOW => IOW, cs => cs, rw => rw, clk => clk ); adr_bus <= conv_std_logic_vector(unsigned(adr_bus) + 1 , 24) after 120 ns; aen<= not aen after 13000 ns; iorosc<= not iorosc after 7000 ns; iowosc<= not iowosc after 5000 ns; ior<=not(iorosc and not aen); iow<=not(iowosc and not aen); END;