-- bch_decodeur4.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre-André Galmes -- Test du decodeur4. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.nono_const.all; entity bch_decodeur4 is end bch_decodeur4; architecture sim1 of bch_decodeur4 is component decodeur4 generic ( -- adresses des différents registres du module. A_REG0 : T_ADDRESS; A_REG1 : T_ADDRESS; A_REG2 : T_ADDRESS; A_REG3 : T_ADDRESS -- si autre choses à déclarer... ); port ( -- TODO : utile la clock ? --clk : in std_logic; bus_address : in T_ADDRESS; enable0 : out std_logic; enable1 : out std_logic; enable2 : out std_logic; enable3 : out std_logic ); end component; -- définiton des signaux --signal clk : std_logic := '0'; signal bus_address : T_ADDRESS; signal enable0 : std_logic; signal enable1 : std_logic; signal enable2 : std_logic; signal enable3 : std_logic; begin U1 : decodeur4 generic map ( -- Définition des addresses. A_REG0 => A_IO1_REG_DATA, A_REG1 => A_IO1_REG_DIRECTION, A_REG2 => A_IO1_REG_INTERRUPT_MASK, A_REG3 => A_IO1_READ_OUTPUT ) port map ( bus_address => bus_address, enable0 => enable0, enable1 => enable1, enable2 => enable2, enable3 => enable3 ); --clk <= not clk after (CK_PERIOD/2); bus_address <= A_IO1_REG_DIRECTION, A_IO1_READ_OUTPUT after 3*CK_PERIOD, A_IO1_REG_INTERRUPT_MASK after 5*CK_PERIOD, A_IO1_REG_DATA after 7*CK_PERIOD; end sim1; configuration cf1_bch_decodeur4 of bch_decodeur4 is for sim1 for all : decodeur4 use entity work.decodeur4(RTL); end for; end for; end cf1_bch_decodeur4;