-- modele.vhd -- Eurobot 2004 : APB Team -- Auteur : Pierre-André Galmes -- Fichier modèle pour la déclaration de module. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.nono_const.all; use work.isa_const.all; entity adaptisa is generic(A_GENERAL : T_ADDRESS_ISA); port ( bus_address_ext : in T_ADDRESS_ISA; bus_address_in : out T_ADDRESS ); end entity; architecture rtl of adaptisa is signal net_adr : std_logic_vector((NB_BIT_ADDRESS_ISA - NB_BIT_ADDRESS - 1) downto 0); signal net_adr_ref : std_logic_vector((NB_BIT_ADDRESS_ISA - NB_BIT_ADDRESS - 1) downto 0); begin net_adr <= bus_address_ext((NB_BIT_ADDRESS_ISA - 1) downto NB_BIT_ADDRESS); net_adr_ref <= A_GENERAL((NB_BIT_ADDRESS_ISA - 1) downto NB_BIT_ADDRESS); bus_address_in <= bus_address_ext((NB_BIT_ADDRESS-1) downto 0) when (net_adr = net_adr_ref) else (others => '0'); -- process(net_adr) -- begin -- if (net_adr = net_adr_ref) then -- bus_address_in <= bus_address_ext((NB_BIT_ADDRESS-1) downto 0); -- else -- bus_address_in <= (others => '0'); -- end if; -- end process; end rtl;