From c269f323c2bc063f257d32795f1ffb377acd4704 Mon Sep 17 00:00:00 2001 From: galmes Date: Wed, 18 Feb 2004 11:38:43 +0000 Subject: Debug des fichiers modeles pour l'implé,entation des différents blocs de la carte fpga --- 2004/n/fpga/src/modele/bch_modele.vhd | 19 +++++++++++-------- 2004/n/fpga/src/modele/modele.vhd | 18 ++++++++++-------- 2004/n/fpga/src/modele/nono_const.vhd | 6 ++++-- 3 files changed, 25 insertions(+), 18 deletions(-) diff --git a/2004/n/fpga/src/modele/bch_modele.vhd b/2004/n/fpga/src/modele/bch_modele.vhd index a7f1f48..18bc9a7 100644 --- a/2004/n/fpga/src/modele/bch_modele.vhd +++ b/2004/n/fpga/src/modele/bch_modele.vhd @@ -5,7 +5,10 @@ library ieee; use ieee.std_logic_1164.all; -use work.nono_const.all +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.nono_const.all; entity bch_modele is @@ -25,17 +28,17 @@ architecture sim1 of bch_modele is rst : in std_logic; clk : in std_logic; rw : in std_logic; -- read / write - bus_data : inout std_logic_vector ((NB_BIT_DATA - 1) downto 0); - bus_address : in std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0) + bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0); + bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0) ); - end modele; + end component; -- définiton des signaux signal rst : std_logic; - signal clk : std_logic; + signal clk : std_logic := '0'; signal rw : std_logic; -- read / write - signal bus_data : std_logic_vector ((NB_BIT_DATA - 1) downto 0); - signal bus_address : std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0) + signal bus_data : unsigned ((NB_BIT_DATA - 1) downto 0); + signal bus_address : unsigned ((NB_BIT_ADDRESS - 1) downto 0); begin U1 : modele port map ( @@ -47,7 +50,7 @@ begin ); rst <= '1', '0' after CK_PERIOD; - clk <= not clk after CK_PERIOD/2; + clk <= not clk after (CK_PERIOD/2); rw <= '0'; bus_address <= A_REG_IO_DIRECTION, A_REG_IO_DATA after 3*CK_PERIOD, diff --git a/2004/n/fpga/src/modele/modele.vhd b/2004/n/fpga/src/modele/modele.vhd index 701ccbc..366759d 100644 --- a/2004/n/fpga/src/modele/modele.vhd +++ b/2004/n/fpga/src/modele/modele.vhd @@ -5,8 +5,10 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; -use work.nono_const.all +use work.nono_const.all; entity modele is generic ( @@ -23,8 +25,8 @@ entity modele is -- XXX : savoir si read = 0 ou 1 !! rw : in std_logic; -- read (0) / write (1) - bus_data : inout std_logic_vector ((NB_BIT_DATA - 1) downto 0); - bus_address : in std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0) + bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0); + bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0) ); end entity; @@ -34,14 +36,14 @@ begin begin if (rst = '1') then bus_data <= x"00"; - elsif (ck'event and ck = '1') then + elsif (clk'event and clk = '1') then if (bus_address = A_REG1) then - bus_data <= "01"; + bus_data <= x"01"; else if (bus_address = A_REG2) then - bus_data <= "02"; - elsif (bus_address = A_REG2) then - bus_data <= "03"; + bus_data <= x"02"; + elsif (bus_address = A_REG3) then + bus_data <= x"03"; end if; end if; end if; diff --git a/2004/n/fpga/src/modele/nono_const.vhd b/2004/n/fpga/src/modele/nono_const.vhd index 5ad355b..5c2e04a 100644 --- a/2004/n/fpga/src/modele/nono_const.vhd +++ b/2004/n/fpga/src/modele/nono_const.vhd @@ -10,11 +10,13 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; package nono_const is -- Temps d'une période d'horloge - constant CK_PERIOD : time := 20 ns; + constant CK_PERIOD : time := 10 ns; -- Taille d'une addresse sur la carte -- RQ : 10 = nb suffisant @@ -25,7 +27,7 @@ package nono_const is constant NB_BIT_DATA : integer := 8; -- Définition d'un nouveau type : ADDRESS - subtype T_ADDRESS is std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0); + subtype T_ADDRESS is unsigned ((NB_BIT_ADDRESS - 1) downto 0); -- Les différentes banques d'adresses (4 x 256) -- Rq pour Pierre : ça va influer sur le bloc de gestion du bus -- cgit v1.2.3