From 7de0fd178d7b2dbccbf34cbffda38a1f4bdb4583 Mon Sep 17 00:00:00 2001 From: prot Date: Wed, 25 Feb 2004 20:00:21 +0000 Subject: fifo comportementale --- 2004/n/fpga/src/fifo/fifobehav.vhd | 71 +++++ 2004/n/fpga/src/fifo/fifoctlr_cc.vhd | 479 +++++++++++++++--------------- 2004/n/fpga/src/portserie/bch_txserie.vhd | 11 +- 2004/n/fpga/src/portserie/decoder.vhd | 13 +- 2004/n/fpga/src/portserie/fifo.vhd | 7 +- 2004/n/fpga/src/portserie/fifodriver.vhd | 3 +- 2004/n/fpga/src/portserie/portserie.sws | 5 + 2004/n/fpga/src/portserie/txserie.vhd | 29 +- 8 files changed, 353 insertions(+), 265 deletions(-) create mode 100644 2004/n/fpga/src/fifo/fifobehav.vhd diff --git a/2004/n/fpga/src/fifo/fifobehav.vhd b/2004/n/fpga/src/fifo/fifobehav.vhd new file mode 100644 index 0000000..a4fb4b4 --- /dev/null +++ b/2004/n/fpga/src/fifo/fifobehav.vhd @@ -0,0 +1,71 @@ +--------------------------------------------------------------------------- +-- -- +-- Module : fifoctlr_cc.vhd Last Update: 12/13/99 -- +-- -- +-- Description : FIFO controller top level. -- +-- Implements a 511x8 FIFO with common read/write clocks. -- +-- -- +-- The following VHDL code implements a 511x8 FIFO in a Spartan-II -- +-- device. The inputs are a Clock, a Read Enable, a Write Enable, -- +-- Write Data, and a FIFO_gsr signal as an initial reset. The outputs -- +-- are Read Data, Full, Empty, and the FIFOcount outputs, which -- +-- indicate roughly how full the FIFO is. -- +-- -- +--------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity fifobehav is + port (clock_in: IN std_logic; + read_enable_in: IN std_logic; + write_enable_in: IN std_logic; + write_data_in: IN std_logic_vector(7 downto 0); + fifo_gsr_in: IN std_logic; + read_data_out: OUT std_logic_vector(7 downto 0); + full_out: OUT std_logic; + empty_out: OUT std_logic; + fifocount_out: OUT std_logic_vector(3 downto 0)); +END fifobehav; + + +architecture behav of fifobehav is +signal full:std_logic:='0'; + +begin +full_out<=full; + +process(clock_in) +variable contenu:std_logic_vector(7 downto 0); +variable fullindicator:std_logic:='0'; + +begin + if(read_enable_in='1') then + if (fullindicator='0') then + read_data_out<="00000000"; + else + read_data_out<=contenu; + fullindicator:='0'; + full<='0'; + end if; + else + read_data_out<="00000000"; + end if; + + if(write_enable_in='1') then + if(fullindicator='0') then + contenu:=write_data_in; + fullindicator:='1'; + full<='1'; + end if; + end if; + + if(fifo_gsr_in='1') then + contenu:="00000000"; + fullindicator:='0'; + full<='0'; + end if; +end process; +end behav; + diff --git a/2004/n/fpga/src/fifo/fifoctlr_cc.vhd b/2004/n/fpga/src/fifo/fifoctlr_cc.vhd index edc9502..807bc56 100644 --- a/2004/n/fpga/src/fifo/fifoctlr_cc.vhd +++ b/2004/n/fpga/src/fifo/fifoctlr_cc.vhd @@ -1,238 +1,241 @@ - ---------------------------------------------------------------------------- --- -- --- Module : fifoctlr_cc.vhd Last Update: 12/13/99 -- --- -- --- Description : FIFO controller top level. -- --- Implements a 511x8 FIFO with common read/write clocks. -- --- -- --- The following VHDL code implements a 511x8 FIFO in a Spartan-II -- --- device. The inputs are a Clock, a Read Enable, a Write Enable, -- --- Write Data, and a FIFO_gsr signal as an initial reset. The outputs -- --- are Read Data, Full, Empty, and the FIFOcount outputs, which -- --- indicate roughly how full the FIFO is. -- --- -- ---------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity fifoctlr_cc is - port (clock_in: IN std_logic; - read_enable_in: IN std_logic; - write_enable_in: IN std_logic; - write_data_in: IN std_logic_vector(7 downto 0); - fifo_gsr_in: IN std_logic; - read_data_out: OUT std_logic_vector(7 downto 0); - full_out: OUT std_logic; - empty_out: OUT std_logic; - fifocount_out: OUT std_logic_vector(3 downto 0)); -END fifoctlr_cc; - -architecture fifoctlr_cc_hdl of fifoctlr_cc is - signal clock: std_logic; - signal read_enable: std_logic; - signal write_enable: std_logic; - signal fifo_gsr: std_logic; - signal read_data: std_logic_vector(7 downto 0) := "00000000"; - signal write_data: std_logic_vector(7 downto 0); - signal full: std_logic; - signal empty: std_logic; - signal read_addr: std_logic_vector(8 downto 0) := "000000000"; - signal write_addr: std_logic_vector(8 downto 0) := "000000000"; - signal fcounter: std_logic_vector(8 downto 0) := "000000000"; - signal read_allow: std_logic; - signal write_allow: std_logic; - signal gnd: std_logic; - signal gnd_bus: std_logic_vector(7 downto 0); - signal pwr: std_logic; - signal read_linearfeedback: std_logic; - signal write_linearfeedback: std_logic; - -component BUFGP - port ( - I: IN std_logic; - O: OUT std_logic); -END component; - -component RAMB4_S8_S8 - port ( - ADDRA: IN std_logic_vector(8 downto 0); - ADDRB: IN std_logic_vector(8 downto 0); - DIA: IN std_logic_vector(7 downto 0); - DIB: IN std_logic_vector(7 downto 0); - WEA: IN std_logic; - WEB: IN std_logic; - CLKA: IN std_logic; - CLKB: IN std_logic; - RSTA: IN std_logic; - RSTB: IN std_logic; - ENA: IN std_logic; - ENB: IN std_logic; - DOA: OUT std_logic_vector(7 downto 0); - DOB: OUT std_logic_vector(7 downto 0)); -END component; - -BEGIN - read_enable <= read_enable_in; - write_enable <= write_enable_in; - fifo_gsr <= fifo_gsr_in; - write_data <= write_data_in; - read_data_out <= read_data; - full_out <= full; - empty_out <= empty; - read_allow <= (read_enable AND NOT empty); - write_allow <= (write_enable AND NOT full); - gnd_bus <= "00000000"; - gnd <= '0'; - pwr <= '1'; - --------------------------------------------------------------------------- --- -- --- A global buffer is instantianted to avoid skew problems. -- --- -- --------------------------------------------------------------------------- - -gclk1: BUFGP port map (I => clock_in, O => clock); - --------------------------------------------------------------------------- --- -- --- Block RAM instantiation for FIFO. Module is 512x8, of which one -- --- address location is sacrificed for the overall speed of the design. -- --- -- --------------------------------------------------------------------------- - -bram1: RAMB4_S8_S8 port map (ADDRA => read_addr, ADDRB => write_addr, - DIB => write_data, DIA => gnd_bus, WEA => gnd, - WEB => write_allow, CLKA => clock, CLKB => clock, - RSTA => gnd, RSTB => gnd, ENA => read_allow, ENB => pwr, - DOA => read_data); - ---------------------------------------------------------------- --- -- --- Empty flag is set on fifo_gsr (initial), or when on the -- --- next clock cycle, Write Enable is low, and either the -- --- FIFOcount is equal to 0, or it is equal to 1 and Read -- --- Enable is high (about to go Empty). -- --- -- ---------------------------------------------------------------- - -proc1: PROCESS (clock, fifo_gsr) -BEGIN - IF (fifo_gsr = '1') THEN - empty <= '1'; - ELSIF (clock'EVENT AND clock = '1') THEN - IF ((fcounter(8 downto 1) = "00000000") AND (write_enable = '0') AND - ((fcounter(0) = '0') OR (read_enable = '1'))) THEN - empty <= '1'; - ELSE - empty <= '0'; - END IF; - END IF; -END PROCESS proc1; - ---------------------------------------------------------------- --- -- --- Full flag is set on fifo_gsr (but it is cleared on the -- --- first valid clock edge after fifo_gsr is removed), or -- --- when on the next clock cycle, Read Enable is low, and -- --- either the FIFOcount is equal to 1FF (hex), or it is -- --- equal to 1FE and the Write Enable is high (about to go -- --- Full). -- --- -- ---------------------------------------------------------------- - -proc2: PROCESS (clock, fifo_gsr) -BEGIN - IF (fifo_gsr = '1') THEN - full <= '1'; - ELSIF (clock'EVENT AND clock = '1') THEN - IF ((fcounter(8 downto 1) = "11111111") AND (read_enable = '0') AND - ((fcounter(0) = '1') OR (write_enable = '1'))) THEN - full <= '1'; - ELSE - full <= '0'; - END IF; - END IF; -END PROCESS proc2; - ----------------------------------------------------------------- --- -- --- Generation of Read and Write address pointers. They use -- --- LFSR counters, which are very fast. Because of the -- --- nature of LFSRs, one address is sacrificed. -- --- -- ----------------------------------------------------------------- - -read_linearfeedback <= NOT (read_addr(8) XOR read_addr(4)); -write_linearfeedback <= NOT (write_addr(8) XOR write_addr(4)); - -proc3: PROCESS (clock, fifo_gsr) -BEGIN - IF (fifo_gsr = '1') THEN - read_addr <= "000000000"; - ELSIF (clock'EVENT AND clock = '1') THEN - IF (read_allow = '1') THEN - read_addr(8) <= read_addr(7); - read_addr(7) <= read_addr(6); - read_addr(6) <= read_addr(5); - read_addr(5) <= read_addr(4); - read_addr(4) <= read_addr(3); - read_addr(3) <= read_addr(2); - read_addr(2) <= read_addr(1); - read_addr(1) <= read_addr(0); - read_addr(0) <= read_linearfeedback; - END IF; - END IF; -END PROCESS proc3; - -proc4: PROCESS (clock, fifo_gsr) -BEGIN - IF (fifo_gsr = '1') THEN - write_addr <= "000000000"; - ELSIF (clock'EVENT AND clock = '1') THEN - IF (write_allow = '1') THEN - write_addr(8) <= write_addr(7); - write_addr(7) <= write_addr(6); - write_addr(6) <= write_addr(5); - write_addr(5) <= write_addr(4); - write_addr(4) <= write_addr(3); - write_addr(3) <= write_addr(2); - write_addr(2) <= write_addr(1); - write_addr(1) <= write_addr(0); - write_addr(0) <= write_linearfeedback; - END IF; - END IF; -END PROCESS proc4; - ----------------------------------------------------------------- --- -- --- Generation of FIFOcount outputs. Used to determine how -- --- full FIFO is, based on a counter that keeps track of how -- --- many words are in the FIFO. Also used to generate Full -- --- and Empty flags. Only the upper four bits of the counter -- --- are sent outside the module. -- --- -- ----------------------------------------------------------------- - -proc5: PROCESS (clock, fifo_gsr) -BEGIN - IF (fifo_gsr = '1') THEN - fcounter <= "000000000"; - ELSIF (clock'EVENT AND clock = '1') THEN - IF (((read_allow = '1') AND (write_allow = '0')) OR - ((read_allow = '0') AND (write_allow = '1'))) THEN - IF (write_allow = '1') THEN - fcounter <= fcounter + '1'; - ELSE - fcounter <= fcounter - '1'; - END IF; - END IF; - END IF; -END PROCESS proc5; - -fifocount_out <= fcounter(8 downto 5); - -END fifoctlr_cc_hdl; - + +--------------------------------------------------------------------------- +-- -- +-- Module : fifoctlr_cc.vhd Last Update: 12/13/99 -- +-- -- +-- Description : FIFO controller top level. -- +-- Implements a 511x8 FIFO with common read/write clocks. -- +-- -- +-- The following VHDL code implements a 511x8 FIFO in a Spartan-II -- +-- device. The inputs are a Clock, a Read Enable, a Write Enable, -- +-- Write Data, and a FIFO_gsr signal as an initial reset. The outputs -- +-- are Read Data, Full, Empty, and the FIFOcount outputs, which -- +-- indicate roughly how full the FIFO is. -- +-- -- +--------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity fifoctlr_cc is + port (clock_in: IN std_logic; + read_enable_in: IN std_logic; + write_enable_in: IN std_logic; + write_data_in: IN std_logic_vector(7 downto 0); + fifo_gsr_in: IN std_logic; + read_data_out: OUT std_logic_vector(7 downto 0); + full_out: OUT std_logic; + empty_out: OUT std_logic; + fifocount_out: OUT std_logic_vector(3 downto 0)); +END fifoctlr_cc; + + +architecture fifoctlr_cc_hdl of fifoctlr_cc is + signal clock: std_logic; + signal read_enable: std_logic; + signal write_enable: std_logic; + signal fifo_gsr: std_logic; + signal read_data: std_logic_vector(7 downto 0) := "00000000"; + signal write_data: std_logic_vector(7 downto 0); + signal full: std_logic; + signal empty: std_logic; + signal read_addr: std_logic_vector(8 downto 0) := "000000000"; + signal write_addr: std_logic_vector(8 downto 0) := "000000000"; + signal fcounter: std_logic_vector(8 downto 0) := "000000000"; + signal read_allow: std_logic; + signal write_allow: std_logic; + signal gnd: std_logic; + signal gnd_bus: std_logic_vector(7 downto 0); + signal pwr: std_logic; + signal read_linearfeedback: std_logic; + signal write_linearfeedback: std_logic; + +component BUFGP + port ( + I: IN std_logic; + O: OUT std_logic); +END component; + +component RAMB4_S8_S8 + port ( + ADDRA: IN std_logic_vector(8 downto 0); + ADDRB: IN std_logic_vector(8 downto 0); + DIA: IN std_logic_vector(7 downto 0); + DIB: IN std_logic_vector(7 downto 0); + WEA: IN std_logic; + WEB: IN std_logic; + CLKA: IN std_logic; + CLKB: IN std_logic; + RSTA: IN std_logic; + RSTB: IN std_logic; + ENA: IN std_logic; + ENB: IN std_logic; + DOA: OUT std_logic_vector(7 downto 0); + DOB: OUT std_logic_vector(7 downto 0)); +END component; + +BEGIN + read_enable <= read_enable_in; + write_enable <= write_enable_in; + fifo_gsr <= fifo_gsr_in; + write_data <= write_data_in; + read_data_out <= read_data; + full_out <= full; + empty_out <= empty; + read_allow <= (read_enable AND NOT empty); + write_allow <= (write_enable AND NOT full); + gnd_bus <= "00000000"; + gnd <= '0'; + pwr <= '1'; + +-------------------------------------------------------------------------- +-- -- +-- A global buffer is instantianted to avoid skew problems. -- +-- -- +-------------------------------------------------------------------------- + +gclk1: BUFGP port map (I => clock_in, O => clock); + +-------------------------------------------------------------------------- +-- -- +-- Block RAM instantiation for FIFO. Module is 512x8, of which one -- +-- address location is sacrificed for the overall speed of the design. -- +-- -- +-------------------------------------------------------------------------- + +bram1: RAMB4_S8_S8 port map (ADDRA => read_addr, ADDRB => write_addr, + DIB => write_data, DIA => gnd_bus, WEA => gnd, + WEB => write_allow, CLKA => clock, CLKB => clock, + RSTA => gnd, RSTB => gnd, ENA => read_allow, ENB => pwr, + DOA => read_data); + +--------------------------------------------------------------- +-- -- +-- Empty flag is set on fifo_gsr (initial), or when on the -- +-- next clock cycle, Write Enable is low, and either the -- +-- FIFOcount is equal to 0, or it is equal to 1 and Read -- +-- Enable is high (about to go Empty). -- +-- -- +--------------------------------------------------------------- + +proc1: PROCESS (clock, fifo_gsr) +BEGIN + IF (fifo_gsr = '1') THEN + empty <= '1'; + ELSIF (clock'EVENT AND clock = '1') THEN + IF ((fcounter(8 downto 1) = "00000000") AND (write_enable = '0') AND + ((fcounter(0) = '0') OR (read_enable = '1'))) THEN + empty <= '1'; + ELSE + empty <= '0'; + END IF; + END IF; +END PROCESS proc1; + +--------------------------------------------------------------- +-- -- +-- Full flag is set on fifo_gsr (but it is cleared on the -- +-- first valid clock edge after fifo_gsr is removed), or -- +-- when on the next clock cycle, Read Enable is low, and -- +-- either the FIFOcount is equal to 1FF (hex), or it is -- +-- equal to 1FE and the Write Enable is high (about to go -- +-- Full). -- +-- -- +--------------------------------------------------------------- + +proc2: PROCESS (clock, fifo_gsr) +BEGIN + IF (fifo_gsr = '1') THEN + full <= '1'; + ELSIF (clock'EVENT AND clock = '1') THEN + IF ((fcounter(8 downto 1) = "11111111") AND (read_enable = '0') AND + ((fcounter(0) = '1') OR (write_enable = '1'))) THEN + full <= '1'; + ELSE + full <= '0'; + END IF; + END IF; +END PROCESS proc2; + +---------------------------------------------------------------- +-- -- +-- Generation of Read and Write address pointers. They use -- +-- LFSR counters, which are very fast. Because of the -- +-- nature of LFSRs, one address is sacrificed. -- +-- -- +---------------------------------------------------------------- + +read_linearfeedback <= NOT (read_addr(8) XOR read_addr(4)); +write_linearfeedback <= NOT (write_addr(8) XOR write_addr(4)); + +proc3: PROCESS (clock, fifo_gsr) +BEGIN + IF (fifo_gsr = '1') THEN + read_addr <= "000000000"; + ELSIF (clock'EVENT AND clock = '1') THEN + IF (read_allow = '1') THEN + read_addr(8) <= read_addr(7); + read_addr(7) <= read_addr(6); + read_addr(6) <= read_addr(5); + read_addr(5) <= read_addr(4); + read_addr(4) <= read_addr(3); + read_addr(3) <= read_addr(2); + read_addr(2) <= read_addr(1); + read_addr(1) <= read_addr(0); + read_addr(0) <= read_linearfeedback; + END IF; + END IF; +END PROCESS proc3; + +proc4: PROCESS (clock, fifo_gsr) +BEGIN + IF (fifo_gsr = '1') THEN + write_addr <= "000000000"; + ELSIF (clock'EVENT AND clock = '1') THEN + IF (write_allow = '1') THEN + write_addr(8) <= write_addr(7); + write_addr(7) <= write_addr(6); + write_addr(6) <= write_addr(5); + write_addr(5) <= write_addr(4); + write_addr(4) <= write_addr(3); + write_addr(3) <= write_addr(2); + write_addr(2) <= write_addr(1); + write_addr(1) <= write_addr(0); + write_addr(0) <= write_linearfeedback; + END IF; + END IF; +END PROCESS proc4; + +---------------------------------------------------------------- +-- -- +-- Generation of FIFOcount outputs. Used to determine how -- +-- full FIFO is, based on a counter that keeps track of how -- +-- many words are in the FIFO. Also used to generate Full -- +-- and Empty flags. Only the upper four bits of the counter -- +-- are sent outside the module. -- +-- -- +---------------------------------------------------------------- + +proc5: PROCESS (clock, fifo_gsr) +BEGIN + IF (fifo_gsr = '1') THEN + fcounter <= "000000000"; + ELSIF (clock'EVENT AND clock = '1') THEN + IF (((read_allow = '1') AND (write_allow = '0')) OR + ((read_allow = '0') AND (write_allow = '1'))) THEN + IF (write_allow = '1') THEN + fcounter <= fcounter + '1'; + ELSE + fcounter <= fcounter - '1'; + END IF; + END IF; + END IF; +END PROCESS proc5; + +fifocount_out <= fcounter(8 downto 5); + +END fifoctlr_cc_hdl; + + + diff --git a/2004/n/fpga/src/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/bch_txserie.vhd index f976ce3..735078d 100644 --- a/2004/n/fpga/src/portserie/bch_txserie.vhd +++ b/2004/n/fpga/src/portserie/bch_txserie.vhd @@ -67,13 +67,14 @@ begin ); rst <= '1', '0' after CK_PERIOD; - clk <= not clk after (CK_PERIOD/2); + clk <= not clk after (CK_PERIOD); rw <= '0'; bus_address <= "0000000011", - "0000000100" after 3*CK_PERIOD, - "0000000010" after 5*CK_PERIOD; + "0000000100" after 6*CK_PERIOD, + "0000000100" after 10*CK_PERIOD, + "0000000011" after 16*CK_PERIOD; bus_data <= "01010101";--) after 10 ns; - masterck<= not masterck after (CK_PERIOD/3); + masterck<= not masterck after (CK_PERIOD/11); end sim1; @@ -85,3 +86,5 @@ end cf1_bch_txserie; + + diff --git a/2004/n/fpga/src/portserie/decoder.vhd b/2004/n/fpga/src/portserie/decoder.vhd index 920431d..ac586b6 100644 --- a/2004/n/fpga/src/portserie/decoder.vhd +++ b/2004/n/fpga/src/portserie/decoder.vhd @@ -11,7 +11,7 @@ use ieee.std_logic_unsigned.all; use work.nono_const.all; entity decoder is - generic(adr : T_ADDRESS); + generic(adr : T_ADDRESS:="0000000000"); port( bus_address : in T_ADDRESS; cs: out std_logic:='0' @@ -22,14 +22,13 @@ architecture rtl of decoder is begin process(bus_address) begin - --if(bus_address = adr) - --then + if(bus_address = adr) + then + cs<='0'; + else cs<='1'; - --else - -- cs<='0'; - --end if; + end if; end process; end rtl; - diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd index 925dbf0..f2a7d22 100644 --- a/2004/n/fpga/src/portserie/fifo.vhd +++ b/2004/n/fpga/src/portserie/fifo.vhd @@ -34,7 +34,8 @@ component fifodriver is ); end component; -component fifoctlr_cc is +--component fifoctlr_cc is +component fifobehav is port (clock_in: IN std_logic; read_enable_in: IN std_logic; write_enable_in: IN std_logic; @@ -69,7 +70,8 @@ begin -FIFO1:fifoctlr_cc +--FIFO1:fifoctlr_cc +FIFO1:fifobehav port map( clock_in=>clock_fifo, read_enable_in=>read_enable, @@ -101,3 +103,4 @@ end rtl; + diff --git a/2004/n/fpga/src/portserie/fifodriver.vhd b/2004/n/fpga/src/portserie/fifodriver.vhd index 974871e..15ab56c 100644 --- a/2004/n/fpga/src/portserie/fifodriver.vhd +++ b/2004/n/fpga/src/portserie/fifodriver.vhd @@ -18,7 +18,7 @@ entity fifodriver is fiforead:out std_logic; fifowrite:out std_logic ); - constant PRESCAL :integer:= 16; + constant PRESCAL :integer:= 1; end fifodriver; architecture rtl of fifodriver is @@ -76,3 +76,4 @@ begin end rtl; + diff --git a/2004/n/fpga/src/portserie/portserie.sws b/2004/n/fpga/src/portserie/portserie.sws index 6ec0881..e528e6d 100644 --- a/2004/n/fpga/src/portserie/portserie.sws +++ b/2004/n/fpga/src/portserie/portserie.sws @@ -148,6 +148,11 @@ [options] [] [] + [file] + name = fifo/fifobehav.vhd + [options] + [] + [] [file] name = fifo.vhd [options] diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd index 81b5b5c..48872cd 100644 --- a/2004/n/fpga/src/portserie/txserie.vhd +++ b/2004/n/fpga/src/portserie/txserie.vhd @@ -112,22 +112,20 @@ component decoder end component; ---signal fifoEmpty: std_logic; ---signal fifoFull: std_logic; +signal fifoEmpty: std_logic; +signal fifoFull: std_logic; --signal fifoLI1: std_logic; --signal fifoLI0: std_logic; --signal BdR1: std_logic; --signal BdR0: std_logic; signal purge: std_logic:='0'; -signal geneck: std_logic; signal txck: std_logic; -signal busck: std_logic; signal confreg: T_DATA; signal flagreg: T_DATA; signal interflag: std_logic_vector(5 downto 0); signal datareg: T_DATA; signal inter_data: T_DATA; -signal txempty: std_logic; +signal txempty: std_logic:='1'; signal csFifo: std_logic; signal fifockin: std_logic; signal fifockout: std_logic; @@ -146,10 +144,10 @@ FIFO1: fifo flagreg(5 downto 0)<=interflag; -fifockin<=csFifo and not rw and busck; -fifockout<=txempty; -- ŕ vérifier !!! Cette ligne est valable pour - -- txempty=1 quand le tx est vide - +fifockin<=csFifo and clk and not rw; +fifockout<=txempty and not fifoempty +; -- ŕ vérifier !!! Cette ligne est valable pour txempty=1 quand le tx est vide + TX1 : transmitter port map( data_in=>inter_data, @@ -160,7 +158,7 @@ TX1 : transmitter CLOCK1 : clockgene port map( - ckin=>geneck, + ckin=>masterck, ckout=>txck, param=>"11" --confreg(1 downto 0) ); @@ -168,9 +166,12 @@ CLOCK1 : clockgene --geneck<='1'; --confreg(4) and masterck; -- On/Off et masterck +fifofull<=interflag(4); +fifoEmpty<=interflag(5); + -- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) RCONF : regIO - generic map(adr=>A_DATA) + generic map(adr=>A_CONFIG) port map( bus_address=>bus_address, bus_data=>bus_data, @@ -178,7 +179,7 @@ RCONF : regIO output=>confreg, rw=>rw, load=>'0', - ck=>busck, + ck=>clk, rst=>'0' ); @@ -192,7 +193,7 @@ RFLAG : regIO output=>open, rw=>rw, load=>'1', - ck=>busck, + ck=>clk, rst=>'0' ); @@ -211,3 +212,5 @@ end rtl; + + -- cgit v1.2.3