From 7ce31c6698e8456f14740a830f93baed2272ad44 Mon Sep 17 00:00:00 2001 From: prot Date: Sun, 14 Mar 2004 23:34:21 +0000 Subject: Ménage --- 2004/n/fpga/src/portserie/uart/RxUnit.vhd | 155 ------------------ 2004/n/fpga/src/portserie/uart/TxUnit.vhd | 116 -------------- 2004/n/fpga/src/portserie/uart/UARTtest.vhd | 214 ------------------------- 2004/n/fpga/src/portserie/uart/bch_txserie.vhd | 140 ---------------- 2004/n/fpga/src/portserie/uart/clkUnit.vhd | 136 ---------------- 2004/n/fpga/src/portserie/uart/miniUART.vhd | 205 ----------------------- 2004/n/fpga/src/portserie/uart/uart.npl | 26 +++ 2004/n/fpga/src/portserie/uart/uart_lib.vhd | 60 ------- 8 files changed, 26 insertions(+), 1026 deletions(-) delete mode 100644 2004/n/fpga/src/portserie/uart/RxUnit.vhd delete mode 100644 2004/n/fpga/src/portserie/uart/TxUnit.vhd delete mode 100644 2004/n/fpga/src/portserie/uart/UARTtest.vhd delete mode 100644 2004/n/fpga/src/portserie/uart/bch_txserie.vhd delete mode 100644 2004/n/fpga/src/portserie/uart/clkUnit.vhd delete mode 100644 2004/n/fpga/src/portserie/uart/miniUART.vhd create mode 100644 2004/n/fpga/src/portserie/uart/uart.npl delete mode 100644 2004/n/fpga/src/portserie/uart/uart_lib.vhd diff --git a/2004/n/fpga/src/portserie/uart/RxUnit.vhd b/2004/n/fpga/src/portserie/uart/RxUnit.vhd deleted file mode 100644 index 148abde..0000000 --- a/2004/n/fpga/src/portserie/uart/RxUnit.vhd +++ /dev/null @@ -1,155 +0,0 @@ ---===========================================================================-- --- --- S Y N T H E Z I A B L E miniUART C O R E --- --- www.OpenCores.Org - January 2000 --- This core adheres to the GNU public license --- --- Design units : miniUART core for the OCRP-1 --- --- File name : RxUnit.vhd --- --- Purpose : Implements an miniUART device for communication purposes --- between the OR1K processor and the Host computer through --- an RS-232 communication protocol. --- --- Library : uart_lib.vhd --- --- Dependencies : IEEE.Std_Logic_1164 --- ---===========================================================================-- -------------------------------------------------------------------------------- --- Revision list --- Version Author Date Changes --- --- 0.1 Ovidiu Lupas 15 January 2000 New model --- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0 --- olupas@opencores.org -------------------------------------------------------------------------------- --- Description : Implements the receive unit of the miniUART core. Samples --- 16 times the RxD line and retain the value in the middle of --- the time interval. -------------------------------------------------------------------------------- --- Entity for Receive Unit - 9600 baudrate -- -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; -library work; - use work.UART_Def.all; -------------------------------------------------------------------------------- --- Receive unit -------------------------------------------------------------------------------- -entity RxUnit is - port ( - Clk : in Std_Logic; -- system clock signal - Reset : in Std_Logic; -- Reset input - Enable : in Std_Logic; -- Enable input - RxD : in Std_Logic; -- RS-232 data input - RD : in Std_Logic; -- Read data signal - FErr : out Std_Logic; -- Status signal - OErr : out Std_Logic; -- Status signal - DRdy : out Std_Logic; -- Status signal - DataIn : out Std_Logic_Vector(7 downto 0)); -end entity; --================== End of entity ==============================-- -------------------------------------------------------------------------------- --- Architecture for receive Unit -------------------------------------------------------------------------------- -architecture Behaviour of RxUnit is - ----------------------------------------------------------------------------- - -- Signals - ----------------------------------------------------------------------------- - signal Start : Std_Logic; -- Syncro signal - signal tmpRxD : Std_Logic; -- RxD buffer - signal tmpDRdy : Std_Logic; -- Data ready buffer - signal outErr : Std_Logic; -- - signal frameErr : Std_Logic; -- - signal BitCnt : Unsigned(3 downto 0); -- - signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter - signal ShtReg : Std_Logic_Vector(7 downto 0); -- - signal DOut : Std_Logic_Vector(7 downto 0); -- -begin - --------------------------------------------------------------------- - -- Receiver process - --------------------------------------------------------------------- - RcvProc : process(Clk,Reset,Enable,RxD) - variable tmpBitCnt : Integer range 0 to 15; - variable tmpSampleCnt : Integer range 0 to 15; - constant CntOne : Unsigned(3 downto 0):="0001"; - begin - if Rising_Edge(Clk) then - tmpBitCnt := ToInteger(BitCnt); - tmpSampleCnt := ToInteger(SampleCnt); - if Reset = '0' then - BitCnt <= "0000"; - SampleCnt <= "0000"; - Start <= '0'; - tmpDRdy <= '0'; - frameErr <= '0'; - outErr <= '0'; - - ShtReg <= "00000000"; -- - DOut <= "00000000"; -- - else - if RD = '1' then - tmpDRdy <= '0'; -- Data was read - end if; - - if Enable = '1' then - if Start = '0' then - if RxD = '0' then -- Start bit, - SampleCnt <= SampleCnt + CntOne; - Start <= '1'; - end if; - else - if tmpSampleCnt = 8 then -- reads the RxD line - tmpRxD <= RxD; - SampleCnt <= SampleCnt + CntOne; - elsif tmpSampleCnt = 15 then - case tmpBitCnt is - when 0 => - if tmpRxD = '1' then -- Start Bit - Start <= '0'; - else - BitCnt <= BitCnt + CntOne; - end if; - SampleCnt <= SampleCnt + CntOne; - when 1|2|3|4|5|6|7|8 => - BitCnt <= BitCnt + CntOne; - SampleCnt <= SampleCnt + CntOne; - ShtReg <= tmpRxD & ShtReg(7 downto 1); - when 9 => - if tmpRxD = '0' then -- stop bit expected - frameErr <= '1'; - else - frameErr <= '0'; - end if; - - if tmpDRdy = '1' then -- - outErr <= '1'; - else - outErr <= '0'; - end if; - - tmpDRdy <= '1'; - DOut <= ShtReg; - BitCnt <= "0000"; - Start <= '0'; - when others => - null; - end case; - else - SampleCnt <= SampleCnt + CntOne; - end if; - end if; - end if; - end if; - end if; - end process; - - DRdy <= tmpDRdy; - DataIn <= DOut; - FErr <= frameErr; - OErr <= outErr; - -end Behaviour; --==================== End of architecture ==================== diff --git a/2004/n/fpga/src/portserie/uart/TxUnit.vhd b/2004/n/fpga/src/portserie/uart/TxUnit.vhd deleted file mode 100644 index 424beeb..0000000 --- a/2004/n/fpga/src/portserie/uart/TxUnit.vhd +++ /dev/null @@ -1,116 +0,0 @@ ---===========================================================================-- --- --- S Y N T H E Z I A B L E miniUART C O R E --- --- www.OpenCores.Org - January 2000 --- This core adheres to the GNU public license --- --- Design units : miniUART core for the OCRP-1 --- --- File name : TxUnit.vhd --- --- Purpose : Implements an miniUART device for communication purposes --- between the OR1K processor and the Host computer through --- an RS-232 communication protocol. --- --- Library : uart_lib.vhd --- --- Dependencies : IEEE.Std_Logic_1164 --- ---===========================================================================-- -------------------------------------------------------------------------------- --- Revision list --- Version Author Date Changes --- --- 0.1 Ovidiu Lupas 15 January 2000 New model --- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed --- olupas@opencores.org -------------------------------------------------------------------------------- --- Description : -------------------------------------------------------------------------------- --- Entity for the Tx Unit -- -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library work; -use work.Uart_Def.all; -------------------------------------------------------------------------------- --- Transmitter unit -------------------------------------------------------------------------------- -entity TxUnit is - port ( - Clk : in Std_Logic; -- Clock signal - Reset : in Std_Logic; -- Reset input - Enable : in Std_Logic; -- Enable input - Load : in Std_Logic; -- Load transmit data - TxD : out Std_Logic; -- RS-232 data output - TRegE : out Std_Logic; -- Tx register empty - TBufE : out Std_Logic; -- Tx buffer empty - DataO : in Std_Logic_Vector(7 downto 0)); -end entity; --================== End of entity ==============================-- -------------------------------------------------------------------------------- --- Architecture for TxUnit -------------------------------------------------------------------------------- -architecture Behaviour of TxUnit is - ----------------------------------------------------------------------------- - -- Signals - ----------------------------------------------------------------------------- - signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer - signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register - signal BitCnt : Unsigned(3 downto 0); -- bit counter - signal tmpTRegE : Std_Logic; -- - signal tmpTBufE : Std_Logic; -- -begin - ----------------------------------------------------------------------------- - -- Implements the Tx unit - ----------------------------------------------------------------------------- - process(Clk,Reset,Enable,Load,DataO,TBuff,TReg,tmpTRegE,tmpTBufE) - variable tmp_TRegE : Std_Logic; - constant CntOne : Unsigned(3 downto 0):="0001"; - begin - if Rising_Edge(Clk) then - if Reset = '0' then - tmpTRegE <= '1'; - tmpTBufE <= '1'; - TxD <= '1'; - BitCnt <= "0000"; - elsif Load = '1' then - TBuff <= DataO; - tmpTBufE <= '0'; - elsif Enable = '1' then - if ( tmpTBufE = '0') and (tmpTRegE = '1') then - TReg <= TBuff; - tmpTRegE <= '0'; --- tmp_TRegE := '0'; - tmpTBufE <= '1'; --- else --- tmp_TRegE := tmpTRegE; - end if; - - if tmpTRegE = '0' then - case BitCnt is - when "0000" => - TxD <= '0'; - BitCnt <= BitCnt + CntOne; - when "0001" | "0010" | "0011" | - "0100" | "0101" | "0110" | - "0111" | "1000" => - TxD <= TReg(0); - TReg <= '1' & TReg(7 downto 1); - BitCnt <= BitCnt + CntOne; - when "1001" => - TxD <= '1'; - TReg <= '1' & TReg(7 downto 1); - BitCnt <= "0000"; - tmpTRegE <= '1'; - when others => null; - end case; - end if; - end if; - end if; - end process; - - TRegE <= tmpTRegE; - TBufE <= tmpTBufE; -end Behaviour; --=================== End of architecture ====================-- \ No newline at end of file diff --git a/2004/n/fpga/src/portserie/uart/UARTtest.vhd b/2004/n/fpga/src/portserie/uart/UARTtest.vhd deleted file mode 100644 index 1533126..0000000 --- a/2004/n/fpga/src/portserie/uart/UARTtest.vhd +++ /dev/null @@ -1,214 +0,0 @@ ---============================================================================-- --- Design units : TestBench for miniUART device. --- --- File name : UARTTest.vhd --- --- Purpose : Implements the test bench for miniUART device. --- --- Library : uart_Lib.vhd --- --- Dependencies : IEEE.Std_Logic_1164 --- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --- Revision list --- Version Author Date Changes --- --- 0.1 Ovidiu Lupas December 1999 New model --------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --- Clock generator -------------------------------------------------------------------------------- -library IEEE,work; -use IEEE.Std_Logic_1164.all; --- -entity ClkGen is - port ( - Clk : out Std_Logic); -- Oscillator clock -end ClkGen;--==================== End of entity ==============================-- --------------------------------------------------------------------------------- --- Architecture for clock and reset signals generator --------------------------------------------------------------------------------- -architecture Behaviour of ClkGen is -begin --========================== Architecture ==============================-- - ------------------------------------------------------------------------------ - -- Provide the system clock signal - ------------------------------------------------------------------------------ - ClkDriver : process - variable clktmp : Std_Logic := '1'; - variable tpw_CI_posedge : Time := 12 ns; -- ~40 MHz - begin - Clk <= clktmp; - clktmp := not clktmp; - wait for tpw_CI_posedge; - end process; -end Behaviour; --=================== End of architecure =====================-- -------------------------------------------------------------------------------- --- LoopBack Device -------------------------------------------------------------------------------- -library IEEE,work; -use IEEE.Std_Logic_1164.all; --- -entity LoopBack is - port ( - Clk : in Std_Logic; -- Oscillator clock - RxWr : in Std_Logic; -- Rx line - TxWr : out Std_Logic); -- Tx line -end LoopBack; --==================== End of entity ==========================-- --------------------------------------------------------------------------------- --- Architecture for clock and reset signals generator --------------------------------------------------------------------------------- -architecture Behaviour of LoopBack is -begin --========================== Architecture ==============================-- - ------------------------------------------------------------------------------ - -- Provide the external clock signal - ------------------------------------------------------------------------------ - ClkTrig : process(Clk) - begin - TxWr <= RxWr; - end process; -end Behaviour; --=================== End of architecure =====================-- - --------------------------------------------------------------------------------- --- Testbench for UART device --------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library work; -use work.Uart_Def.all; - -entity UARTTEST is -end UARTTEST; - -architecture stimulus of UARTTEST is - ------------------------------------------------------------------- - -- Signals - ------------------------------------------------------------------- - signal Reset : Std_Logic; -- Synchro signal - signal Clk : Std_Logic; -- Clock signal - signal DataIn : Std_Logic_Vector(7 downto 0); - signal DataOut : Std_Logic_Vector(7 downto 0); - signal RxD : Std_Logic; -- RS-232 data input - signal TxD : Std_Logic; -- RS-232 data output - signal CS_N : Std_Logic; - signal RD_N : Std_Logic; - signal WR_N : Std_Logic; - signal IntRx_N : Std_Logic; -- Receive interrupt - signal IntTx_N : Std_Logic; -- Transmit interrupt - signal Addr : Std_Logic_Vector(1 downto 0); -- - ------------------------------------------------------------------- - -- Clock Divider - ------------------------------------------------------------------- - component ClkGen is - port ( - Clk : out Std_Logic); -- Oscillator clock - end component; - ------------------------------------------------------------------- - -- LoopBack Device - ------------------------------------------------------------------- - component LoopBack is - port ( - Clk : in Std_Logic; -- Oscillator clock - RxWr : in Std_Logic; -- Rx line - TxWr : out Std_Logic); -- Tx line - end component; - ------------------------------------------------------------------- - -- UART Device - ------------------------------------------------------------------- - component miniUART is - port ( - SysClk : in Std_Logic; -- System Clock - Reset : in Std_Logic; -- Reset input - CS_N : in Std_Logic; - RD_N : in Std_Logic; - WR_N : in Std_Logic; - RxD : in Std_Logic; - TxD : out Std_Logic; - IntRx_N : out Std_Logic; -- Receive interrupt - IntTx_N : out Std_Logic; -- Transmit interrupt - Addr : in Std_Logic_Vector(1 downto 0); -- - DataIn : in Std_Logic_Vector(7 downto 0); -- - DataOut : out Std_Logic_Vector(7 downto 0)); -- - end component; -begin --======================== Architecture ========================-- - --------------------------------------------------------------------- - -- Instantiation of components - --------------------------------------------------------------------- - Clock : ClkGen port map (Clk); - LoopDev : LoopBack port map (Clk,TxD,RxD); - miniUARTDev : miniUART port map (Clk,Reset,CS_N,RD_N,WR_N,RxD,TxD, - IntRx_N,IntTx_N,Addr,DataIn,DataOut); - --------------------------------------------------------------------- - -- Reset cycle - --------------------------------------------------------------------- - RstCyc : process - begin - Reset <= '1'; - wait for 5 ns; - Reset <= '0'; - wait for 250 ns; - Reset <= '1'; - wait; - end process; - --------------------------------------------------------------------- - -- - --------------------------------------------------------------------- - ProcCyc : process(Clk,IntRx_N,IntTx_N,Reset) - variable counter : unsigned(3 downto 0); - constant cone : unsigned(3 downto 0):= "0001"; - variable temp : bit := '0'; - begin - if Rising_Edge(Reset) then - counter := "0000"; - WR_N <= '1'; - RD_N <= '1'; - CS_N <= '1'; - elsif Rising_Edge(Clk) then - if IntTx_N = '0' then - if temp = '0' then - temp := '1'; - case counter is - when "0000" => - Addr <= "00"; - DataIn <= x"AA"; - WR_N <= '0'; - CS_N <= '0'; - counter := counter + cone; - when "0001" => - Addr <= "00"; - DataIn <= x"AF"; - WR_N <= '0'; - CS_N <= '0'; - counter := counter + cone; - when "0010" => - Addr <= "00"; - DataIn <= x"55"; - WR_N <= '0'; - CS_N <= '0'; - counter := counter + cone; - when "0011" => - Addr <= "00"; - DataIn <= x"E8"; - WR_N <= '0'; - CS_N <= '0'; - counter := "0000"; - when others => null; - end case; - elsif temp = '1' then - temp := '0'; - end if; - elsif IntRx_N = '0' then - Addr <= "00"; - RD_N <= '0'; - CS_N <= '0'; - else - RD_N <= '1'; - CS_N <= '1'; - WR_N <= '1'; - DataIn <= "ZZZZZZZZ"; - end if; - end if; - end process; -end stimulus; --================== End of TestBench ================== - diff --git a/2004/n/fpga/src/portserie/uart/bch_txserie.vhd b/2004/n/fpga/src/portserie/uart/bch_txserie.vhd deleted file mode 100644 index d1aa1e3..0000000 --- a/2004/n/fpga/src/portserie/uart/bch_txserie.vhd +++ /dev/null @@ -1,140 +0,0 @@ --- modele.vhd --- Eurobot 2004 : APB Team --- Auteur : Pierre-André Galmes --- Fichier modèle pour la déclaration de module. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -use work.nono_const.all; - - -entity bch_txserie is -end bch_txserie; - -architecture sim1 of bch_txserie is - - component txserie - generic ( - -- adresses des différents registres du module. - A_DATA : T_ADDRESS ; - A_CONFIG : T_ADDRESS ; - A_FLAG : T_ADDRESS - -- si autre choses à déclarer... - ); - port ( - rst : in std_logic; - clk : in std_logic; - rw : in std_logic; -- read (0) / write (1) - bus_data : inout T_DATA; - bus_address : in T_ADDRESS; - masterck: in std_logic; - txout: out std_logic; - minIRQ: out std_logic - ); - end component; - - --- définiton des signaux -signal rst : std_logic; -signal clk : std_logic := '0'; -signal simclk : std_logic := '0'; -signal rw : std_logic; -- read / write -signal bus_data : T_DATA:="00000000"; -signal bus_address : T_ADDRESS; -signal masterck: std_logic:='0'; -signal txout: std_logic; -signal minIRQ: std_logic; -signal state_next:integer:=0; - -begin - U1 : txserie - generic map ( - -- Définition des addresses. - A_DATA => "0000000001", - A_CONFIG => "0000000010", - A_FLAG => "0000000011" - ) - port map ( - rst => rst, - clk => clk, - rw => rw, - bus_data => bus_data, - bus_address => bus_address, - masterck=> masterck, - txout=> txout, - minIRQ=> minIRQ - ); - - - masterck<= not masterck after (CK_PERIOD/11); - simclk<= not simclk after (CK_PERIOD/2); - - - process(simclk) - begin - if(simclk'event and simclk='1') then - state_next<=(state_next + 1); - end if; - end process; - - process(state_next) - begin - bus_address<="0000000000"; - clk<='0'; - rst<='0'; - bus_data<=(others =>'Z'); - - case state_next is - when 1 => bus_address<="0000000010"; - bus_data<="00010111"; - rw<='0'; - when 2 => bus_address<="0000000010"; - bus_data<="00010111"; - rw<='0'; - clk<='1'; - when 3 => null; - - when 4 => bus_address<="0000000001"; - bus_data<="00010111"; - rw<='0'; - when 5 => bus_address<="0000000001"; - bus_data<="00010111"; - rw<='0'; - clk<='1'; - when 6 => null; - - when 7 => bus_address<="0000000011"; - rw<='1'; - when 8 => bus_address<="0000000011"; - rw<='1'; - clk<='1'; - when 9 => null; - - - when 10 => bus_address<="0000000010"; - rw<='1'; - when 11 => bus_address<="0000000010"; - rw<='1'; - clk<='1'; - when 12 => null; - - when others => null; - end case; - end process; -end sim1; - - -configuration cf1_bch_txserie of bch_txserie is - for sim1 - for all : txserie use entity work.txserie(rtl); end for; - end for; -end cf1_bch_txserie; - - - - - - diff --git a/2004/n/fpga/src/portserie/uart/clkUnit.vhd b/2004/n/fpga/src/portserie/uart/clkUnit.vhd deleted file mode 100644 index 1e42617..0000000 --- a/2004/n/fpga/src/portserie/uart/clkUnit.vhd +++ /dev/null @@ -1,136 +0,0 @@ ---===========================================================================-- --- --- S Y N T H E Z I A B L E miniUART C O R E --- --- www.OpenCores.Org - January 2000 --- This core adheres to the GNU public license - --- Design units : miniUART core for the OCRP-1 --- --- File name : clkUnit.vhd --- --- Purpose : Implements an miniUART device for communication purposes --- between the OR1K processor and the Host computer through --- an RS-232 communication protocol. --- --- Library : uart_lib.vhd --- --- Dependencies : IEEE.Std_Logic_1164 --- ---===========================================================================-- -------------------------------------------------------------------------------- --- Revision list --- Version Author Date Changes --- --- 1.0 Ovidiu Lupas 15 January 2000 New model --- 1.1 Ovidiu Lupas 28 May 2000 EnableRx/EnableTx ratio corrected --- olupas@opencores.org -------------------------------------------------------------------------------- --- Description : Generates the Baud clock and enable signals for RX & TX --- units. -------------------------------------------------------------------------------- --- Entity for Baud rate generator Unit - 9600 baudrate -- -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; -library work; - use work.UART_Def.all; -------------------------------------------------------------------------------- --- Baud rate generator -------------------------------------------------------------------------------- -entity ClkUnit is - port ( - SysClk : in Std_Logic; -- System Clock - EnableRx : out Std_Logic; -- Control signal - EnableTx : out Std_Logic; -- Control signal - Reset : in Std_Logic); -- Reset input -end entity; --================== End of entity ==============================-- -------------------------------------------------------------------------------- --- Architecture for Baud rate generator Unit -------------------------------------------------------------------------------- -architecture Behaviour of ClkUnit is - ----------------------------------------------------------------------------- - -- Signals - ----------------------------------------------------------------------------- - signal ClkDiv26 : Std_Logic; - signal tmpEnRX : Std_Logic; - signal tmpEnTX : Std_Logic; -begin - ----------------------------------------------------------------------------- - -- Divides the system clock of 40 MHz by 26 - ----------------------------------------------------------------------------- - DivClk26 : process(SysClk,Reset) - constant CntOne : unsigned(4 downto 0) := "00001"; - variable Cnt26 : unsigned(4 downto 0); - begin - if Rising_Edge(SysClk) then - if Reset = '0' then - Cnt26 := "00000"; - ClkDiv26 <= '0'; - else - Cnt26 := Cnt26 + CntOne; - case Cnt26 is --- when "11010" => - when "00001" => - ClkDiv26 <= '1'; - Cnt26 := "00000"; - when others => - ClkDiv26 <= '0'; - end case; - end if; - end if; - end process; - ----------------------------------------------------------------------------- - -- Provides the EnableRX signal, at ~ 155 KHz - ----------------------------------------------------------------------------- - DivClk10 : process(SysClk,Reset,Clkdiv26) - constant CntOne : unsigned(3 downto 0) := "0001"; - variable Cnt10 : unsigned(3 downto 0); - begin - if Rising_Edge(SysClk) then - if Reset = '0' then - Cnt10 := "0000"; - tmpEnRX <= '0'; - elsif ClkDiv26 = '1' then - Cnt10 := Cnt10 + CntOne; - end if; - case Cnt10 is - when "1010" => - tmpEnRX <= '1'; - Cnt10 := "0000"; - when others => - tmpEnRX <= '0'; - end case; - end if; - end process; - ----------------------------------------------------------------------------- - -- Provides the EnableTX signal, at 9.6 KHz - ----------------------------------------------------------------------------- - DivClk16 : process(SysClk,Reset,tmpEnRX) - constant CntOne : unsigned(4 downto 0) := "00001"; - variable Cnt16 : unsigned(4 downto 0); - begin - if Rising_Edge(SysClk) then - if Reset = '0' then - Cnt16 := "00000"; - tmpEnTX <= '0'; - elsif tmpEnRX = '1' then - Cnt16 := Cnt16 + CntOne; - end if; - case Cnt16 is - when "01111" => - tmpEnTX <= '1'; - Cnt16 := Cnt16 + CntOne; - when "10001" => - Cnt16 := "00000"; - tmpEnTX <= '0'; - when others => - tmpEnTX <= '0'; - end case; - end if; - end process; - - EnableRX <= tmpEnRX; - EnableTX <= tmpEnTX; -end Behaviour; --==================== End of architecture =================== diff --git a/2004/n/fpga/src/portserie/uart/miniUART.vhd b/2004/n/fpga/src/portserie/uart/miniUART.vhd deleted file mode 100644 index 31a4840..0000000 --- a/2004/n/fpga/src/portserie/uart/miniUART.vhd +++ /dev/null @@ -1,205 +0,0 @@ ---===========================================================================-- --- --- S Y N T H E Z I A B L E miniUART C O R E --- --- www.OpenCores.Org - January 2000 --- This core adheres to the GNU public license --- --- Design units : miniUART core for the OCRP-1 --- --- File name : miniuart.vhd --- --- Purpose : Implements an miniUART device for communication purposes --- between the OR1K processor and the Host computer through --- an RS-232 communication protocol. --- --- Library : uart_lib.vhd --- --- Dependencies : IEEE.Std_Logic_1164 --- --- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC ---===========================================================================-- -------------------------------------------------------------------------------- --- Revision list --- Version Author Date Changes --- --- 0.1 Ovidiu Lupas 15 January 2000 New model --- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations --- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl --- the RSBusCtrl did not process all possible situations --- --- olupas@opencores.org -------------------------------------------------------------------------------- --- Description : The memory consists of a dual-port memory addressed by --- two counters (RdCnt & WrCnt). The third counter (StatCnt) --- sets the status signals and keeps a track of the data flow. -------------------------------------------------------------------------------- --- Entity for miniUART Unit - 9600 baudrate -- -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; -library work; - use work.UART_Def.all; - -entity miniUART is - port ( - SysClk : in Std_Logic; -- System Clock - Reset : in Std_Logic; -- Reset input - CS_N : in Std_Logic; - RD_N : in Std_Logic; - WR_N : in Std_Logic; - RxD : in Std_Logic; - TxD : out Std_Logic; - IntRx_N : out Std_Logic; -- Receive interrupt - IntTx_N : out Std_Logic; -- Transmit interrupt - Addr : in Std_Logic_Vector(1 downto 0); -- - DataIn : in Std_Logic_Vector(7 downto 0); -- - DataOut : out Std_Logic_Vector(7 downto 0)); -- -end entity; --================== End of entity ==============================-- -------------------------------------------------------------------------------- --- Architecture for miniUART Controller Unit -------------------------------------------------------------------------------- -architecture uart of miniUART is - ----------------------------------------------------------------------------- - -- Signals - ----------------------------------------------------------------------------- - signal RxData : Std_Logic_Vector(7 downto 0); -- - signal TxData : Std_Logic_Vector(7 downto 0); -- - signal CSReg : Std_Logic_Vector(7 downto 0); -- Ctrl & status register - -- CSReg detailed - -----------+--------+--------+--------+--------+--------+--------+--------+ - -- CSReg(7)|CSReg(6)|CSReg(5)|CSReg(4)|CSReg(3)|CSReg(2)|CSReg(1)|CSReg(0)| - -- Res | Res | Res | Res | UndRun | OvrRun | FErr | OErr | - -----------+--------+--------+--------+--------+--------+--------+--------+ - signal EnabRx : Std_Logic; -- Enable RX unit - signal EnabTx : Std_Logic; -- Enable TX unit - signal DRdy : Std_Logic; -- Receive Data ready - signal TRegE : Std_Logic; -- Transmit register empty - signal TBufE : Std_Logic; -- Transmit buffer empty - signal FErr : Std_Logic; -- Frame error - signal OErr : Std_Logic; -- Output error - signal Read : Std_Logic; -- Read receive buffer - signal Load : Std_Logic; -- Load transmit buffer - ----------------------------------------------------------------------------- - -- Baud rate Generator - ----------------------------------------------------------------------------- - component ClkUnit is - port ( - SysClk : in Std_Logic; -- System Clock - EnableRX : out Std_Logic; -- Control signal - EnableTX : out Std_Logic; -- Control signal - Reset : in Std_Logic); -- Reset input - end component; - ----------------------------------------------------------------------------- - -- Receive Unit - ----------------------------------------------------------------------------- - component RxUnit is - port ( - Clk : in Std_Logic; -- Clock signal - Reset : in Std_Logic; -- Reset input - Enable : in Std_Logic; -- Enable input - RxD : in Std_Logic; -- RS-232 data input - RD : in Std_Logic; -- Read data signal - FErr : out Std_Logic; -- Status signal - OErr : out Std_Logic; -- Status signal - DRdy : out Std_Logic; -- Status signal - DataIn : out Std_Logic_Vector(7 downto 0)); - end component; - ----------------------------------------------------------------------------- - -- Transmitter Unit - ----------------------------------------------------------------------------- - component TxUnit is - port ( - Clk : in Std_Logic; -- Clock signal - Reset : in Std_Logic; -- Reset input - Enable : in Std_Logic; -- Enable input - Load : in Std_Logic; -- Load transmit data - TxD : out Std_Logic; -- RS-232 data output - TRegE : out Std_Logic; -- Tx register empty - TBufE : out Std_Logic; -- Tx buffer empty - DataO : in Std_Logic_Vector(7 downto 0)); - end component; -begin - ----------------------------------------------------------------------------- - -- Instantiation of internal components - ----------------------------------------------------------------------------- - ClkDiv : ClkUnit port map (SysClk,EnabRX,EnabTX,Reset); - TxDev : TxUnit port map (SysClk,Reset,EnabTX,Load,TxD,TRegE,TBufE,TxData); - RxDev : RxUnit port map (SysClk,Reset,EnabRX,RxD,Read,FErr,OErr,DRdy,RxData); - ----------------------------------------------------------------------------- - -- Implements the controller for Rx&Tx units - ----------------------------------------------------------------------------- - RSBusCtrl : process(SysClk,Reset,Read,Load) - variable StatM : Std_Logic_Vector(4 downto 0); - begin - if Rising_Edge(SysClk) then - if Reset = '0' then - StatM := "00000"; - IntTx_N <= '1'; - IntRx_N <= '1'; - CSReg <= "11110000"; - else - StatM(0) := DRdy; - StatM(1) := FErr; - StatM(2) := OErr; - StatM(3) := TBufE; - StatM(4) := TRegE; - end if; - case StatM is - when "00001" => - IntRx_N <= '0'; - CSReg(2) <= '1'; - when "10001" => - IntRx_N <= '0'; - CSReg(2) <= '1'; - when "01000" => - IntTx_N <= '0'; - when "11000" => - IntTx_N <= '0'; - CSReg(3) <= '1'; - when others => null; - end case; - - if Read = '1' then - CSReg(2) <= '0'; - IntRx_N <= '1'; - end if; - - if Load = '1' then - CSReg(3) <= '0'; - IntTx_N <= '1'; - end if; - end if; - end process; - ----------------------------------------------------------------------------- - -- Combinational section - ----------------------------------------------------------------------------- - process(SysClk) - begin - if (CS_N = '0' and RD_N = '0') then - Read <= '1'; - else Read <= '0'; - end if; - - if (CS_N = '0' and WR_N = '0') then - Load <= '1'; - else Load <= '0'; - end if; - - if Read = '0' then - DataOut <= "ZZZZZZZZ"; - elsif (Read = '1' and Addr = "00") then - DataOut <= RxData; - elsif (Read = '1' and Addr = "01") then - DataOut <= CSReg; - end if; - - if Load = '0' then - TxData <= "ZZZZZZZZ"; - elsif (Load = '1' and Addr = "00") then - TxData <= DataIn; - end if; - end process; -end uart; --===================== End of architecture ======================= - diff --git a/2004/n/fpga/src/portserie/uart/uart.npl b/2004/n/fpga/src/portserie/uart/uart.npl new file mode 100644 index 0000000..759173a --- /dev/null +++ b/2004/n/fpga/src/portserie/uart/uart.npl @@ -0,0 +1,26 @@ +JDF G +// Created by Project Navigator ver 1.0 +PROJECT uart +DESIGN uart +DEVFAM spartan2 +DEVFAMTIME 0 +DEVICE xc2s200 +DEVICETIME 0 +DEVPKG pq208 +DEVPKGTIME 0 +DEVSPEED -6 +DEVSPEEDTIME 0 +DEVTOPLEVELMODULETYPE HDL +TOPLEVELMODULETYPETIME 0 +DEVSYNTHESISTOOL XST (VHDL/Verilog) +SYNTHESISTOOLTIME 0 +DEVSIMULATOR Modelsim +SIMULATORTIME 0 +DEVGENERATEDSIMULATIONMODEL VHDL +GENERATEDSIMULATIONMODELTIME 0 +SOURCE rxcver.vhd +SOURCE txmit.vhd +SOURCE uart.vhd +STIMULUS uart_tb.vhd +[STRATEGY-LIST] +Normal=True diff --git a/2004/n/fpga/src/portserie/uart/uart_lib.vhd b/2004/n/fpga/src/portserie/uart/uart_lib.vhd deleted file mode 100644 index d458c64..0000000 --- a/2004/n/fpga/src/portserie/uart/uart_lib.vhd +++ /dev/null @@ -1,60 +0,0 @@ ---===========================================================================-- --- --- S Y N T H E Z I A B L E miniUART C O R E --- --- www.OpenCores.Org - January 2000 --- This core adheres to the GNU public license --- --- Design units : UART_Def --- --- File name : uart_lib.vhd --- --- Purpose : Implements an miniUART device for communication purposes --- between the OR1K processor and the Host computer through --- an RS-232 communication protocol. --- --- Library : uart_lib.vhd --- --- Dependencies : IEEE.Std_Logic_1164 --- ---===========================================================================-- -------------------------------------------------------------------------------- --- Revision list --- Version Author Date Changes --- --- 0.1 Ovidiu Lupas 15 January 2000 New model --- olupas@opencores.org -------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --- package UART_Def --------------------------------------------------------------------------------- -library IEEE,STD; -use IEEE.Std_Logic_1164.all; -use IEEE.Numeric_Std.all; ---**-- -package UART_Def is - ----------------------------------------------------------------------------- - -- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB - -- Error message for unknowns (U, X, W, Z, -), converted to 0 - -- Verifies whether vector is too long (> 16 bits) - ----------------------------------------------------------------------------- - function ToInteger ( - Invector : in Unsigned(3 downto 0)) - return Integer; -end UART_Def; --==================== End of package header ======================-- -package body UART_Def is - function ToInteger ( - InVector : in Unsigned(3 downto 0)) - return Integer is - constant HeaderMsg : String := "To_Integer:"; - constant MsgSeverity : Severity_Level := Warning; - variable Value : Integer := 0; - begin - for i in 0 to 3 loop - if (InVector(i) = '1') then - Value := Value + (2**I); - end if; - end loop; - return Value; - end ToInteger; -end UART_Def; --================ End of package body ================ -- cgit v1.2.3