From 2ac3370482b0a39a687f42110287df6f7e914455 Mon Sep 17 00:00:00 2001 From: galmes Date: Mon, 1 Mar 2004 21:04:01 +0000 Subject: Ajout des fichiers des bascules pour la gestion des interruptions. --- 2004/n/fpga/src/bascule/bascule.vhd | 53 +++++++++++++++++++++++++++ 2004/n/fpga/src/bascule/bch_bascule.vhd | 63 +++++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+) create mode 100644 2004/n/fpga/src/bascule/bascule.vhd create mode 100644 2004/n/fpga/src/bascule/bch_bascule.vhd diff --git a/2004/n/fpga/src/bascule/bascule.vhd b/2004/n/fpga/src/bascule/bascule.vhd new file mode 100644 index 0000000..e3511ee --- /dev/null +++ b/2004/n/fpga/src/bascule/bascule.vhd @@ -0,0 +1,53 @@ +-- bascule.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Bascule 8 bits avec signal de détection des changements. + +-- Remarque : +-- masque : si bit à 1 => on détecte l'interruption. +-- si bit à 0 => on détecte pas l'interruption. + + +library ieee; +use ieee.std_logic_1164.all; +--use ieee.std_logic_arith.all; +--use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity bascule is + port ( + clk : in std_logic; + rst : in std_logic; + data_in : in T_DATA; + data_out : out T_DATA; + it_detected : out std_logic + ); +end entity; + +architecture RTL of bascule is +begin + -- process séquentiel + process (rst, clk) + begin + if (rst = '1') then + -- ne pas déclencher d'it après rst. + data_out <= x"00"; + it_detected <= '0'; + elsif (clk'event and clk = '1') then + if (data_in(0) = '1') then data_out(0) <= '1'; end if; + if (data_in(1) = '1') then data_out(1) <= '1'; end if; + if (data_in(2) = '1') then data_out(2) <= '1'; end if; + if (data_in(3) = '1') then data_out(3) <= '1'; end if; + if (data_in(4) = '1') then data_out(4) <= '1'; end if; + if (data_in(5) = '1') then data_out(5) <= '1'; end if; + if (data_in(6) = '1') then data_out(6) <= '1'; end if; + if (data_in(7) = '1') then data_out(7) <= '1'; end if; + -- Détection des interruptions. + if (data_in /= x"00") then it_detected <= '1'; end if; + end if; + end process; + +end RTL; diff --git a/2004/n/fpga/src/bascule/bch_bascule.vhd b/2004/n/fpga/src/bascule/bch_bascule.vhd new file mode 100644 index 0000000..6fac989 --- /dev/null +++ b/2004/n/fpga/src/bascule/bch_bascule.vhd @@ -0,0 +1,63 @@ +-- bch_bascule.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Test de bascule. + +library ieee; +use ieee.std_logic_1164.all; +--use ieee.std_logic_arith.all; +--use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity bch_bascule is +end bch_bascule; + +architecture sim1 of bch_bascule is + + component bascule + port ( + clk : in std_logic; + rst : in std_logic; + data_in : in T_DATA; + data_out : out T_DATA; + it_detected : out std_logic + ); + end component; + + -- définiton des signaux + signal clk : std_logic := '0'; + signal rst : std_logic; + signal data_in : T_DATA; + signal data_out : T_DATA; + signal it_detected : std_logic; + +begin + U1 : bascule port map ( + clk => clk, + rst => rst, + data_in => data_in, + data_out => data_out, + it_detected => it_detected + ); + + clk <= not clk after CK_PERIOD/2; + rst <= '1', + '0' after CK_PERIOD, + '1' after 5*CK_PERIOD, + '0' after 7*CK_PERIOD; + data_in <= x"02", + x"00" after 2*CK_PERIOD, + x"08" after 5*CK_PERIOD, + x"01" after 7*CK_PERIOD; + --x"03" after 5*CK_PERIOD; +end sim1; + +configuration cf1_bch_bascule of bch_bascule is + for sim1 + for all : bascule use entity work.bascule(RTL); end for; + end for; +end cf1_bch_bascule; + -- cgit v1.2.3