From 16cbbd83d43093a12fbb18f0287fda5c286c28a7 Mon Sep 17 00:00:00 2001 From: prot Date: Mon, 1 Mar 2004 16:16:05 +0000 Subject: Modif du txserie pour adaptiation a la fifo coregen // // // // a l'UART efrei --- 2004/n/fpga/src/portserie/fifo.vhd | 8 +-- 2004/n/fpga/src/portserie/fifodriver.vhd | 3 +- 2004/n/fpga/src/portserie/portserie.sws | 15 +++-- 2004/n/fpga/src/portserie/txserie.vhd | 112 +++++++++++++++---------------- 2004/n/fpga/src/registre/registre.vhd | 55 ++++++++------- 5 files changed, 98 insertions(+), 95 deletions(-) diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd index 9023596..7122c96 100644 --- a/2004/n/fpga/src/portserie/fifo.vhd +++ b/2004/n/fpga/src/portserie/fifo.vhd @@ -34,8 +34,8 @@ component fifodriver is ); end component; ---component fifoctlr_cc is -component fifobehav is +component fifoctlr_cc is +--component fifobehav is port (clock_in: IN std_logic; read_enable_in: IN std_logic; write_enable_in: IN std_logic; @@ -70,8 +70,8 @@ begin ---FIFO1:fifoctlr_cc -FIFO1:fifobehav +FIFO1:fifoctlr_cc +--FIFO1:fifobehav port map( clock_in=>clock_fifo, read_enable_in=>read_enable, diff --git a/2004/n/fpga/src/portserie/fifodriver.vhd b/2004/n/fpga/src/portserie/fifodriver.vhd index 9084d51..f3f1d1b 100644 --- a/2004/n/fpga/src/portserie/fifodriver.vhd +++ b/2004/n/fpga/src/portserie/fifodriver.vhd @@ -36,7 +36,7 @@ begin -- writeflag<='1'; -- end if; -- end process; --- + -- process(readreq) -- begin -- if (readreq'event and readreq='1') then @@ -88,3 +88,4 @@ end rtl; + diff --git a/2004/n/fpga/src/portserie/portserie.sws b/2004/n/fpga/src/portserie/portserie.sws index e528e6d..e7939dc 100644 --- a/2004/n/fpga/src/portserie/portserie.sws +++ b/2004/n/fpga/src/portserie/portserie.sws @@ -148,11 +148,6 @@ [options] [] [] - [file] - name = fifo/fifobehav.vhd - [options] - [] - [] [file] name = fifo.vhd [options] @@ -178,6 +173,16 @@ [options] [] [] + [file] + name = fifo/fifobehav.vhd + [options] + [] + [] + [file] + name = txmit.vhd + [options] + [] + [] [] # End description of library portserie # Begin various workspace properties diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd index 48872cd..ee76e52 100644 --- a/2004/n/fpga/src/portserie/txserie.vhd +++ b/2004/n/fpga/src/portserie/txserie.vhd @@ -37,31 +37,26 @@ use ieee.std_logic_unsigned.all; use work.nono_const.all; entity txserie is - generic ( - -- adresses des différents registres du module. - A_DATA : T_ADDRESS ; - A_CONFIG : T_ADDRESS ; - A_FLAG : T_ADDRESS - -- si autre choses à déclarer... - ); port ( rst : in std_logic; clk : in std_logic; rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA; - bus_address : in T_ADDRESS; masterck: in std_logic; txout: out std_logic; minIRQ: out std_logic + + csData : in std_logic; + csConfig : in std_logic; + csFlag : in std_logic; ); end txserie; architecture rtl of txserie is component regIO - generic(adr : T_ADDRESS); port( - bus_address: in T_ADDRESS; + cs: in std_logic; bus_data: inout T_DATA; input: in T_DATA; output: out T_DATA; @@ -86,14 +81,17 @@ component fifo is end component; -component transmitter - port( - data_in: in T_DATA; - ck: in std_logic; - flag: out std_logic; - txout: out std_logic - ); -end component; +entity TXMIT is + port ( + MCLKX16 : in std_logic; + WRITE : in std_logic; + RESET : in std_logic; + DATA : in std_logic_vector(7 downto 0); + + TX : out std_logic; + TXRDY : out std_logic + ); +end TXMIT; component clockgene port( @@ -114,61 +112,66 @@ end component; signal fifoEmpty: std_logic; signal fifoFull: std_logic; ---signal fifoLI1: std_logic; ---signal fifoLI0: std_logic; +signal fifoLI1: std_logic; +signal fifoLI0: std_logic; --signal BdR1: std_logic; --signal BdR0: std_logic; -signal purge: std_logic:='0'; +signal fifopurge: std_logic:='0'; +signal fifoflags: std_logic_vector(5 downto 0); +signal fifockin: std_logic; +signal fifockout: std_logic; + signal txck: std_logic; signal confreg: T_DATA; -signal flagreg: T_DATA; -signal interflag: std_logic_vector(5 downto 0); -signal datareg: T_DATA; +signal flagreg: T_DATA:="00000000"; signal inter_data: T_DATA; -signal txempty: std_logic:='1'; -signal csFifo: std_logic; -signal fifockin: std_logic; -signal fifockout: std_logic; +signal txready: std_logic:='1'; begin FIFO1: fifo port map( data_in=>bus_data, data_out=>inter_data, - ck=>masterck, ck_in=>fifockin, ck_out=>fifockout, - flags=>interflag(5 downto 0), - purge=>confreg(3) + purge=>fifopurge ); -flagreg(5 downto 0)<=interflag; +fifockin<=csData and clk and not rw; +fifockout<=txready and not fifoempty +fifopurge<=confreg(3) or rst; + +flagreg(0)<=fifoLI1; +flagreg(1)<=fifoLI0; +flagreg(2)<=fifoAFull; +flagreg(3)<=fifoAEmpty; +flagreg(4)<=fifoFull; +flagreg(5)<=fifoEmpty; -fifockin<=csFifo and clk and not rw; -fifockout<=txempty and not fifoempty -; -- à vérifier !!! Cette ligne est valable pour txempty=1 quand le tx est vide +minirq<=fifoAFull and confreg(2) --fifo almost full AND Int/En -TX1 : transmitter +TX1 : TXMIT port map( - data_in=>inter_data, - ck=>txck, - flag=>txempty, - txout=>txout + MCLKX16=>txck, + WRITE=>'1', + RESET => rst, + DATA inter_data, + TX => txout, + TXRDY => txready ); +end TXMIT; + + +geneck<=confreg(4) and masterck; -- On/Off et masterck CLOCK1 : clockgene port map( - ckin=>masterck, + ckin=geneck, ckout=>txck, - param=>"11" --confreg(1 downto 0) + param=>confreg(1 downto 0) ); - ---geneck<='1'; --confreg(4) and masterck; -- On/Off et masterck -fifofull<=interflag(4); -fifoEmpty<=interflag(5); - -- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) RCONF : regIO generic map(adr=>A_CONFIG) @@ -180,7 +183,7 @@ RCONF : regIO rw=>rw, load=>'0', ck=>clk, - rst=>'0' + rst=>rst ); -- Flag : (x ! x ! Empty ! Full/Int ! FLI3 ! FLI2 ! FLI1 ! FLI0) @@ -194,19 +197,9 @@ RFLAG : regIO rw=>rw, load=>'1', ck=>clk, - rst=>'0' + rst=>rst ); --- la sortie intout est active si la pile est pleine ET si le bit de conf est --- activé -minIRQ<=flagreg(4) and confreg(2); -- IntEn et fifoFull - -DECOD : decoder - generic map(adr=>A_DATA) - port map( - bus_address=>bus_address, - cs=>csFifo - ); end rtl; @@ -214,3 +207,4 @@ end rtl; + diff --git a/2004/n/fpga/src/registre/registre.vhd b/2004/n/fpga/src/registre/registre.vhd index e0445fb..675eb83 100644 --- a/2004/n/fpga/src/registre/registre.vhd +++ b/2004/n/fpga/src/registre/registre.vhd @@ -30,7 +30,7 @@ use ieee.std_logic_unsigned.all; use work.nono_const.all; entity regIO is - generic(adr : T_ADDRESS); + generic(adr : T_ADDRESS := "0000000001"); port( bus_data: inout T_DATA; bus_address: in T_ADDRESS; @@ -48,37 +48,40 @@ architecture rtl of regIO is signal REG : T_DATA :=(others => '0'); begin - p_w:process(ck,load,input,rst) - begin - if(ck='1') then - if(bus_address=adr) then - if(rw='0') then - if(load='0') then - REG<=bus_data; - end if; - else -- RW=1 : la CM lit => on écrit sur le bus - bus_data<=REG; - end if; - else - bus_data<=(others => 'Z'); - end if; - else - bus_data<=(others => 'Z'); + p_w:process(ck,rst,load,input) + begin + + if( rst = '1') then + REG <= (others => '0'); + bus_data <= (others => 'Z'); + + elsif(ck'event and ck='1') then + if(bus_address=adr) then + if(rw='0' and load='0') then + REG<=bus_data; + bus_data <= (others => 'Z'); + elsif(rw='0' and load='1') then + bus_data <= (others => 'Z'); + elsif(rw='1') then -- RW=1 : la CM lit => on écrit sur le bus + bus_data<=REG; + end if; + else + bus_data <= (others => 'Z'); + end if; end if; + +-- si la clock est à 0, alors le bus est forcément en Z + if(ck='0') then + bus_data <= (others => 'Z'); + end if; -- chargement : prioritaire sur l'écriture via le bus if(load='1' and not(ck='1' and rw='1')) then REG<=input; end if; - --- reset : prioritaire sur tout - if(rst'event and rst='1') then - REG<=(others => '0'); - bus_data<=(others => 'Z'); - end if; - - end process p_w; - + end process p_w; + + -- p_load : process(load,input) -- begin -- if(load='1') then -- cgit v1.2.3