From e5a0856106ec36ee2112429dea23ff1ee456e6e8 Mon Sep 17 00:00:00 2001 From: prot Date: Sat, 28 Feb 2004 12:33:16 +0000 Subject: . --- 2004/n/fpga/src/adaptisa/adaptisa.sws | 157 ++++++++++++++++++++++++++++ 2004/n/fpga/src/adaptisa/adaptisa.vhd | 42 ++++++++ 2004/n/fpga/src/adaptisa/bch_adaptisa.vhd | 48 +++++++++ 2004/n/fpga/src/fifo/transmit.sws | 167 ++++++++++++++++++++++++++++++ 4 files changed, 414 insertions(+) create mode 100644 2004/n/fpga/src/adaptisa/adaptisa.sws create mode 100644 2004/n/fpga/src/adaptisa/adaptisa.vhd create mode 100644 2004/n/fpga/src/adaptisa/bch_adaptisa.vhd create mode 100644 2004/n/fpga/src/fifo/transmit.sws (limited to '2004') diff --git a/2004/n/fpga/src/adaptisa/adaptisa.sws b/2004/n/fpga/src/adaptisa/adaptisa.sws new file mode 100644 index 0000000..c75360b --- /dev/null +++ b/2004/n/fpga/src/adaptisa/adaptisa.sws @@ -0,0 +1,157 @@ +# +# This file has been automatically generated by the Symphony EDA IDE +# Please do NOT modify this file manually. If you do, do it with +# extreme care. This file represents your project settings. Corrupting +# this file can render this file useless!!! +# +# Begin version identification section +[version] + version = 1 +[] +# Begin libraries section (used by all tools) +[libraries] + ieee = $SYMPHONYEDA/lib/ieee/ieee.sym + adaptisa = adaptisa.sym +[] +# End of libraries section + [options] + [booloption] + name = -strict + value = 0 + invert = 0 + [] + [booloption] + name = -s + value = 0 + invert = 0 + [] + [stringoption] + name = -breakon + value = FAILURE + [] + [stringoption] + name = -stdin + value = "" + [] + [stringoption] + name = -stdout + value = "" + [] + [stringoption] + name = -coverage + value = "" + [] + [multistringoption] + name = -nowarn + [] + [multistringoption] + name = -noaccel + [] + [multistringoption] + name = -sdftyp + [] + [multistringoption] + name = -sdfmin + [] + [multistringoption] + name = -sdfmax + [] + [] +# Begin description of library ieee +[library] + name = ieee + [options] + [booloption] + name = -87 + value = 0 + invert = 0 + [] + [booloption] + name = -x + value = 0 + invert = 0 + [] + [booloption] + name = -s + value = 1 + invert = 0 + [] + [booloption] + name = -strict + value = 0 + invert = 0 + [] + [intoption] + name = -maxerrors + value = 10 + [] + [booloption] + name = -autoorder + value = 1 + invert = 0 + [] + [] +[] +# End description of library ieee +# Begin description of library adaptisa +[library] + name = adaptisa + toplevel = bch_modele + [options] + [booloption] + name = -87 + value = 0 + invert = 0 + [] + [booloption] + name = -x + value = 0 + invert = 0 + [] + [booloption] + name = -s + value = 1 + invert = 0 + [] + [booloption] + name = -strict + value = 0 + invert = 0 + [] + [intoption] + name = -maxerrors + value = 10 + [] + [booloption] + name = -autoorder + value = 1 + invert = 0 + [] + [] + [file] + name = ../modele/isa_const.vhd + [options] + [] + [] + [file] + name = ../modele/nono_const.vhd + [options] + [] + [] + [file] + name = adaptisa.vhd + [options] + [] + [] + [file] + name = bch_adaptisa.vhd + [options] + [] + [] +[] +# End description of library adaptisa +# Begin various workspace properties +[properties] + work =adaptisa +[] +# End workspace properties diff --git a/2004/n/fpga/src/adaptisa/adaptisa.vhd b/2004/n/fpga/src/adaptisa/adaptisa.vhd new file mode 100644 index 0000000..a88ee64 --- /dev/null +++ b/2004/n/fpga/src/adaptisa/adaptisa.vhd @@ -0,0 +1,42 @@ +-- modele.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Fichier modèle pour la déclaration de module. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.nono_const.all; +use work.isa_const.all; + +entity adaptisa is + generic(A_GENERAL : T_ADDRESS_ISA); + port ( + bus_address_ext : in T_ADDRESS_ISA; + bus_address_in : out T_ADDRESS + ); +end entity; + +architecture rtl of adaptisa is +signal net_adr : std_logic_vector((NB_BIT_ADDRESS_ISA - NB_BIT_ADDRESS - 1) downto 0); +signal net_adr_ref : std_logic_vector((NB_BIT_ADDRESS_ISA - NB_BIT_ADDRESS - 1) downto 0); +begin + net_adr <= bus_address_ext((NB_BIT_ADDRESS_ISA - 1) downto NB_BIT_ADDRESS); + net_adr_ref <= A_GENERAL((NB_BIT_ADDRESS_ISA - 1) downto NB_BIT_ADDRESS); + + bus_address_in <= bus_address_ext((NB_BIT_ADDRESS-1) downto 0) when (net_adr = net_adr_ref) else (others => '0'); + + +-- process(net_adr) +-- begin +-- if (net_adr = net_adr_ref) then +-- bus_address_in <= bus_address_ext((NB_BIT_ADDRESS-1) downto 0); +-- else +-- bus_address_in <= (others => '0'); +-- end if; +-- end process; +end rtl; + + diff --git a/2004/n/fpga/src/adaptisa/bch_adaptisa.vhd b/2004/n/fpga/src/adaptisa/bch_adaptisa.vhd new file mode 100644 index 0000000..a9ecb24 --- /dev/null +++ b/2004/n/fpga/src/adaptisa/bch_adaptisa.vhd @@ -0,0 +1,48 @@ +-- modele.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Fichier modèle pour la déclaration de module. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.nono_const.all; +use work.isa_const.all; + + +entity bch_modele is +end bch_modele; + +architecture sim1 of bch_modele is + component adaptisa + generic(A_GENERAL:T_ADDRESS_ISA); + port ( + bus_address_ext : in T_ADDRESS_ISA; + bus_address_in : out T_ADDRESS + ); + end component; + + signal bus_address : T_ADDRESS_ISA:="00101000010000100001"; + +begin + U1 : adaptisa + generic map (A_GENERAL=>"00001000010000100001") + port map ( + bus_address_ext=>bus_address, + bus_address_in=>open + ); + + bus_address <= "00001000010000100001" after 50 ns, + "00101000010000000000" after 100 ns, + "00001000010000000000" after 150 ns; +end sim1; + +configuration cf1_bch_modele of bch_modele is + for sim1 + for all : adaptisa use entity work.adaptisa(rtl); end for; + end for; +end cf1_bch_modele; + + diff --git a/2004/n/fpga/src/fifo/transmit.sws b/2004/n/fpga/src/fifo/transmit.sws new file mode 100644 index 0000000..d91b309 --- /dev/null +++ b/2004/n/fpga/src/fifo/transmit.sws @@ -0,0 +1,167 @@ +# +# This file has been automatically generated by the Symphony EDA IDE +# Please do NOT modify this file manually. If you do, do it with +# extreme care. This file represents your project settings. Corrupting +# this file can render this file useless!!! +# +# Begin version identification section +[version] + version = 1 +[] +# Begin libraries section (used by all tools) +[libraries] + ieee = $SYMPHONYEDA/lib/ieee/ieee.sym + transmit = transmit.sym +[] +# End of libraries section + [options] + [booloption] + name = -strict + value = 0 + invert = 0 + [] + [booloption] + name = -s + value = 0 + invert = 0 + [] + [stringoption] + name = -breakon + value = FAILURE + [] + [stringoption] + name = -stdin + value = "" + [] + [stringoption] + name = -stdout + value = "" + [] + [stringoption] + name = -coverage + value = "" + [] + [multistringoption] + name = -nowarn + [] + [multistringoption] + name = -noaccel + [] + [multistringoption] + name = -sdftyp + [] + [multistringoption] + name = -sdfmin + [] + [multistringoption] + name = -sdfmax + [] + [] +# Begin description of library ieee +[library] + name = ieee + [options] + [booloption] + name = -87 + value = 0 + invert = 0 + [] + [booloption] + name = -x + value = 0 + invert = 0 + [] + [booloption] + name = -s + value = 1 + invert = 0 + [] + [booloption] + name = -strict + value = 0 + invert = 0 + [] + [intoption] + name = -maxerrors + value = 10 + [] + [booloption] + name = -autoorder + value = 1 + invert = 0 + [] + [] +[] +# End description of library ieee +# Begin description of library transmit +[library] + name = transmit + toplevel = uarttest + [options] + [booloption] + name = -87 + value = 0 + invert = 0 + [] + [booloption] + name = -x + value = 0 + invert = 0 + [] + [booloption] + name = -s + value = 1 + invert = 0 + [] + [booloption] + name = -strict + value = 0 + invert = 0 + [] + [intoption] + name = -maxerrors + value = 10 + [] + [booloption] + name = -autoorder + value = 1 + invert = 0 + [] + [] + [file] + name = ../portserie/uart_lib.vhd + [options] + [] + [] + [file] + name = ../portserie/RxUnit.vhd + [options] + [] + [] + [file] + name = ../portserie/TxUnit.vhd + [options] + [] + [] + [file] + name = ../portserie/clkUnit.vhd + [options] + [] + [] + [file] + name = ../portserie/miniUART.vhd + [options] + [] + [] + [file] + name = ../portserie/UARTtest.vhd + [options] + [] + [] +[] +# End description of library transmit +# Begin various workspace properties +[properties] + work =transmit +[] +# End workspace properties -- cgit v1.2.3