From 99294453118e8d992716ab5a63b1bd1114bb74ec Mon Sep 17 00:00:00 2001 From: prot Date: Wed, 5 May 2004 07:10:46 +0000 Subject: *** empty log message *** --- 2004/n/mic799/half_dup.asm | 182 +++++++++++++++++++++++ 2004/n/mic799/p16c5x.inc | 224 ++++++++++++++++++++++++++++ 2004/n/mic799/p16f876.inc | 359 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 765 insertions(+) create mode 100644 2004/n/mic799/half_dup.asm create mode 100644 2004/n/mic799/p16c5x.inc create mode 100644 2004/n/mic799/p16f876.inc (limited to '2004') diff --git a/2004/n/mic799/half_dup.asm b/2004/n/mic799/half_dup.asm new file mode 100644 index 0000000..4abac8e --- /dev/null +++ b/2004/n/mic799/half_dup.asm @@ -0,0 +1,182 @@ + LIST P = 16C54, n = 66 +; +;****************************************************************************** +; RS-232 Communication With PIC16C54 +; +; Half Duplex Asynchronous Communication +; +; This program has been tested at Bauds from 1200 to 19200 Baud +; ( @ 8,16,20 Mhz CLKIN ) +; +; As a test, this program will echo back the data that has been +; received. +; +; Program: HALF_DUP.ASM +; Revision Date: +; 1-13-97 Compatibility with MPASMWIN 1.40 +; +;****************************************************************************** +; + INCLUDE + +PIC54 equ 1FFH ; Define Reset Vector +Same equ 1 +MSB equ 7 + +;***************** Communication Parameters ************************** +; +X_MODE equ 1 ; If ( X_MODE==1) Then transmit LSB first +; if ( X_MODE==0) Then transmit MSB first ( CODEC like ) +R_MODE equ 1 ; If ( R_MODE==1) Then receive LSB first +; if ( X_MODE==0) Then receive MSB first ( CODEC like ) +X_Nbit equ 1 ; if (X_Nbit==1) # of data bits ( Transmission ) is 8 else 7 +R_Nbit equ 1 ; if (R_Nbit==1) # of data bits ( Reception ) is 8 else 7 +; +Sbit2 equ 0 ; if Sbit2 = 0 then 1 Stop Bit else 2 Stop Bits +; +;************************************************************************* +X_flag equ PA0 ; Bit 5 of F3 ( PA0 ) +R_flag equ PA1 ; Bit 6 of F3 ( PA1 ) +; +DX equ 0 ; Transmit Pin ( Bit 0 of Port A ) +DR equ 1 ; Reciive Pin ( Bit 1 of Port A ) +; +; +BAUD_1 equ .68 ; 3+3X = CLKOUT/Baud +BAUD_2 equ .67 ; 6+3X = CLKOUT/Baud +BAUD_3 equ .34 ; 3+3X = 0.5*CLKOUT/Baud +BAUD_4 equ .86 ; 3+3X = 1.25*CLKOUT/Baud +BAUD_X equ .66 ; 11+3X = CLKOUT/Baud +BAUD_Y equ .66 ; 9 +3X = CLKOUT/Baud +; +;************************ Data RAM Assignments ********************** +; + ORG 08H ; Dummy Origin +; +RcvReg RES 1 ; Data received +XmtReg RES 1 ; Data to be transmitted +Count RES 1 ; Counter for #of Bits Transmitted +DlyCnt RES 1 +;*********************************************************************** +; + ORG 0 +; +Talk clrf RcvReg ; Clear all bits of RcvReg + btfsc PORTA,DR ; check for a Start Bit + goto User ; delay for 104/2 uS + call Delay4 ; delay for 104+104/4 +;*************************************************************** +; Receiver +; +Rcvr + IF R_Nbit + movlw 8 ; 8 Data bits + ELSE + movlw 7 ; 7 data bits + ENDIF +; + movwf Count +R_next bcf STATUS,C + IF R_MODE + rrf RcvReg,Same ; to set if MSB first or LSB first + ELSE + rlf RcvReg,Same + ENDIF + btfsc PORTA,DR +; + IF R_MODE + IF R_Nbit + bsf RcvReg,MSB ; Conditional Assembly + ELSE + bsf RcvReg,MSB-1 + ENDIF + ELSE + bsf RcvReg,LSB + ENDIF +; + call DelayY + decfsz Count,Same + goto R_next +;**************************************************** +R_over movf RcvReg,0 ; Send back What is Just Received + movwf XmtReg +;**************************************************** +; Transmitter +; +Xmtr + IF X_Nbit + movlw 8 + ELSE + movlw 7 + ENDIF + movwf Count +; + IF X_MODE + ELSE + IF X_Nbit + ELSE + rlf XmtReg,Same + ENDIF + ENDIF +; + bcf PORTA,DX ; Send Start Bit + call Delay1 +X_next bcf STATUS,C +; + IF X_MODE + rrf XmtReg,Same ; Conditional Assembly + ELSE ; to set if MSB first or LSB first + rlf XmtReg,Same + ENDIF +; + btfsc STATUS,C + bsf PORTA,DX + btfss STATUS,C + bcf PORTA,DX + call DelayX + decfsz Count,Same + goto X_next + bsf PORTA,DX ; Send Stop Bit + call Delay1 +; + IF Sbit2 + bsf PORTA,DX + call Delay1 + ENDIF +; + goto Talk ; Back To Reception & Transmision +; +; End of Transmission +; +DelayY movlw BAUD_Y + goto save +DelayX movlw BAUD_X + goto save +Delay4 movlw BAUD_4 + goto save +Delay1 movlw BAUD_1 ; 104 uS for 9600 baud + goto save +Delay2 movlw BAUD_2 +save movwf DlyCnt +redo_1 decfsz DlyCnt,Same + goto redo_1 + retlw 0 +; +main movlw 0EH ; Bit 0 of Port A is Output + tris PORTA ; Set PORTA.0 as output ( DX ) + bsf PORTA,DR +; + goto Talk +; +; +User movlw BAUD_3 + movwf DlyCnt +redo_2 decfsz DlyCnt,Same + goto redo_2 + goto Talk ; Loop Until Start Bit Found +; +; + ORG PIC54 + goto main +; + END diff --git a/2004/n/mic799/p16c5x.inc b/2004/n/mic799/p16c5x.inc new file mode 100644 index 0000000..e243e1f --- /dev/null +++ b/2004/n/mic799/p16c5x.inc @@ -0,0 +1,224 @@ + LIST +; P16C5X.INC Standard Header File, Version 3.30 Microchip Technology, Inc. + NOLIST + +; This header file defines configurations, registers, and other useful bits of +; information for the 16C5X microcontrollers. These names are taken to match +; the data sheets as closely as possible. The microcontrollers included +; in this file are: + +; 16C52 +; 16C54 +; 16CR54 +; 16C54A +; 16CR54A +; 16C55 +; 16C56 +; 16C57 +; 16CR57A +; 16CR57B +; 16C58A +; 16CR58A + +; There is one group of symbols that is valid for all microcontrollers. +; Each microcontroller in this family also has its own section of special +; symbols. Note that the processor must be selected before this file is +; included. The processor may be selected the following ways: + +; 1. Command line switch: +; C:\ MPASM MYFILE.ASM /P16C54A +; 2. LIST directive in the source file +; LIST P=16C54A +; 3. Processor Type entry in the MPASM full-screen interface + +;========================================================================== +; +; Revision History +; +;========================================================================== + +;Rev: Date: Reason: + +;3.30 07/16/96 Aligned processors with MPASM v1.40 +;3.20 04/09/96 Added 16C54B, 16CR56B, 16C58B +;3.10 12/14/95 Added 16C52 +;3.01 11/29/95 Removed 16CR55 +;3.00 10/16/95 Added new processors for MPASM v1.30 +;2.04 07/26/95 Reformatted for readability +;2.03 06/21/95 Removed leading spaces + +;========================================================================== +; +; Generic Definitions +; +;========================================================================== + +W EQU H'0000' +F EQU H'0001' + +;----- Register Files ----------------------------------------------------- + +INDF EQU H'0000' +TMR0 EQU H'0001' +PCL EQU H'0002' +STATUS EQU H'0003' +FSR EQU H'0004' +PORTA EQU H'0005' +PORTB EQU H'0006' + +;----- STATUS Bits -------------------------------------------------------- + +PA2 EQU H'0007' +PA1 EQU H'0006' +PA0 EQU H'0005' +NOT_TO EQU H'0004' +NOT_PD EQU H'0003' +Z EQU H'0002' +DC EQU H'0001' +C EQU H'0000' + +;----- OPTION Bits -------------------------------------------------------- + +T0CS EQU H'0005' +T0SE EQU H'0004' +PSA EQU H'0003' +PS2 EQU H'0002' +PS1 EQU H'0001' +PS0 EQU H'0000' + +;========================================================================== +; +; Processor-dependent Definitions +; +;========================================================================== + + IFDEF __16C52 + __MAXRAM H'01F' + #define __CONFIG_2 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16C54 + __MAXRAM H'01F' + #define __CONFIG_0 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16CR54 + __MAXRAM H'01F' + #define __CONFIG_0 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16C54A + __MAXRAM H'01F' + #define __CONFIG_0 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16CR54A + __MAXRAM H'01F' + #define __CONFIG_1 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16C55 + ; Register Files +PORTC EQU H'0007' + __MAXRAM H'01F' + #define __CONFIG_0 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16C56 + __MAXRAM H'01F' + #define __CONFIG_0 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16C57 + ; Register Files +PORTC EQU H'0007' + __MAXRAM H'07F' + #define __CONFIG_0 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16CR57A + ; Register Files +PORTC EQU H'0007' + __MAXRAM H'07F' + #define __CONFIG_0 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16CR57B + ; Register Files +PORTC EQU H'0007' + __MAXRAM H'07F' + #define __CONFIG_1 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16C58A + __MAXRAM H'07F' + #define __CONFIG_0 + ENDIF + +;-------------------------------------------------------------------------- + + IFDEF __16CR58A + __MAXRAM H'07F' + #define __CONFIG_1 + ENDIF + +;========================================================================== +; +; Configuration Bits +; +;========================================================================== + + IFDEF __CONFIG_0 +_CP_ON EQU H'0FF7' +_CP_OFF EQU H'0FFF' +_WDT_ON EQU H'0FFF' +_WDT_OFF EQU H'0FFB' +_LP_OSC EQU H'0FFC' +_XT_OSC EQU H'0FFD' +_HS_OSC EQU H'0FFE' +_RC_OSC EQU H'0FFF' + #undefine __CONFIG_0 + ENDIF + + + IFDEF __CONFIG_1 +_CP_ON EQU H'0007' +_CP_OFF EQU H'0FFF' +_WDT_ON EQU H'0FFF' +_WDT_OFF EQU H'0FFB' +_LP_OSC EQU H'0FFC' +_XT_OSC EQU H'0FFD' +_HS_OSC EQU H'0FFE' +_RC_OSC EQU H'0FFF' + #undefine __CONFIG_1 + ENDIF + + IFDEF __CONFIG_2 +_CP_ON EQU H'0FF7' +_CP_OFF EQU H'0FFF' +_XT_OSC EQU H'0FFD' +_RC_OSC EQU H'0FFF' + #undefine __CONFIG_2 + ENDIF + + LIST diff --git a/2004/n/mic799/p16f876.inc b/2004/n/mic799/p16f876.inc new file mode 100644 index 0000000..dedd80d --- /dev/null +++ b/2004/n/mic799/p16f876.inc @@ -0,0 +1,359 @@ + LIST +; P16F876.INC Standard Header File, Version 1.00 Microchip Technology, Inc. + NOLIST + +; This header file defines configurations, registers, and other useful bits of +; information for the PIC16F876 microcontroller. These names are taken to match +; the data sheets as closely as possible. + +; Note that the processor must be selected before this file is +; included. The processor may be selected the following ways: + +; 1. Command line switch: +; C:\ MPASM MYFILE.ASM /PIC16F876 +; 2. LIST directive in the source file +; LIST P=PIC16F876 +; 3. Processor Type entry in the MPASM full-screen interface + +;========================================================================== +; +; Revision History +; +;========================================================================== + +;Rev: Date: Reason: + +;1.12 01/12/00 Changed some bit names, a register name, configuration bits +; to match datasheet (DS30292B) +;1.00 08/07/98 Initial Release + +;========================================================================== +; +; Verify Processor +; +;========================================================================== + + IFNDEF __16F876 + MESSG "Processor-header file mismatch. Verify selected processor." + ENDIF + +;========================================================================== +; +; Register Definitions +; +;========================================================================== + +W EQU H'0000' +F EQU H'0001' + +;----- Register Files------------------------------------------------------ + +INDF EQU H'0000' +TMR0 EQU H'0001' +PCL EQU H'0002' +STATUS EQU H'0003' +FSR EQU H'0004' +PORTA EQU H'0005' +PORTB EQU H'0006' +PORTC EQU H'0007' + +PCLATH EQU H'000A' +INTCON EQU H'000B' +PIR1 EQU H'000C' +PIR2 EQU H'000D' +TMR1L EQU H'000E' +TMR1H EQU H'000F' +T1CON EQU H'0010' +TMR2 EQU H'0011' +T2CON EQU H'0012' +SSPBUF EQU H'0013' +SSPCON EQU H'0014' +CCPR1L EQU H'0015' +CCPR1H EQU H'0016' +CCP1CON EQU H'0017' +RCSTA EQU H'0018' +TXREG EQU H'0019' +RCREG EQU H'001A' +CCPR2L EQU H'001B' +CCPR2H EQU H'001C' +CCP2CON EQU H'001D' +ADRESH EQU H'001E' +ADCON0 EQU H'001F' + +OPTION_REG EQU H'0081' +TRISA EQU H'0085' +TRISB EQU H'0086' +TRISC EQU H'0087' +PIE1 EQU H'008C' +PIE2 EQU H'008D' +PCON EQU H'008E' +SSPCON2 EQU H'0091' +PR2 EQU H'0092' +SSPADD EQU H'0093' +SSPSTAT EQU H'0094' +TXSTA EQU H'0098' +SPBRG EQU H'0099' +ADRESL EQU H'009E' +ADCON1 EQU H'009F' + +EEDATA EQU H'010C' +EEADR EQU H'010D' +EEDATH EQU H'010E' +EEADRH EQU H'010F' + +EECON1 EQU H'018C' +EECON2 EQU H'018D' + +;----- STATUS Bits -------------------------------------------------------- + +IRP EQU H'0007' +RP1 EQU H'0006' +RP0 EQU H'0005' +NOT_TO EQU H'0004' +NOT_PD EQU H'0003' +Z EQU H'0002' +DC EQU H'0001' +C EQU H'0000' + +;----- INTCON Bits -------------------------------------------------------- + +GIE EQU H'0007' +PEIE EQU H'0006' +T0IE EQU H'0005' +INTE EQU H'0004' +RBIE EQU H'0003' +T0IF EQU H'0002' +INTF EQU H'0001' +RBIF EQU H'0000' + +;----- PIR1 Bits ---------------------------------------------------------- + +ADIF EQU H'0006' +RCIF EQU H'0005' +TXIF EQU H'0004' +SSPIF EQU H'0003' +CCP1IF EQU H'0002' +TMR2IF EQU H'0001' +TMR1IF EQU H'0000' + +;----- PIR2 Bits ---------------------------------------------------------- + +EEIF EQU H'0004' +BCLIF EQU H'0003' +CCP2IF EQU H'0000' + +;----- T1CON Bits --------------------------------------------------------- + +T1CKPS1 EQU H'0005' +T1CKPS0 EQU H'0004' +T1OSCEN EQU H'0003' +NOT_T1SYNC EQU H'0002' +T1INSYNC EQU H'0002' ; Backward compatibility only +T1SYNC EQU H'0002' +TMR1CS EQU H'0001' +TMR1ON EQU H'0000' + +;----- T2CON Bits --------------------------------------------------------- + +TOUTPS3 EQU H'0006' +TOUTPS2 EQU H'0005' +TOUTPS1 EQU H'0004' +TOUTPS0 EQU H'0003' +TMR2ON EQU H'0002' +T2CKPS1 EQU H'0001' +T2CKPS0 EQU H'0000' + +;----- SSPCON Bits -------------------------------------------------------- + +WCOL EQU H'0007' +SSPOV EQU H'0006' +SSPEN EQU H'0005' +CKP EQU H'0004' +SSPM3 EQU H'0003' +SSPM2 EQU H'0002' +SSPM1 EQU H'0001' +SSPM0 EQU H'0000' + +;----- CCP1CON Bits ------------------------------------------------------- + +CCP1X EQU H'0005' +CCP1Y EQU H'0004' +CCP1M3 EQU H'0003' +CCP1M2 EQU H'0002' +CCP1M1 EQU H'0001' +CCP1M0 EQU H'0000' + +;----- RCSTA Bits --------------------------------------------------------- + +SPEN EQU H'0007' +RX9 EQU H'0006' +RC9 EQU H'0006' ; Backward compatibility only +NOT_RC8 EQU H'0006' ; Backward compatibility only +RC8_9 EQU H'0006' ; Backward compatibility only +SREN EQU H'0005' +CREN EQU H'0004' +ADDEN EQU H'0003' +FERR EQU H'0002' +OERR EQU H'0001' +RX9D EQU H'0000' +RCD8 EQU H'0000' ; Backward compatibility only + +;----- CCP2CON Bits ------------------------------------------------------- + +CCP2X EQU H'0005' +CCP2Y EQU H'0004' +CCP2M3 EQU H'0003' +CCP2M2 EQU H'0002' +CCP2M1 EQU H'0001' +CCP2M0 EQU H'0000' + +;----- ADCON0 Bits -------------------------------------------------------- + +ADCS1 EQU H'0007' +ADCS0 EQU H'0006' +CHS2 EQU H'0005' +CHS1 EQU H'0004' +CHS0 EQU H'0003' +GO EQU H'0002' +NOT_DONE EQU H'0002' +GO_DONE EQU H'0002' +ADON EQU H'0000' + +;----- OPTION_REG Bits ---------------------------------------------------- + +NOT_RBPU EQU H'0007' +INTEDG EQU H'0006' +T0CS EQU H'0005' +T0SE EQU H'0004' +PSA EQU H'0003' +PS2 EQU H'0002' +PS1 EQU H'0001' +PS0 EQU H'0000' + +;----- PIE1 Bits ---------------------------------------------------------- + +ADIE EQU H'0006' +RCIE EQU H'0005' +TXIE EQU H'0004' +SSPIE EQU H'0003' +CCP1IE EQU H'0002' +TMR2IE EQU H'0001' +TMR1IE EQU H'0000' + +;----- PIE2 Bits ---------------------------------------------------------- + +EEIE EQU H'0004' +BCLIE EQU H'0003' +CCP2IE EQU H'0000' + +;----- PCON Bits ---------------------------------------------------------- + +NOT_POR EQU H'0001' +NOT_BO EQU H'0000' +NOT_BOR EQU H'0000' + +;----- SSPCON2 Bits -------------------------------------------------------- + +GCEN EQU H'0007' +ACKSTAT EQU H'0006' +ACKDT EQU H'0005' +ACKEN EQU H'0004' +RCEN EQU H'0003' +PEN EQU H'0002' +RSEN EQU H'0001' +SEN EQU H'0000' + +;----- SSPSTAT Bits ------------------------------------------------------- + +SMP EQU H'0007' +CKE EQU H'0006' +D EQU H'0005' +I2C_DATA EQU H'0005' +NOT_A EQU H'0005' +NOT_ADDRESS EQU H'0005' +D_A EQU H'0005' +DATA_ADDRESS EQU H'0005' +P EQU H'0004' +I2C_STOP EQU H'0004' +S EQU H'0003' +I2C_START EQU H'0003' +R EQU H'0002' +I2C_READ EQU H'0002' +NOT_W EQU H'0002' +NOT_WRITE EQU H'0002' +R_W EQU H'0002' +READ_WRITE EQU H'0002' +UA EQU H'0001' +BF EQU H'0000' + +;----- TXSTA Bits --------------------------------------------------------- + +CSRC EQU H'0007' +TX9 EQU H'0006' +NOT_TX8 EQU H'0006' ; Backward compatibility only +TX8_9 EQU H'0006' ; Backward compatibility only +TXEN EQU H'0005' +SYNC EQU H'0004' +BRGH EQU H'0002' +TRMT EQU H'0001' +TX9D EQU H'0000' +TXD8 EQU H'0000' ; Backward compatibility only + +;----- ADCON1 Bits -------------------------------------------------------- + +ADFM EQU H'0007' +PCFG3 EQU H'0003' +PCFG2 EQU H'0002' +PCFG1 EQU H'0001' +PCFG0 EQU H'0000' + +;----- EECON1 Bits -------------------------------------------------------- + +EEPGD EQU H'0007' +WRERR EQU H'0003' +WREN EQU H'0002' +WR EQU H'0001' +RD EQU H'0000' + +;========================================================================== +; +; RAM Definition +; +;========================================================================== + + __MAXRAM H'1FF' + __BADRAM H'08'-H'09' + __BADRAM H'88'-H'89', H'8F'-H'90', H'95'-H'97', H'9A'-H'9D' + __BADRAM H'105', H'107'-H'109' + __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' + +;========================================================================== +; +; Configuration Bits +; +;========================================================================== + +_CP_ALL EQU H'0FCF' +_CP_HALF EQU H'1FDF' +_CP_UPPER_256 EQU H'2FEF' +_CP_OFF EQU H'3FFF' +_DEBUG_ON EQU H'37FF' +_DEBUG_OFF EQU H'3FFF' +_WRT_ENABLE_ON EQU H'3FFF' +_WRT_ENABLE_OFF EQU H'3DFF' +_CPD_ON EQU H'3EFF' +_CPD_OFF EQU H'3FFF' +_LVP_ON EQU H'3FFF' +_LVP_OFF EQU H'3F7F' +_BODEN_ON EQU H'3FFF' +_BODEN_OFF EQU H'3FBF' +_PWRTE_OFF EQU H'3FFF' +_PWRTE_ON EQU H'3FF7' +_WDT_ON EQU H'3FFF' +_WDT_OFF EQU H'3FFB' +_LP_OSC EQU H'3FFC' +_XT_OSC EQU H'3FFD' +_HS_OSC EQU H'3FFE' +_RC_OSC EQU H'3FFF' + + LIST -- cgit v1.2.3