From 8e39188d2a674e7cc3ab0639c62e3e680bbed8fe Mon Sep 17 00:00:00 2001 From: galmes Date: Tue, 30 Mar 2004 15:10:52 +0000 Subject: interrupt : Version Fonctionnelle testée sur carte (avec caméra intégrée). --- 2004/n/fpga/src/interrupt/interrupt.vhd | 12 ++++++------ 2004/n/fpga/src/or/or3.vhd | 17 ++++++++--------- 2004/n/fpga/src/or/or8.vhd | 29 +++++++++++------------------ 3 files changed, 25 insertions(+), 33 deletions(-) (limited to '2004') diff --git a/2004/n/fpga/src/interrupt/interrupt.vhd b/2004/n/fpga/src/interrupt/interrupt.vhd index 529e6d0..c94ca4c 100644 --- a/2004/n/fpga/src/interrupt/interrupt.vhd +++ b/2004/n/fpga/src/interrupt/interrupt.vhd @@ -34,12 +34,12 @@ architecture RTL of interrupt is -- Définition des composants utilisés. -- Ou à trois entrées. -component or3 is +component or3_nono is port ( - in1 : in std_logic; - in2 : in std_logic; - in3 : in std_logic; - or_out : out std_logic + or3_in1 : in std_logic; + or3_in2 : in std_logic; + or3_in3 : in std_logic; + or3_out : out std_logic ); end component; @@ -93,7 +93,7 @@ port map ( it_aux_bloc3 ); -IRQ_gen : or3 +IRQ_gen : or3_nono port map ( it_aux_bloc1, it_aux_bloc2, diff --git a/2004/n/fpga/src/or/or3.vhd b/2004/n/fpga/src/or/or3.vhd index 48ae2c8..b59a48e 100644 --- a/2004/n/fpga/src/or/or3.vhd +++ b/2004/n/fpga/src/or/or3.vhd @@ -12,18 +12,17 @@ use work.isa_const.all; use work.nono_const.all; -entity or3 is +entity or3_nono is port ( - in1 : in std_logic; - in2 : in std_logic; - in3 : in std_logic; - or_out : out std_logic + or3_in1 : in std_logic; + or3_in2 : in std_logic; + or3_in3 : in std_logic; + or3_out : out std_logic ); end entity; -architecture RTL of or3 is +architecture RTL of or3_nono is begin - - or_out <= '1' when (in1 = '1' or - in2 = '1' or in3 ='1') else '0'; + or3_out <= '1' when (or3_in1 = '1' or + or3_in2 = '1' or or3_in3 ='1') else '0'; end RTL; diff --git a/2004/n/fpga/src/or/or8.vhd b/2004/n/fpga/src/or/or8.vhd index ae0d159..85f2088 100644 --- a/2004/n/fpga/src/or/or8.vhd +++ b/2004/n/fpga/src/or/or8.vhd @@ -15,29 +15,22 @@ use work.nono_const.all; entity or8 is port ( - in0 : in std_logic; - in1 : in std_logic; - in2 : in std_logic; - in3 : in std_logic; - in4 : in std_logic; - in5 : in std_logic; - in6 : in std_logic; - in7 : in std_logic; - or_out : out std_logic + or8_in : in std_logic_vector (7 downto 0); + or8_out : out std_logic ); end entity; architecture RTL of or8 is begin - or_out <= '1' when - (in0 = '1' or - in1 = '1' or - in2 = '1' or - in3 = '1' or - in4 = '1' or - in5 = '1' or - in6 = '1' or - in7 = '1' + or8_out <= '1' when + (or8_in (0) = '1' or + or8_in (1) = '1' or + or8_in (2) = '1' or + or8_in (3) = '1' or + or8_in (4) = '1' or + or8_in (5) = '1' or + or8_in (6) = '1' or + or8_in (7) = '1' ) else '0'; end RTL; -- cgit v1.2.3