From 737a773308c58c99768b36d8facf355df6f2b14c Mon Sep 17 00:00:00 2001 From: prot Date: Tue, 24 Feb 2004 16:37:29 +0000 Subject: . --- 2004/n/fpga/src/portserie/fifo.vhd | 10 +++++++--- 2004/n/fpga/src/portserie/txserie.vhd | 15 ++++++++++----- 2 files changed, 17 insertions(+), 8 deletions(-) (limited to '2004') diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd index 04ff690..35ad154 100644 --- a/2004/n/fpga/src/portserie/fifo.vhd +++ b/2004/n/fpga/src/portserie/fifo.vhd @@ -5,9 +5,9 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; use work.nono_const.all; @@ -61,8 +61,10 @@ signal clock_fifo:std_logic; begin -- conversion de types : --data_in_s <= TO_STDLOGICVECTOR(unsigned(data_in),8); -data_out <= TO_UNSIGNED(CONV_INTEGER(data_out_s),8); -data_in_s <= conv_std_logic_vector(data_input); +--data_in_s <= conv_std_logic_vector(data_input); + +data_in_s <= conv_std_logic_vector(unsigned(data_input),data_input'length); +data_out <= conv_unsigned(CONV_INTEGER(data_out_s),8); FIFO1:fifoctlr_cc port map( @@ -93,3 +95,5 @@ end rtl; + + diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd index 11e0946..5995f9c 100644 --- a/2004/n/fpga/src/portserie/txserie.vhd +++ b/2004/n/fpga/src/portserie/txserie.vhd @@ -97,8 +97,8 @@ end component; component clockgene port( - ck_in: in std_logic; - ck_out: in std_logic; + ckin: in std_logic; + ckout: out std_logic; param: in std_logic_vector(1 downto 0) ); end component; @@ -128,6 +128,7 @@ signal busck: std_logic; --signal rst: std_logic; signal confreg: unsigned(7 downto 0); signal flagreg: unsigned(7 downto 0); +signal interflag: std_logic_vector(5 downto 0); signal datareg: unsigned(7 downto 0); signal inter_data: unsigned(7 downto 0); signal txempty: std_logic; @@ -143,9 +144,11 @@ FIFO1: fifo ck=>masterck, ck_in=>fifockin, ck_out=>fifockout, - flags=>flagreg(5 downto 0), + flags=>interflag(5 downto 0), purge=>confreg(3) ); + +flagreg(5 downto 0)<=conv_unsigned(CONV_INTEGER(interflag),8); fifockin<=csFifo and not rw and busck; fifockout<=txempty; -- ŕ vérifier !!! Cette ligne est valable pour @@ -161,8 +164,8 @@ TX1 : transmitter CLOCK1 : clockgene port map( - ck_in=>geneck, - ck_out=>txck, + ckin=>geneck, + ckout=>txck, param=>"11" --confreg(1 downto 0) ); @@ -218,3 +221,5 @@ end rtl; + + -- cgit v1.2.3