From 4ccfe616f851d0ea39d6fe5ac0d18a37e66af74b Mon Sep 17 00:00:00 2001 From: galmes Date: Mon, 23 Feb 2004 16:19:44 +0000 Subject: Améliorations de modele --- 2004/n/fpga/src/modele/bch_modele.vhd | 33 ++++++++++++++++++++------------- 2004/n/fpga/src/modele/modele.vhd | 7 ++----- 2004/n/fpga/src/modele/nono_const.vhd | 6 ++++-- 3 files changed, 26 insertions(+), 20 deletions(-) (limited to '2004') diff --git a/2004/n/fpga/src/modele/bch_modele.vhd b/2004/n/fpga/src/modele/bch_modele.vhd index 18bc9a7..eb062c5 100644 --- a/2004/n/fpga/src/modele/bch_modele.vhd +++ b/2004/n/fpga/src/modele/bch_modele.vhd @@ -19,17 +19,17 @@ architecture sim1 of bch_modele is component modele generic ( -- adresses des différents registres du module. - A_REG1 : T_ADDRESS := A_REG_IO_DIRECTION; - A_REG2 : T_ADDRESS := A_REG_IO_DATA; - A_REG3 : T_ADDRESS := A_REG_IO_INTERRUPT_MASK + A_REG1 : T_ADDRESS; + A_REG2 : T_ADDRESS; + A_REG3 : T_ADDRESS -- si autre choses à déclarer... ); port ( rst : in std_logic; clk : in std_logic; rw : in std_logic; -- read / write - bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0); - bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0) + bus_data : inout T_DATA; + bus_address : in T_ADDRESS ); end component; @@ -37,16 +37,23 @@ architecture sim1 of bch_modele is signal rst : std_logic; signal clk : std_logic := '0'; signal rw : std_logic; -- read / write - signal bus_data : unsigned ((NB_BIT_DATA - 1) downto 0); - signal bus_address : unsigned ((NB_BIT_ADDRESS - 1) downto 0); + signal bus_data : T_DATA; + signal bus_address : T_ADDRESS; begin - U1 : modele port map ( - rst => rst, - clk => clk, - rw => rw, - bus_data => bus_data, - bus_address => bus_address + U1 : modele + generic map ( + -- Définition des addresses. + A_REG1 => A_REG_IO_DIRECTION, + A_REG2 => A_REG_IO_DATA, + A_REG3 => A_REG_IO_INTERRUPT_MASK + ) + port map ( + rst => rst, + clk => clk, + rw => rw, + bus_data => bus_data, + bus_address => bus_address ); rst <= '1', '0' after CK_PERIOD; diff --git a/2004/n/fpga/src/modele/modele.vhd b/2004/n/fpga/src/modele/modele.vhd index c877df9..c4e9f38 100644 --- a/2004/n/fpga/src/modele/modele.vhd +++ b/2004/n/fpga/src/modele/modele.vhd @@ -21,12 +21,9 @@ entity modele is port ( rst : in std_logic; clk : in std_logic; - - -- XXX : savoir si read = 0 ou 1 !! rw : in std_logic; -- read (0) / write (1) - - bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0); - bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0) + bus_data : inout T_DATA; + bus_address : in T_ADDRESS ); end entity; diff --git a/2004/n/fpga/src/modele/nono_const.vhd b/2004/n/fpga/src/modele/nono_const.vhd index fc260e1..0afbace 100644 --- a/2004/n/fpga/src/modele/nono_const.vhd +++ b/2004/n/fpga/src/modele/nono_const.vhd @@ -29,8 +29,10 @@ package nono_const is constant NB_BIT_DATA : integer := 8; -- Définition de nouveaux types : T_ADDRESS et T_DATA - subtype T_ADDRESS is unsigned ((NB_BIT_ADDRESS - 1) downto 0); - subtype T_DATA is unsigned ((NB_BIT_DATA - 1) downto 0); + --subtype T_ADDRESS is unsigned ((NB_BIT_ADDRESS - 1) downto 0); + --subtype T_DATA is unsigned ((NB_BIT_DATA - 1) downto 0); + subtype T_ADDRESS is std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0); + subtype T_DATA is std_logic_vector ((NB_BIT_DATA - 1) downto 0); -- Les différentes banques d'adresses (4 x 256) -- Rq pour Pierre : ça va influer sur le bloc de gestion du bus -- cgit v1.2.3