From 2698ec1d2251323bdcc992295179c76b4686ab1e Mon Sep 17 00:00:00 2001 From: prot Date: Mon, 15 Mar 2004 00:01:41 +0000 Subject: Le clock gen qui gère maintenant les 4 baudrates --- 2004/n/fpga/src/portserie/clockgene/clockgene.npl | 25 ++++++++ 2004/n/fpga/src/portserie/clockgene/clockgene.vhd | 73 +++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 2004/n/fpga/src/portserie/clockgene/clockgene.npl create mode 100644 2004/n/fpga/src/portserie/clockgene/clockgene.vhd (limited to '2004') diff --git a/2004/n/fpga/src/portserie/clockgene/clockgene.npl b/2004/n/fpga/src/portserie/clockgene/clockgene.npl new file mode 100644 index 0000000..c7ab4ea --- /dev/null +++ b/2004/n/fpga/src/portserie/clockgene/clockgene.npl @@ -0,0 +1,25 @@ +JDF G +// Created by Project Navigator ver 1.0 +PROJECT clockgene +DESIGN clockgene +DEVFAM spartan2 +DEVFAMTIME 0 +DEVICE xc2s200 +DEVICETIME 0 +DEVPKG pq208 +DEVPKGTIME 0 +DEVSPEED -6 +DEVSPEEDTIME 0 +DEVTOPLEVELMODULETYPE HDL +TOPLEVELMODULETYPETIME 0 +DEVSYNTHESISTOOL XST (VHDL/Verilog) +SYNTHESISTOOLTIME 0 +DEVSIMULATOR Modelsim +SIMULATORTIME 0 +DEVGENERATEDSIMULATIONMODEL VHDL +GENERATEDSIMULATIONMODELTIME 0 +STIMULUS ..\portserie\bch_txserie.vhd +SOURCE ..\..\modele\nono_const.vhd +SOURCE ..\portserie\clockgene.vhd +[STRATEGY-LIST] +Normal=True diff --git a/2004/n/fpga/src/portserie/clockgene/clockgene.vhd b/2004/n/fpga/src/portserie/clockgene/clockgene.vhd new file mode 100644 index 0000000..b98a6b3 --- /dev/null +++ b/2004/n/fpga/src/portserie/clockgene/clockgene.vhd @@ -0,0 +1,73 @@ +-- clockgene.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre Prot +-- clock + +-- fréquence d'entrée : 30MHz +-- fréquence de sortie : 115kHz +-- diviseur = (freq d'entrée)/(frequ sortie) + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.nono_const.all; +-- pour la valeur de DIVIS_CK_SERIAL + +-- param : +-- 00 -> 9600 bauds +-- 01 -> 19200 bauds +-- 10 -> 57600 bauds +-- 11 -> 115200 bauds + +-- horloge de ref +entity clockgene is +port( + rst: in std_logic; + ckin: in std_logic; + ckout: out std_logic; + param: in std_logic_vector(1 downto 0) + ); +end clockgene; + + +architecture rtl of clockgene is +signal compteur:std_logic_vector(10 downto 0):=(others=>'0'); +signal div_param:integer; -- le diviseur paramétrable +signal clr:std_logic; + +begin + + clr<=rst; + + process(param,rst) + begin + case param is + when "00" => div_param <= (DIVIS_CK_SERIAL*12); -- 9600 * 12 =115200 + when "01" => div_param <= (DIVIS_CK_SERIAL*6); -- 19200 * 6 =115200 + when "10" => div_param <= (DIVIS_CK_SERIAL*2); -- 57600 * 2 =115200 + when "11" => div_param <= DIVIS_CK_SERIAL; -- 115200 * 1=115200 + when others => null; + end case; + end process; + +-- baudmax : génère la fréquence nécéssaire à du 115200 + baudmax:process(ckin,clr) + begin + if(clr='1') then + ckout<='0'; + compteur<=(others=>'0'); + elsif(ckin'event and ckin='1') then + if(compteur = div_param) then + ckout<='1'; + compteur<=(others=>'0'); + else + compteur <= compteur + 1; + ckout<='0'; + end if; + end if; + end process; +end rtl; + + -- cgit v1.2.3