From 872a5b43d413383e6a841910397417a084e9057f Mon Sep 17 00:00:00 2001 From: prot Date: Thu, 26 Feb 2004 21:58:25 +0000 Subject: On avance on avance... --- 2004/n/fpga/src/portserie/bch_txserie.vhd | 72 +++++++++++++++++++++++---- 2004/n/fpga/src/portserie/decoder.vhd | 5 +- 2004/n/fpga/src/portserie/fifo.vhd | 5 +- 2004/n/fpga/src/portserie/fifodriver.vhd | 83 +++++++++++++++++-------------- 4 files changed, 114 insertions(+), 51 deletions(-) (limited to '2004/n') diff --git a/2004/n/fpga/src/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/bch_txserie.vhd index 735078d..d1aa1e3 100644 --- a/2004/n/fpga/src/portserie/bch_txserie.vhd +++ b/2004/n/fpga/src/portserie/bch_txserie.vhd @@ -40,20 +40,22 @@ architecture sim1 of bch_txserie is -- définiton des signaux signal rst : std_logic; signal clk : std_logic := '0'; +signal simclk : std_logic := '0'; signal rw : std_logic; -- read / write signal bus_data : T_DATA:="00000000"; signal bus_address : T_ADDRESS; signal masterck: std_logic:='0'; signal txout: std_logic; signal minIRQ: std_logic; +signal state_next:integer:=0; begin U1 : txserie generic map ( -- Définition des addresses. - A_DATA => "0000000011", - A_CONFIG => "0000000100", - A_FLAG => "0000000010" + A_DATA => "0000000001", + A_CONFIG => "0000000010", + A_FLAG => "0000000011" ) port map ( rst => rst, @@ -66,15 +68,62 @@ begin minIRQ=> minIRQ ); - rst <= '1', '0' after CK_PERIOD; - clk <= not clk after (CK_PERIOD); - rw <= '0'; - bus_address <= "0000000011", - "0000000100" after 6*CK_PERIOD, - "0000000100" after 10*CK_PERIOD, - "0000000011" after 16*CK_PERIOD; - bus_data <= "01010101";--) after 10 ns; + masterck<= not masterck after (CK_PERIOD/11); + simclk<= not simclk after (CK_PERIOD/2); + + + process(simclk) + begin + if(simclk'event and simclk='1') then + state_next<=(state_next + 1); + end if; + end process; + + process(state_next) + begin + bus_address<="0000000000"; + clk<='0'; + rst<='0'; + bus_data<=(others =>'Z'); + + case state_next is + when 1 => bus_address<="0000000010"; + bus_data<="00010111"; + rw<='0'; + when 2 => bus_address<="0000000010"; + bus_data<="00010111"; + rw<='0'; + clk<='1'; + when 3 => null; + + when 4 => bus_address<="0000000001"; + bus_data<="00010111"; + rw<='0'; + when 5 => bus_address<="0000000001"; + bus_data<="00010111"; + rw<='0'; + clk<='1'; + when 6 => null; + + when 7 => bus_address<="0000000011"; + rw<='1'; + when 8 => bus_address<="0000000011"; + rw<='1'; + clk<='1'; + when 9 => null; + + + when 10 => bus_address<="0000000010"; + rw<='1'; + when 11 => bus_address<="0000000010"; + rw<='1'; + clk<='1'; + when 12 => null; + + when others => null; + end case; + end process; end sim1; @@ -88,3 +137,4 @@ end cf1_bch_txserie; + diff --git a/2004/n/fpga/src/portserie/decoder.vhd b/2004/n/fpga/src/portserie/decoder.vhd index ac586b6..4eb4724 100644 --- a/2004/n/fpga/src/portserie/decoder.vhd +++ b/2004/n/fpga/src/portserie/decoder.vhd @@ -24,11 +24,12 @@ process(bus_address) begin if(bus_address = adr) then - cs<='0'; - else cs<='1'; + else + cs<='0'; end if; end process; end rtl; + diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd index f2a7d22..9023596 100644 --- a/2004/n/fpga/src/portserie/fifo.vhd +++ b/2004/n/fpga/src/portserie/fifo.vhd @@ -79,8 +79,8 @@ FIFO1:fifobehav write_data_in=>data_in, fifo_gsr_in=>purge, read_data_out=>data_out, - full_out=>flags(5), - empty_out=>flags(4), + full_out=>flags(4), + empty_out=>flags(5), fifocount_out=>flags(3 downto 0) ); @@ -104,3 +104,4 @@ end rtl; + diff --git a/2004/n/fpga/src/portserie/fifodriver.vhd b/2004/n/fpga/src/portserie/fifodriver.vhd index 15ab56c..9084d51 100644 --- a/2004/n/fpga/src/portserie/fifodriver.vhd +++ b/2004/n/fpga/src/portserie/fifodriver.vhd @@ -21,55 +21,64 @@ entity fifodriver is constant PRESCAL :integer:= 1; end fifodriver; +-- arch architecture rtl of fifodriver is -signal subck: integer :=0; -signal state_actual,state_next : integer; +signal clock:std_logic; +signal writeflag,readflag :std_logic; +signal subck : integer :=0; begin --- la partie COMBI - COMBI:process(state_actual,readreq,writereq) - begin - fifowrite <= '0'; - fiforead <= '0'; - fifock <= '0'; - state_next <= 1; - - case state_actual is - when 1 => if (readreq='1') then - state_next <= 2; - elsif(writereq='1') then - state_next <= 4; - end if; - - when 2 => state_next <= 3; - fiforead<='1'; + fifock<=clock; - when 3 => state_next <= 1; - fiforead<='1'; - fifock<='1'; +-- process(writereq) +-- begin +-- if (writereq'event and writereq='1') then +-- writeflag<='1'; +-- end if; +-- end process; +-- +-- process(readreq) +-- begin +-- if (readreq'event and readreq='1') then +-- readflag<='1'; +-- end if; +-- end process; - when 4 => state_next <= 5; - fifowrite<='1'; + process(clock,writereq,readreq) + begin + if (writereq'event and writereq='1') then + writeflag<='1'; + end if; - when 5 => state_next <= 1; - fifowrite<='1'; - fifock<='1'; + if (readreq'event and readreq='1') then + readflag<='1'; + end if; - when others => NULL; - end case; - end process COMBI; + -- sur front descendant de fifock, on met fifowrite et fiforead à + -- jour + if(clock'event and clock='0') then + if(readflag='1') then + readflag<='0'; + fiforead<='1'; + end if; + + if(writeflag='1') then + writeflag<='0'; + fifowrite<='1'; + end if; + end if; + end process; --- la partie SEQU - SEQU:process(masterck,reset) +-- la partie SEQU : divise la fréquence d'horloge + SEQU:process(masterck) begin - if (reset='1') then - state_actual <= 1; - elsif (masterck'event and masterck='1') then + if (masterck'event and masterck='1') then if(subck=PRESCAL) then subck<=0; - state_actual <= state_next ; + clock<='1'; else subck<=subck+1; + clock<='0'; end if; end if; end process SEQU; @@ -77,3 +86,5 @@ end rtl; + + -- cgit v1.2.3