From aa5af70bfadebbf3f4809d232f3cf692541cac36 Mon Sep 17 00:00:00 2001 From: galmes Date: Mon, 1 Mar 2004 14:40:02 +0000 Subject: Modification des modeles. Nouvelle version de la gestion de l'addressage (avec 1 chip select par registre). --- 2004/n/fpga/src/modele/bch_modele.vhd | 40 +++++++++++++++++------------------ 2004/n/fpga/src/modele/modele.vhd | 18 ++++++---------- 2 files changed, 26 insertions(+), 32 deletions(-) (limited to '2004/n/fpga') diff --git a/2004/n/fpga/src/modele/bch_modele.vhd b/2004/n/fpga/src/modele/bch_modele.vhd index f813335..8ee34e3 100644 --- a/2004/n/fpga/src/modele/bch_modele.vhd +++ b/2004/n/fpga/src/modele/bch_modele.vhd @@ -17,20 +17,16 @@ end bch_modele; architecture sim1 of bch_modele is component modele - generic ( - -- adresses des différents registres du module. - A_REG1 : T_ADDRESS; - A_REG2 : T_ADDRESS; - A_REG3 : T_ADDRESS - -- si autre choses à déclarer... - ); port ( rst : in std_logic; clk : in std_logic; - rw : in std_logic; -- read / write + rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA; - bus_address : in T_ADDRESS - ); + -- chaque registre se voit administrer un chip select. + cs_reg0 : in std_logic; -- chip select + cs_reg1 : in std_logic; + cs_reg2 : in std_logic + ); end component; -- définiton des signaux @@ -38,30 +34,32 @@ architecture sim1 of bch_modele is signal clk : std_logic := '0'; signal rw : std_logic; -- read / write signal bus_data : T_DATA; - signal bus_address : T_ADDRESS; + signal cs_reg0 : std_logic := '0'; -- chip select + signal cs_reg1 : std_logic := '0'; + signal cs_reg2 : std_logic := '0'; begin U1 : modele - generic map ( - -- Définition des addresses. - A_REG1 => A_IO1_REG_DIRECTION, - A_REG2 => A_IO1_REG_DATA, - A_REG3 => A_IO1_REG_INTERRUPT_MASK - ) port map ( rst => rst, clk => clk, rw => rw, bus_data => bus_data, - bus_address => bus_address + cs_reg0 => cs_reg0, + cs_reg1 => cs_reg1, + cs_reg2 => cs_reg2 ); rst <= '1', '0' after CK_PERIOD; clk <= not clk after (CK_PERIOD/2); rw <= '0'; - bus_address <= A_IO1_REG_DIRECTION, - A_IO1_REG_DATA after 3*CK_PERIOD, - A_IO1_REG_INTERRUPT_MASK after 5*CK_PERIOD; + cs_reg0 <= '1' after CK_PERIOD, + '0' after 3*CK_PERIOD; + cs_reg1 <= '1' after 4*CK_PERIOD, + '0' after 7*CK_PERIOD; + cs_reg2 <= '1' after 8*CK_PERIOD, + '0' after 10*CK_PERIOD; + end sim1; configuration cf1_bch_modele of bch_modele is diff --git a/2004/n/fpga/src/modele/modele.vhd b/2004/n/fpga/src/modele/modele.vhd index c4e9f38..0e11e62 100644 --- a/2004/n/fpga/src/modele/modele.vhd +++ b/2004/n/fpga/src/modele/modele.vhd @@ -11,19 +11,15 @@ use ieee.std_logic_unsigned.all; use work.nono_const.all; entity modele is - generic ( - -- adresses des différents registres du module. - A_REG1 : T_ADDRESS; - A_REG2 : T_ADDRESS; - A_REG3 : T_ADDRESS - -- si autre choses à déclarer... - ); port ( rst : in std_logic; clk : in std_logic; rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA; - bus_address : in T_ADDRESS + -- chaque registre se voit administrer un chip select. + cs_reg0 : in std_logic; -- chip select + cs_reg1 : in std_logic; + cs_reg2 : in std_logic ); end entity; @@ -34,12 +30,12 @@ begin if (rst = '1') then bus_data <= x"00"; elsif (clk'event and clk = '1') then - if (bus_address = A_REG1) then + if (cs_reg0 = '1') then bus_data <= x"01"; else - if (bus_address = A_REG2) then + if (cs_reg1 = '1') then bus_data <= x"02"; - elsif (bus_address = A_REG3) then + elsif (cs_reg2 = '1') then bus_data <= x"03"; end if; end if; -- cgit v1.2.3