From 998849bbda87a0c255d6e689c41491332cae722a Mon Sep 17 00:00:00 2001 From: galmes Date: Sun, 18 Apr 2004 16:24:25 +0000 Subject: pwm : suppression des tb de la version de Fidèle ! --- 2004/n/fpga/src/pwm/tb_affichepwm3.vhd | 62 ------------------------- 2004/n/fpga/src/pwm/tb_clk1us.vhd | 49 -------------------- 2004/n/fpga/src/pwm/tb_comptvalue3.vhd | 71 ----------------------------- 2004/n/fpga/src/pwm/tb_fsmpwm3.vhd | 66 --------------------------- 2004/n/fpga/src/pwm/tb_regdata3.vhd | 73 ------------------------------ 2004/n/fpga/src/pwm/tb_toppwm3.vhd | 83 ---------------------------------- 6 files changed, 404 deletions(-) delete mode 100644 2004/n/fpga/src/pwm/tb_affichepwm3.vhd delete mode 100644 2004/n/fpga/src/pwm/tb_clk1us.vhd delete mode 100644 2004/n/fpga/src/pwm/tb_comptvalue3.vhd delete mode 100644 2004/n/fpga/src/pwm/tb_fsmpwm3.vhd delete mode 100644 2004/n/fpga/src/pwm/tb_regdata3.vhd delete mode 100644 2004/n/fpga/src/pwm/tb_toppwm3.vhd (limited to '2004/n/fpga') diff --git a/2004/n/fpga/src/pwm/tb_affichepwm3.vhd b/2004/n/fpga/src/pwm/tb_affichepwm3.vhd deleted file mode 100644 index 4a93b0a..0000000 --- a/2004/n/fpga/src/pwm/tb_affichepwm3.vhd +++ /dev/null @@ -1,62 +0,0 @@ ---rtl bench de la sortie pwm en fonction de tc test à faire sur41MS environ -library IEEE; - use IEEE.std_logic_1164.all; - use IEEE.std_logic_arith.all; - use IEEE.std_logic_unsigned.all; -library synopsys; -use synopsys.bv_arithmetic.all; ---ENTITY -entity tb_affichepwm3 is -end tb_affichepwm3; ---ARCHITECTURE -architecture sim1 of tb_affichepwm3 is - component affichepwm3 - port(rst : in std_logic; - clk : in std_logic; - clk1usaff : in std_logic; - -- tcaff : in integer; - valueaff : in integer; - outpwm : out std_logic - ); - end component; --- declaration des signaux -signal clk : std_logic:='0'; - signal clk1usaff : std_logic:='0'; - signal rst : std_logic; -signal tcaff: integer :=20161; --mettre a 20161 -signal valueaff: integer:=0; -signal outpwm : std_logic; ---declaration de constantes -constant CLK1US_PERIOD :time:= 992 ns; -constant tcmax :integer:= 20161; --pour le clk1us -constant CLK_PERIOD :time := 32 ns ; - -begin - U1affichepwm3: affichepwm3 port map ( - rst=>rst,clk=>clk,clk1usaff=>clk1usaff, - -- tcaff=>tcaff, - valueaff=>valueaff, - outpwm=>outpwm - ); - ---STIMULI - rst<='1','0'after (CLK1US_PERIOD/3); - clk<= not clk after (CLK_PERIOD/2); - clk1usaff<= not clk1usaff after (CLK1US_PERIOD/2); ---tcaff<=tcmax,0 after (tcmax*CLK1US_PERIOD), - --tcmax after (2*(tcmax*CLK1US_PERIOD)), - --0 after (3*(tcmax*CLK1US_PERIOD)), - --tcmax after (4*(tcmax*CLK1US_PERIOD)); - -valueaff<= 0,90 after((tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/2)), - 0 after((tcmax*CLK1US_PERIOD)+(CLK1US_PERIOD*2)), - 12 after((2*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/2)); -end sim1; - ---CONFIGURATION -configuration cfg_tb_affichepwm3 of tb_affichepwm3 is - for sim1 - for all : affichepwm3 use entity work.affichepwm3(affichepwm3behav); - end for; -end for; -end cfg_tb_affichepwm3; diff --git a/2004/n/fpga/src/pwm/tb_clk1us.vhd b/2004/n/fpga/src/pwm/tb_clk1us.vhd deleted file mode 100644 index 03727e9..0000000 --- a/2004/n/fpga/src/pwm/tb_clk1us.vhd +++ /dev/null @@ -1,49 +0,0 @@ ---test bench du compteur sur value pour duree du niveau haut test à faire sur 59ms environ -library IEEE; - use IEEE.std_logic_1164.all; - use IEEE.std_logic_arith.all; - use IEEE.std_logic_unsigned.all; -library synopsys; -use synopsys.bv_arithmetic.all; ---ENTITY -entity tb_clk1us is -end tb_clk1us; ---ARCHITECTURE -architecture sim1 of tb_clk1us is - component clk1us - port( - rst : in std_logic; - clk : in std_logic; - --inc : buffer integer; - clk1usout : out std_logic - ); - end component; --- declaration des signaux -signal rst:std_logic; -signal clk:std_logic:='0'; ---signal inc : integer; -signal clk1usout : std_logic; ---declaration de constantes -constant CLK_PERIOD :time := 32 ns ; --31,25ns normalememt - -begin - U1clk1us: clk1us port map ( -rst=>rst, - clk=>clk, - -- inc=>inc, - clk1usout=>clk1usout - ); - ---STIMULI - clk<= not clk after (CLK_PERIOD/2); - rst<='1','0' after (CLK_PERIOD/4); - -end sim1; - ---CONFIGURATION -configuration cfg_tb_clk1us of tb_clk1us is - for sim1 - for all : clk1us use entity work.clk1us(clk1usbehav); - end for; -end for; -end cfg_tb_clk1us; diff --git a/2004/n/fpga/src/pwm/tb_comptvalue3.vhd b/2004/n/fpga/src/pwm/tb_comptvalue3.vhd deleted file mode 100644 index 6247158..0000000 --- a/2004/n/fpga/src/pwm/tb_comptvalue3.vhd +++ /dev/null @@ -1,71 +0,0 @@ ---test bench du compteur sur value pour duree du niveau haut test à faire sur 59ms environ -library IEEE; - use IEEE.std_logic_1164.all; - use IEEE.std_logic_arith.all; - use IEEE.std_logic_unsigned.all; -library synopsys; -use synopsys.bv_arithmetic.all; ---ENTITY -entity tb_comptvalue3 is -end tb_comptvalue3; ---ARCHITECTURE -architecture sim1 of tb_comptvalue3 is - component comptvalue3 - port( - rst : in std_logic; - clk : in std_logic; - clk1uscompt : in std_logic; - loadcompt : in std_logic; - datacompt : in integer; - tccompt : buffer integer; - valuecompt : out integer - ); - end component; --- declaration des signaux -signal rst:std_logic; -signal clk:std_logic:='0'; -signal clk1uscompt: std_logic:='0'; -signal loadcompt: std_logic; -signal datacompt : integer:=0; -signal tccompt: integer; -signal valuecompt: integer; ---declaration de constantes - -constant CLK1US_PERIOD :time:= 992 ns; -constant tcmax :integer:= 20161; --pour le clk1us -constant CLK_PERIOD :time := 32 ns ; -begin - U1comptvalue3: comptvalue3 port map ( - rst=>rst, - clk=>clk, - clk1uscompt=>clk1uscompt, - loadcompt=>loadcompt, - datacompt=>datacompt, - tccompt=>tccompt, - valuecompt=>valuecompt - ); - ---STIMULI - clk<= not clk after (CLK_PERIOD/2);rst<='1','0'after (CLK_PERIOD/6); - clk1uscompt<= not clk1uscompt after (CLK1US_PERIOD/2); - loadcompt<='0','1'after (tcmax*CLK1US_PERIOD-(CLK1US_PERIOD/2)),'0' after (tcmax*CLK1US_PERIOD+(CLK1US_PERIOD/2)), - '1'after((2*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/2)),'0' after ((2*(tcmax*CLK1US_PERIOD))+(CLK1US_PERIOD/2)), - '1'after ((3*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/2)),'0' after ((3*(tcmax*CLK1US_PERIOD))+(CLK1US_PERIOD/2)), - '1'after((4*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/2)),'0' after ((4*(tcmax*CLK1US_PERIOD))+(CLK1US_PERIOD/2)); - datacompt<= - 0, 25 after ((tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)), - 0 after (2*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)), - 255 after (3*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)), - 100 after (4*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)); - - -end sim1; - ---CONFIGURATION -configuration cfg_tb_comptvalue3 of tb_comptvalue3 is - for sim1 - for all : comptvalue3 use entity work.comptvalue3(comptvalue3behav); - end for; -end for; -end cfg_tb_comptvalue3; - diff --git a/2004/n/fpga/src/pwm/tb_fsmpwm3.vhd b/2004/n/fpga/src/pwm/tb_fsmpwm3.vhd deleted file mode 100644 index aec67ed..0000000 --- a/2004/n/fpga/src/pwm/tb_fsmpwm3.vhd +++ /dev/null @@ -1,66 +0,0 @@ ---simulation pendant 41 ms - -library IEEE; - use IEEE.std_logic_1164.all; - use IEEE.std_logic_arith.all; - use IEEE.std_logic_unsigned.all; -library work; -library synopsys; -use synopsys.bv_arithmetic.all; ---ENTITY -entity tb_fsmpwm3 is -end tb_fsmpwm3; ---ARCHITECTURE -architecture sim1 of tb_fsmpwm3 is - component fsmpwm3 - port(RST :in std_logic; - CLK :in std_logic; - CLK1USFSM :in std_logic; - tcfsm :in integer; - - enloadfsm:out std_logic - ); - end component; --- declaration des signaux -signal RST:std_logic; -signal CLK:std_logic:='0'; -signal CLK1USFSM:std_logic:='0'; -signal tcfsm:integer:=0; - -signal enloadfsm: std_logic:='0'; - ---CONSTANT -constant CLK1US_PERIOD :time:= 992 ns; -constant tcmax :integer:= 20161; --pour le clk1us -constant CLK_PERIOD :time := 32 ns ; ---MAP - begin - U1fsmpwm3 : fsmpwm3 port map ( - RST=>RST,CLK=>CLK,CLK1USFSM=>CLK1USFSM,tcfsm=>tcfsm,enloadfsm=>enloadfsm - ); - - rst<='1','0'after (CLK1US_PERIOD/3); - clk<= not clk after (CLK_PERIOD/2); - clk1usfsm<= not clk1usfsm after (CLK1US_PERIOD/2); --- STIMULI - - process - begin - tcfsm<=tcmax;wait for (CLK1US_PERIOD); - tcfsm<=10;wait for ((tcmax*(CLK1US_PERIOD))-(CLK1US_PERIOD)); - tcfsm<=0;wait for ((CLK1US_PERIOD)); - tcfsm<=tcmax;wait for (CLK1US_PERIOD); - tcfsm<=10;wait for ((tcmax*(CLK1US_PERIOD))-(CLK1US_PERIOD)); - tcfsm<=0;wait for ((CLK1US_PERIOD)); - - end process; -end sim1; - ---CONFIGURATION -configuration cfg_tb_fsmpwm3 of tb_fsmpwm3 is - for sim1 - --for U1fsmpwm3 : fsmpwm3 use entity work.fsmpwm3(BEHAV); - for all: fsmpwm3 use entity work.fsmpwm3(BEHAV); -end for; -end for; -end cfg_tb_fsmpwm3; diff --git a/2004/n/fpga/src/pwm/tb_regdata3.vhd b/2004/n/fpga/src/pwm/tb_regdata3.vhd deleted file mode 100644 index 90fd060..0000000 --- a/2004/n/fpga/src/pwm/tb_regdata3.vhd +++ /dev/null @@ -1,73 +0,0 @@ ---rtlBench du registre de sauvegarde des donnees entrantes:qst de stabilite ---simul sur 41 ms ---*******tests ---on verifie si 099 est bien en sortie au depart alors que load vaut 0 ---si chq load dure 1 clk1us ---si a chq nv haut de load, l'entree est sur la sortie. ---*********** - -library IEEE; - use IEEE.std_logic_1164.all; - use IEEE.std_logic_arith.all; - use IEEE.std_logic_unsigned.all; -library work; -library synopsys; -use synopsys.bv_arithmetic.all; ---ENTITY -entity tb_regdata3 is -end tb_regdata3; ---ARCHITECTURE -architecture sim1 of tb_regdata3 is - component regdata3 - port(RST : in std_logic; - CLK : in std_logic; - clk1usreg : in std_logic; - enloadreg: in std_logic; - datain: in std_logic_vector (7 downto 0); - datareg: out integer--signaux de sortie du registre - ); - end component; - --- declaration des signaux -signal rst: std_logic; -signal clk: std_logic:='0'; -signal clk1usreg: std_logic:='0'; -signal enloadreg: std_logic:='0'; - -signal datain: std_logic_vector (7 downto 0):="00000000"; - -signal datareg: integer:=0;--signaux de sortie du registre - ---CONSTANT -constant CLK1US_PERIOD :time:=992 ns; -constant tcmax :integer:= 20161; --pour le clk1us -constant CLK_PERIOD :time := 32 ns ; - ---MAP - begin - U1regdata3 : regdata3 port map ( - rst=>rst,clk=>clk,clk1usreg=>clk1usreg,enloadreg=>enloadreg,datain=>datain,datareg=>datareg - ); --- STIMULI - clk<= not clk after (CLK_PERIOD/2); - rst<='1','0' after (CLK_PERIOD/3); - clk1usreg<= not clk1usreg after (CLK1US_PERIOD/2); - - - enloadreg<= '0','1' after (tcmax*CLK1US_PERIOD), '0' after ((tcmax*CLK1US_PERIOD)+(CLK1US_PERIOD)), - '1' after(2*(tcmax*CLK1US_PERIOD)), '0' after ((2*(tcmax*CLK1US_PERIOD))+(CLK1US_PERIOD)); - - - datain<="10100000","00000101" after (CLK1US_PERIOD/4), - "00011001" after((tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)), - "00000000" after((2*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/6)); - - -end sim1; ---CONFIGURATION -configuration cfg_tb_regdata3 of tb_regdata3 is - for sim1 - for U1regdata3 : regdata3 use entity work.regdata3(BEHAV); -end for; -end for; -end cfg_tb_regdata3; diff --git a/2004/n/fpga/src/pwm/tb_toppwm3.vhd b/2004/n/fpga/src/pwm/tb_toppwm3.vhd deleted file mode 100644 index 5775d18..0000000 --- a/2004/n/fpga/src/pwm/tb_toppwm3.vhd +++ /dev/null @@ -1,83 +0,0 @@ ---simulation sur 82 ms environ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; -library work; -library synopsys; -use synopsys.bv_arithmetic.all; - ---ENTITY -entity tb_toppwm3 is -end tb_toppwm3; - ---ARCHITECTURE -architecture sim1 of tb_toppwm3 is - component toppwm3 - port( - RST :in std_logic; - CLK :in std_logic; - DATA :in std_logic_vector (7 downto 0); - OUTPWM :out std_logic - ); - end component; --- declaration des signaux -signal RST : std_logic; -signal CLK : std_logic:='0'; -signal DATA: std_logic_vector (7 downto 0); - -signal OUTPWM: std_logic; - ---CONSTANT ---constant ENVLP_PERIOD : time := 20 ms; ---constant DATA_MAX : integer := 15; ---constant CLK_PERIOD : time := (ENVLP_PERIOD/DATA_MAX); ---constant CLK1_FREQ :integer:= 30E+6;--car freq de 30MHz ---constant tcmax :integer:= 600E3; ---constant seconde :time := 1 sec; ---constant CLK_PERIOD :time := (seconde/CLK1_FREQ) ; - ---constant CLK1US_PERIOD :time:= 992 ns; ---constant tcmax :integer:= 20161; --pour le clk1us -constant CLK_PERIOD :time := 32 ns ; - - ---MAP - begin - U1toppwm3: toppwm3 port map ( - RST=>RST, - CLK=>CLK, - DATA=>DATA, - OUTPWM=>OUTPWM - ); - --- STIMULI - RST <= '1','0' after(CLK_PERIOD/6); - clk<= not clk after (CLK_PERIOD/2); - - data<="00000011", "00011001" after 17 ms, --0 25 - -- "00000000", "00011001" after 17 ms, --0 25 - "00000000" after 38 ms, -- 0 - "11111111" after 58 ms, -- 255 - "01111111" after 78 ms; -- 127 - - --"00000000", "00011001" after ((tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)), - --"00000000" after (2*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)), - --"11111111" after (3*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)), - --"00011100" after (4*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)); - - --"00000000",--10 - -- "01100101" after 25 ms,--5 - -- "00000000" after 30 ms,--vérifier que cette donnée est bien perdue - -- "11111111" after 38 ms, - -- "00100000" after 50 ms; -end sim1; - ---CONFIGURATION -configuration cfg_tb_toppwm3 of tb_toppwm3 is - for sim1 - -- for U1toppwm3 : toppwm3 use entity work.toppwm3(RTL);end for; - for all : toppwm3 use entity work.toppwm3(RTL);end for; -end for; -end cfg_tb_toppwm3; - -- cgit v1.2.3