From 8b3bc0049450eb44b2c2c461bec3c3f3801742f8 Mon Sep 17 00:00:00 2001 From: prot Date: Sat, 17 Apr 2004 10:29:32 +0000 Subject: Intgration du tx dans le fpga Le behav marche, mais pas en post-translate --- 2004/n/fpga/src/fpga/fpga-test.vhd | 78 +- 2004/n/fpga/src/fpga/fpga.npl | 9 + 2004/n/fpga/src/fpga/fpga.vhd | 40 +- 2004/n/fpga/src/fpga/fpga_translate.vhd | 7584 +++++++++++++++----- .../n/fpga/src/portserie/portserie/bch_txserie.vhd | 54 +- 2004/n/fpga/src/portserie/portserie/txserie.vhd | 11 +- 2004/n/fpga/src/portserie/rxserie/rxserie.vhd | 2 +- 7 files changed, 5817 insertions(+), 1961 deletions(-) (limited to '2004/n/fpga') diff --git a/2004/n/fpga/src/fpga/fpga-test.vhd b/2004/n/fpga/src/fpga/fpga-test.vhd index 4595ca4..4459bef 100644 --- a/2004/n/fpga/src/fpga/fpga-test.vhd +++ b/2004/n/fpga/src/fpga/fpga-test.vhd @@ -31,7 +31,12 @@ ARCHITECTURE behavior OF bch_fpga IS bus_adr : IN std_logic_vector(23 downto 0); rxin1 : IN std_logic; bus_data : INOUT std_logic_vector(7 downto 0); - irq : OUT std_logic + irq : OUT std_logic; + irqrxFIFO : OUT std_logic; + irqrxRX : OUT std_logic; + irqrxERR : OUT std_logic; + irqtx : OUT std_logic; + txout1 : OUT std_logic ); END COMPONENT; @@ -45,8 +50,11 @@ ARCHITECTURE behavior OF bch_fpga IS SIGNAL bus_adr : std_logic_vector(23 downto 0); SIGNAL bus_data : std_logic_vector(7 downto 0); SIGNAL irq : std_logic; + SIGNAL irqrxFIFO,irqrxRX,irqrxERR,irqtx : std_logic; + SIGNAL rxin1 : std_logic:='0'; - + SIGNAL txout1 : std_logic; + signal data : integer; signal data_received : std_logic_vector(7 downto 0); @@ -62,18 +70,25 @@ BEGIN bus_adr => bus_adr, bus_data => bus_data, irq => irq, - rxin1 => rxin1 + irqrxFIFO => irqrxFIFO , + irqrxRX => irqrxRX, + irqrxERR => irqrxERR , + irqtx => irqtx , + rxin1 => rxin1, + txout1 => txout1 ); + -- master clock clk_speed <= (Not clk_speed) after (CK_PERIOD/2); -- Reset -rst <= '1','0' after (10*CK_PERIOD); +rst <= '1','0' after (100 ns); -- baudrate/(16*2) used to generate half clock cycle; clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz + -- feeding back output from transmitter to the input of receiver -rxin1 <= (not rxin1) after 15751 ns; +rxin1 <= txout1; check:process @@ -119,23 +134,56 @@ check:process WAIT FOR 20 ns; END write_bus; + +-- RX +-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0) +-- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 ) + + +-- TX +-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) +-- Flag : (x ! x ! x ! x ! Empty ! Full ! FLI1 ! FLI0 ) + begin - read_bus(259); - data<=179; - write_bus(259); - read_bus(259); - wait for 100 ns; - read_bus(258); +-- RX +-- data : 257 +-- config : 258 +-- flag : 259 +-- TX +-- data : 260 +-- config : 261 +-- flag : 262 + + wait for 500 ns; + +-- configuration du RX (RX_config) data<=255; write_bus(258); read_bus(258); wait for 100 ns; - read_bus(257); - data<=179; - write_bus(257); - read_bus(257); +-- configuration du TX + data<=119; + write_bus(261); + read_bus(261); + wait for 5 us; + +-- transmission par le TX + data<=177; + write_bus(260); + read_bus(260); + + wait for 100 ns; + + +-- transmission par le TX + data<=22; + write_bus(260); + read_bus(260); + + + wait for 100 ns; wait for 100 ns; end process; diff --git a/2004/n/fpga/src/fpga/fpga.npl b/2004/n/fpga/src/fpga/fpga.npl index 47b8714..6bc4e79 100644 --- a/2004/n/fpga/src/fpga/fpga.npl +++ b/2004/n/fpga/src/fpga/fpga.npl @@ -33,7 +33,16 @@ SOURCE ..\decodisa\decodisa.vhd STIMULUS ..\decodisa\bch_decodisa.vhd STIMULUS fpga-test.vhd SOURCE ..\modele\nono_const.vhd +STIMULUS ..\portserie\portserie\bch_txmit.vhd +STIMULUS ..\portserie\portserie\bch_txserie.vhd +SOURCE ..\portserie\portserie\txserie.vhd +SOURCE ..\portserie\uart\txmit.vhd [STATUS-ALL] decodisa.ngcFile=WARNINGS,1080659193 +fpga.ngcFile=WARNINGS,1082194051 +fpga.ngdFile=WARNINGS,1082194062 +txmit.ngdFile=WARNINGS,1082195280 +txserie.ngcFile=WARNINGS,1082194924 +txserie.ngdFile=WARNINGS,1082194930 [STRATEGY-LIST] Normal=True diff --git a/2004/n/fpga/src/fpga/fpga.vhd b/2004/n/fpga/src/fpga/fpga.vhd index 95aa898..1973b41 100644 --- a/2004/n/fpga/src/fpga/fpga.vhd +++ b/2004/n/fpga/src/fpga/fpga.vhd @@ -22,9 +22,11 @@ port( bus_adr : in std_logic_vector(23 downto 0); bus_data : INOUT std_logic_vector(7 downto 0); irq : OUT std_logic; + irqrxFIFO,irqrxRX,irqrxERR,irqtx : OUT std_logic; -- les entrées-sorties - rxin1:in std_logic + rxin1:in std_logic; + txout1:out std_logic ); end fpga; @@ -49,6 +51,22 @@ architecture rtl of fpga is ); END COMPONENT; + COMPONENT txserie + PORT( + rst : IN std_logic; + bus_clk : IN std_logic; + rw : IN std_logic; + clk : IN std_logic; + clk_ref : IN std_logic; + csData : IN std_logic; + csConfig : IN std_logic; + csFlag : IN std_logic; + bus_data : INOUT std_logic_vector(7 downto 0); + txout : OUT std_logic; + minIRQ : OUT std_logic + ); + END COMPONENT; + COMPONENT decodisa PORT( adr_bus : IN std_logic_vector(23 downto 0); @@ -91,14 +109,28 @@ begin clk => clk_speed, clk_ref => clk_ref, rxin => rxin1, - irqFIFO => open, - irqRX => open, - irqERR => open, + irqFIFO => irqrxFIFO, + irqRX => irqrxRX, + irqERR => irqrxERR, csData => cs(1), csConfig => cs(2), csFlag => cs(3) ); + Inst_txserie1: txserie PORT MAP( + rst => rst, + bus_clk => bus_clk, + rw => rw, + bus_data => bus_data, + clk => clk_speed, + clk_ref => clk_ref, + txout => txout1, + minIRQ => irqtx, + csData => cs(4), + csConfig => cs(5), + csFlag => cs(6) + ); + end rtl; diff --git a/2004/n/fpga/src/fpga/fpga_translate.vhd b/2004/n/fpga/src/fpga/fpga_translate.vhd index b2ca18d..fbae9fb 100644 --- a/2004/n/fpga/src/fpga/fpga_translate.vhd +++ b/2004/n/fpga/src/fpga/fpga_translate.vhd @@ -29,24 +29,38 @@ entity fpga is IOW : in STD_LOGIC := 'X'; clk_ref : in STD_LOGIC := 'X'; irq : out STD_LOGIC; + irqrxERR : out STD_LOGIC; + irqrxRX : out STD_LOGIC; + irqtx : out STD_LOGIC; + txout1 : out STD_LOGIC; + irqrxFIFO : out STD_LOGIC; bus_adr : in STD_LOGIC_VECTOR ( 23 downto 0 ); bus_data : inout STD_LOGIC_VECTOR ( 7 downto 0 ) ); end fpga; architecture Structure of fpga is - signal rst_IBUF : STD_LOGIC; + signal bus_clk : STD_LOGIC; + signal irqrxERR_OBUF : STD_LOGIC; + signal irqrxRX_OBUF : STD_LOGIC; + signal rst_BUFGP : STD_LOGIC; signal rxin1_IBUF : STD_LOGIC; signal bus_adr_1_IBUF : STD_LOGIC; signal clk_speed_BUFGP : STD_LOGIC; signal AEN_IBUF : STD_LOGIC; + signal irqtx_OBUF : STD_LOGIC; + signal Inst_txserie1_TX1_TX : STD_LOGIC; + signal irqrxFIFO_OBUF : STD_LOGIC; signal IOR_IBUF : STD_LOGIC; signal IOW_IBUF : STD_LOGIC; - signal clk_ref_IBUF : STD_LOGIC; - signal rw : STD_LOGIC; - signal bus_clk : STD_LOGIC; + signal clk_ref_BUFGP : STD_LOGIC; signal bus_adr_0_IBUF : STD_LOGIC; - signal N10989 : STD_LOGIC; + signal rw : STD_LOGIC; + signal Inst_txserie1_TX1_n0026 : STD_LOGIC; + signal Inst_txserie1_TX1_n0032 : STD_LOGIC; + signal Inst_txserie1_TX1_n0027 : STD_LOGIC; + signal Inst_txserie1_TX1_n0033 : STD_LOGIC; + signal Inst_txserie1_TX1_n0034 : STD_LOGIC; signal bus_adr_15_IBUF : STD_LOGIC; signal bus_adr_14_IBUF : STD_LOGIC; signal bus_adr_13_IBUF : STD_LOGIC; @@ -61,64 +75,100 @@ architecture Structure of fpga is signal bus_adr_4_IBUF : STD_LOGIC; signal bus_adr_3_IBUF : STD_LOGIC; signal bus_adr_2_IBUF : STD_LOGIC; - signal Inst_rxserie1_RFLAG_REG_2_n0000 : STD_LOGIC; signal Inst_rxserie1_RCONF_n0007 : STD_LOGIC; - signal Inst_rxserie1_RCONF_I1_N1369 : STD_LOGIC; - signal Inst_rxserie1_FIFO1_state_read_FFd4_N1455 : STD_LOGIC; - signal N10999 : STD_LOGIC; - signal Inst_rxserie1_RFLAG_REG_6_n0000 : STD_LOGIC; - signal Inst_rxserie1_RFLAG_REG_3_n0000 : STD_LOGIC; - signal bus_data_5_IOBUF : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_write_FFd2 : STD_LOGIC; + signal Inst_rxserie1_RCONF_I1_N1528 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_write_FFd1 : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_write_FFd1 : STD_LOGIC; + signal Inst_rxserie1_state_rx_read_FFd3_In : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_read_FFd1_In : STD_LOGIC; + signal bus_data_6_IOBUF : STD_LOGIC; signal Inst_rxserie1_state_rx_read_FFd2 : STD_LOGIC; signal Inst_rxserie1_RC1_RXDATARDY : STD_LOGIC; + signal bus_data_3_IOBUF : STD_LOGIC; + signal N6239 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_ckout : STD_LOGIC; signal Inst_rxserie1_geneck : STD_LOGIC; signal Inst_rxserie1_rxread : STD_LOGIC; - signal Inst_rxserie1_FIFO1_state_write_FFd2 : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_read_FFd3_In : STD_LOGIC; signal Inst_rxserie1_RC1_OVERRUN : STD_LOGIC; signal Inst_rxserie1_RC1_FRAMING_ERR : STD_LOGIC; signal Inst_rxserie1_RC1_PARITY_ERR : STD_LOGIC; - signal Inst_rxserie1_I7_N1369 : STD_LOGIC; - signal Inst_rxserie1_RC1_RXCNT_3_rt : STD_LOGIC; - signal Inst_rxserie1_FIFO1_state_read_FFd2 : STD_LOGIC; - signal Inst_rxserie1_RC1_RXCNT_1_rt : STD_LOGIC; + signal Inst_rxserie1_I7_N1528 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_read_FFd3 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_read_FFd3_In : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_read_FFd4 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_rd_en : STD_LOGIC; signal Inst_rxserie1_FIFO1_wr_en : STD_LOGIC; - signal Inst_rxserie1_RFLAG_I1_N1369 : STD_LOGIC; + signal N8727 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_write_FFd3 : STD_LOGIC; - signal Inst_rxserie1_CLOCK1_compteur_0_rt : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_read_FFd4_In : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_1_n0000 : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_read_FFd1_In : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_0_n0000 : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_5_n0000 : STD_LOGIC; - signal N11003 : STD_LOGIC; - signal Inst_rxserie1_state_rx_read_FFd1 : STD_LOGIC; - signal Inst_rxserie1_FIFO1_state_write_FFd1 : STD_LOGIC; - signal Inst_rxserie1_RFLAG_REG_4_n0000 : STD_LOGIC; - signal Inst_rxserie1_state_rx_read_FFd3_In : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_read_FFd1 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_write_FFd3_In : STD_LOGIC; - signal Inst_rxserie1_state_rx_read_FFd4 : STD_LOGIC; - signal Inst_rxserie1_state_rx_read_FFd3 : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_read_FFd4_In : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_4_n0000 : STD_LOGIC; + signal Inst_txserie1_FIFO1_dready : STD_LOGIC; + signal bus_data_2_IOBUF : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_write_FFd1_In : STD_LOGIC; - signal Inst_rxserie1_RFLAG_n0007 : STD_LOGIC; signal Inst_rxserie1_FIFO1_state_write_FFd2_In : STD_LOGIC; - signal N4805 : STD_LOGIC; + signal Inst_txserie1_state_txload_0_Q : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_read_FFd1 : STD_LOGIC; + signal Inst_txserie1_RFLAG_n0007 : STD_LOGIC; + signal Inst_rxserie1_RFLAG_I1_N1528 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_read_FFd2 : STD_LOGIC; + signal Inst_rxserie1_RFLAG_n0007 : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_2_n0000 : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_6_n0000 : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_write_FFd2 : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_write_FFd1_In : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_write_FFd3_In : STD_LOGIC; + signal Inst_txserie1_FIFO1_dready_N1514 : STD_LOGIC; + signal Inst_rxserie1_state_rx_read_FFd4 : STD_LOGIC; + signal Inst_rxserie1_state_rx_read_FFd1 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_read_FFd4_N1643 : STD_LOGIC; + signal Inst_rxserie1_state_rx_read_FFd3 : STD_LOGIC; + signal N15406 : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_write_FFd2_In : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_write_FFd3 : STD_LOGIC; + signal Inst_txserie1_RCONF_n0007 : STD_LOGIC; + signal Inst_txserie1_FIFO1_wr_en : STD_LOGIC; + signal Inst_txserie1_RCONF_I1_N1528 : STD_LOGIC; + signal bus_data_4_IOBUF : STD_LOGIC; + signal Inst_txserie1_RFLAG_REG_0_n0000 : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_read_FFd4 : STD_LOGIC; + signal Inst_txserie1_RFLAG_REG_2_n0000 : STD_LOGIC; + signal Inst_txserie1_RFLAG_I1_N1528 : STD_LOGIC; + signal Inst_txserie1_FIFO1_rd_en : STD_LOGIC; + signal Inst_txserie1_RFLAG_REG_3_n0000 : STD_LOGIC; + signal Inst_txserie1_RFLAG_REG_1_n0000 : STD_LOGIC; + signal Inst_txserie1_FIFO1_state_read_FFd3 : STD_LOGIC; + signal Inst_txserie1_state_txload_2_Q : STD_LOGIC; + signal bus_data_5_IOBUF : STD_LOGIC; + signal Inst_txserie1_txready : STD_LOGIC; + signal Inst_txserie1_fifopurge : STD_LOGIC; + signal Inst_txserie1_txload : STD_LOGIC; + signal Inst_txserie1_CLOCK1_ckout : STD_LOGIC; + signal Inst_txserie1_n0010 : STD_LOGIC; + signal N6828 : STD_LOGIC; signal bus_data_0_IOBUF : STD_LOGIC; signal bus_data_7_IOBUF : STD_LOGIC; signal bus_data_1_IOBUF : STD_LOGIC; - signal bus_data_6_IOBUF : STD_LOGIC; - signal bus_data_2_IOBUF : STD_LOGIC; - signal bus_data_4_IOBUF : STD_LOGIC; - signal bus_data_3_IOBUF : STD_LOGIC; + signal Inst_txserie1_TX1_n0039 : STD_LOGIC; signal Inst_rxserie1_RC1_n0050 : STD_LOGIC; signal Inst_rxserie1_RC1_Madd_n0040_inst_cy_12 : STD_LOGIC; signal Inst_rxserie1_RC1_Madd_n0040_inst_cy_11 : STD_LOGIC; - signal Inst_rxserie1_RC1_N7296 : STD_LOGIC; + signal Inst_rxserie1_RC1_N10580 : STD_LOGIC; signal Inst_rxserie1_RC1_n0062 : STD_LOGIC; signal Inst_rxserie1_RC1_HUNT : STD_LOGIC; signal Inst_rxserie1_RC1_RX1 : STD_LOGIC; signal Inst_rxserie1_RC1_PARITYGEN : STD_LOGIC; signal Inst_rxserie1_RC1_n0051 : STD_LOGIC; - signal Inst_rxserie1_RC1_RXCLK : STD_LOGIC; signal Inst_decodisa_reg_select : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCLK : STD_LOGIC; signal Inst_rxserie1_RC1_READ1 : STD_LOGIC; signal Inst_rxserie1_RC1_IDLE1 : STD_LOGIC; signal Inst_rxserie1_RC1_READ2 : STD_LOGIC; @@ -143,9 +193,44 @@ architecture Structure of fpga is signal Inst_rxserie1_RC1_n0036 : STD_LOGIC; signal Inst_rxserie1_RC1_n0063 : STD_LOGIC; signal Inst_rxserie1_RC1_Madd_n0040_inst_lut2_10 : STD_LOGIC; - signal N11001 : STD_LOGIC; signal Inst_rxserie1_RC1_Madd_n0040_inst_cy_10 : STD_LOGIC; signal Inst_rxserie1_RC1_IDLE : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_n0005 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 : STD_LOGIC; + signal N15395 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_0_3_n0001 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_n0006 : STD_LOGIC; + signal N15387 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_0_0_n0001 : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCNT_3_rt : STD_LOGIC; + signal N15389 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_0_0_n0000 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_0_2_n0000 : STD_LOGIC; + signal N15391 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_0_3_n0000 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_0_1_n0001 : STD_LOGIC; + signal N15393 : STD_LOGIC; + signal N15397 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_0_2_n0001 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_0_1_n0000 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_rt : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1 : STD_LOGIC; @@ -165,25 +250,57 @@ architecture Structure of fpga is signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 : STD_LOGIC; - signal N10993 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_3_n0001 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_n0006 : STD_LOGIC; - signal Inst_rxserie1_RC1_RXCNT_2_rt : STD_LOGIC; - signal N10997 : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_0_rt : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCNT_1_rt : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_0_n0001 : STD_LOGIC; - signal N10991 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_0_n0000 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_2_n0000 : STD_LOGIC; - signal N10995 : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCNT_2_rt : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_3_n0000 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_1_n0001 : STD_LOGIC; - signal N10987 : STD_LOGIC; + signal N15385 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_2_n0001 : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_0_1_n0000 : STD_LOGIC; - signal N11025 : STD_LOGIC; - signal N11021 : STD_LOGIC; - signal CHOICE64 : STD_LOGIC; - signal CHOICE45 : STD_LOGIC; + signal N15399 : STD_LOGIC; + signal Inst_txserie1_TX1_WRITE2 : STD_LOGIC; + signal Inst_txserie1_TX1_TXCLK : STD_LOGIC; + signal Inst_txserie1_TX1_WRITE1 : STD_LOGIC; + signal Inst_txserie1_TX1_TXDONE : STD_LOGIC; + signal Inst_txserie1_TX1_TXDATARDY : STD_LOGIC; + signal Inst_txserie1_TX1_n0048 : STD_LOGIC; + signal Inst_txserie1_TX1_TXDONE1 : STD_LOGIC; + signal Inst_txserie1_TX1_TAG1 : STD_LOGIC; + signal Inst_txserie1_TX1_TAG2 : STD_LOGIC; + signal Inst_txserie1_TX1_TXPARITY : STD_LOGIC; + signal Inst_txserie1_TX1_n0020 : STD_LOGIC; + signal Inst_txserie1_TX1_n0021 : STD_LOGIC; + signal Inst_txserie1_TX1_n0022 : STD_LOGIC; + signal Inst_txserie1_TX1_n0017 : STD_LOGIC; + signal Inst_txserie1_TX1_n0023 : STD_LOGIC; + signal Inst_txserie1_TX1_n0018 : STD_LOGIC; + signal Inst_txserie1_TX1_n0024 : STD_LOGIC; + signal Inst_txserie1_TX1_n0019 : STD_LOGIC; + signal Inst_txserie1_TX1_n0030 : STD_LOGIC; + signal Inst_txserie1_TX1_n0025 : STD_LOGIC; + signal Inst_txserie1_TX1_n0031 : STD_LOGIC; + signal N14869 : STD_LOGIC; + signal N15437 : STD_LOGIC; + signal CHOICE135 : STD_LOGIC; + signal N14920 : STD_LOGIC; + signal N15477 : STD_LOGIC; + signal CHOICE95 : STD_LOGIC; + signal CHOICE41 : STD_LOGIC; + signal N15425 : STD_LOGIC; + signal CHOICE68 : STD_LOGIC; + signal CHOICE98 : STD_LOGIC; + signal CHOICE36 : STD_LOGIC; + signal CHOICE144 : STD_LOGIC; + signal N15429 : STD_LOGIC; + signal N15433 : STD_LOGIC; + signal CHOICE116 : STD_LOGIC; + signal N14659 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N47 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N48 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N49 : STD_LOGIC; @@ -257,6 +374,79 @@ architecture Structure of fpga is signal Inst_rxserie1_FIFO1_fifo0_N2 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N0 : STD_LOGIC; signal Inst_rxserie1_FIFO1_fifo0_N1 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N47 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N48 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N49 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N50 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N51 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N52 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N53 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N54 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1271 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1143 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1142 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N74 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1113 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1110 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1107 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1104 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1101 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N73 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1040 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1037 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1034 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1031 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1028 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N716 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N738 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N715 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N735 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N733 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N17 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N714 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N730 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N728 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N18 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N713 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N725 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N723 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N19 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N712 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N720 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N717 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N20 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N718 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N592 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N609 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N4 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N591 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N606 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N604 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N5 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N590 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N601 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N599 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N6 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N589 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N596 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N593 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N7 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N594 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N33 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_wr_ack : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N505 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_wr_err : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N456 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N38 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N3 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_rd_ack : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N333 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_rd_err : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N284 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N37 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N2 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N0 : STD_LOGIC; + signal Inst_txserie1_FIFO1_fifo0_N1 : STD_LOGIC; signal Inst_decodisa_dadrL_O_255_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N18685 : STD_LOGIC; signal Inst_decodisa_dadrL_N18684 : STD_LOGIC; @@ -1004,44 +1194,58 @@ architecture Structure of fpga is signal Inst_decodisa_dadrL_O_7_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1077 : STD_LOGIC; signal Inst_decodisa_dadrL_N1076 : STD_LOGIC; - signal Inst_decodisa_dadrL_O_6_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N1006 : STD_LOGIC; signal Inst_decodisa_dadrL_N1005 : STD_LOGIC; - signal Inst_decodisa_dadrL_O_5_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N935 : STD_LOGIC; signal Inst_decodisa_dadrL_N934 : STD_LOGIC; - signal Inst_decodisa_dadrL_O_4_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N864 : STD_LOGIC; signal Inst_decodisa_dadrL_N863 : STD_LOGIC; signal Inst_decodisa_dadrL_N793 : STD_LOGIC; signal Inst_decodisa_dadrL_N792 : STD_LOGIC; signal Inst_decodisa_dadrL_N722 : STD_LOGIC; signal Inst_decodisa_dadrL_N721 : STD_LOGIC; - signal Inst_decodisa_dadrL_O_1_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N651 : STD_LOGIC; signal Inst_decodisa_dadrL_N650 : STD_LOGIC; signal Inst_decodisa_dadrL_O_0_Q : STD_LOGIC; signal Inst_decodisa_dadrL_N580 : STD_LOGIC; signal Inst_decodisa_dadrL_N579 : STD_LOGIC; signal Inst_decodisa_dadrL_N0 : STD_LOGIC; + signal clk_ref_BUFGP_IBUFG : STD_LOGIC; signal clk_speed_BUFGP_IBUFG : STD_LOGIC; + signal rst_BUFGP_IBUFG : STD_LOGIC; signal GSR : STD_LOGIC; - signal Inst_rxserie1_RCONF_REG_7_GSR_OR : STD_LOGIC; - signal Inst_rxserie1_RCONF_REG_0_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RFLAG_REG_2_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RFLAG_REG_1_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_0_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_0_GSR_OR : STD_LOGIC; signal Inst_rxserie1_FIFO1_wr_en_GSR_OR : STD_LOGIC; - signal Inst_rxserie1_RCONF_REG_6_GSR_OR : STD_LOGIC; - signal Inst_rxserie1_RCONF_REG_5_GSR_OR : STD_LOGIC; - signal Inst_rxserie1_RCONF_REG_4_GSR_OR : STD_LOGIC; - signal Inst_rxserie1_RCONF_REG_3_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_FIFO1_rd_en_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_6_GSR_OR : STD_LOGIC; - signal Inst_rxserie1_RCONF_REG_1_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_5_GSR_OR : STD_LOGIC; - signal Inst_rxserie1_RCONF_REG_2_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_4_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_3_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_2_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RFLAG_REG_1_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RFLAG_REG_3_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RCONF_REG_2_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RCONF_REG_7_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RCONF_REG_3_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RCONF_REG_5_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RCONF_REG_4_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_7_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RCONF_REG_6_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_6_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_5_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_4_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_3_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_2_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_1_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RCONF_REG_1_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RFLAG_REG_0_GSR_OR : STD_LOGIC; + signal Inst_txserie1_RCONF_REG_0_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_CNT_1_GSR_OR : STD_LOGIC; + signal Inst_txserie1_FIFO1_wr_en_GSR_OR : STD_LOGIC; + signal Inst_txserie1_FIFO1_rd_en_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_6_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_3_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RHR_5_GSR_OR : STD_LOGIC; @@ -1076,6 +1280,17 @@ architecture Structure of fpga is signal Inst_rxserie1_RC1_RXCNT_3_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RXCNT_2_GSR_OR : STD_LOGIC; signal Inst_rxserie1_RC1_RXCNT_0_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_ckout_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_9_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_8_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_0_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_1_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_2_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_3_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_4_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_5_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_6_GSR_OR : STD_LOGIC; + signal Inst_txserie1_CLOCK1_compteur_7_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_ckout_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_9_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_8_GSR_OR : STD_LOGIC; @@ -1087,6 +1302,33 @@ architecture Structure of fpga is signal Inst_rxserie1_CLOCK1_compteur_5_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_6_GSR_OR : STD_LOGIC; signal Inst_rxserie1_CLOCK1_compteur_7_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_THR_6_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_THR_5_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_THR_3_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TSR_0_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TSR_1_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_THR_4_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TXDONE1_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_WRITE1_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_WRITE2_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TXDATARDY_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_THR_7_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TXCLK_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TAG2_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TAG1_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TXPARITY_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TX_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TSR_7_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TSR_6_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TSR_5_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TSR_4_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TSR_3_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_TSR_2_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_THR_0_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_THR_1_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_THR_2_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_CNT_2_GSR_OR : STD_LOGIC; + signal Inst_txserie1_TX1_CNT_0_GSR_OR : STD_LOGIC; signal GTS : STD_LOGIC; signal bus_data_0_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal bus_data_1_IOBUF_OBUFT_GTS_AND : STD_LOGIC; @@ -1096,9 +1338,14 @@ architecture Structure of fpga is signal bus_data_5_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal bus_data_6_IOBUF_OBUFT_GTS_AND : STD_LOGIC; signal bus_data_7_IOBUF_OBUFT_GTS_AND : STD_LOGIC; - signal VCC : STD_LOGIC; + signal txout1_OBUF_GTS_TRI : STD_LOGIC; + signal irqtx_OBUF_GTS_TRI : STD_LOGIC; + signal irqrxFIFO_OBUF_GTS_TRI : STD_LOGIC; + signal irqrxRX_OBUF_GTS_TRI : STD_LOGIC; + signal irqrxERR_OBUF_GTS_TRI : STD_LOGIC; signal GND : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_0_T : STD_LOGIC; + signal VCC : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_7_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_6_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_5_T : STD_LOGIC; @@ -1107,29 +1354,64 @@ architecture Structure of fpga is signal NlwInverterSignal_Inst_rxserie1_I7_2_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_I7_1_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_wr_en_C : STD_LOGIC; - signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_rd_en_C : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_1_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_2_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_0_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RCONF_I1_1_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_7_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_6_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_5_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_4_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_3_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RCONF_I1_2_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RCONF_I1_0_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RCONF_I1_7_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RCONF_I1_6_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd2_C : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_1_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_2_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RCONF_I1_5_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_0_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RCONF_I1_4_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_7_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_6_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_5_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_4_T : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_3_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RCONF_I1_3_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd3_C : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd2_C : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd1_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd1_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_txload_G : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd4_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_FIFO1_wr_en_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_FIFO1_dready_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd3_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_FIFO1_rd_en_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_1_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_2_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd3_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_0_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_7_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_6_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_5_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_4_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_RFLAG_I1_3_T : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd1_C : STD_LOGIC; + signal NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd4_C : STD_LOGIC; signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C : STD_LOGIC; - signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C : STD_LOGIC; signal NLW_Inst_rxserie1_FIFO1_fifo0_BU161_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_rxserie1_FIFO1_fifo0_BU143_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_rxserie1_FIFO1_fifo0_BU137_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_rxserie1_FIFO1_fifo0_BU7_O_UNCONNECTED : STD_LOGIC; + signal NLW_Inst_txserie1_FIFO1_fifo0_BU161_O_UNCONNECTED : STD_LOGIC; + signal NLW_Inst_txserie1_FIFO1_fifo0_BU143_O_UNCONNECTED : STD_LOGIC; + signal NLW_Inst_txserie1_FIFO1_fifo0_BU137_O_UNCONNECTED : STD_LOGIC; + signal NLW_Inst_txserie1_FIFO1_fifo0_BU7_O_UNCONNECTED : STD_LOGIC; signal NLW_Inst_decodisa_dadrL_VCC_O_UNCONNECTED : STD_LOGIC; signal NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; signal NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; @@ -1147,30 +1429,49 @@ architecture Structure of fpga is signal NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; signal NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; signal NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; - signal cs : STD_LOGIC_VECTOR ( 3 downto 2 ); - signal Inst_rxserie1_CLOCK1_compteur_n0001 : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal Inst_rxserie1_CLOCK1_compteur_n0005 : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal Inst_rxserie1_RFLAG_REG : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal NlwInverterSignal_txout1_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_irqtx_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_irqrxFIFO_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_irqrxRX_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_irqrxERR_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal cs : STD_LOGIC_VECTOR ( 6 downto 1 ); + signal Inst_txserie1_TX1_CNT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal Inst_txserie1_TX1_THR : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal Inst_txserie1_TX1_CNT_n0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal Inst_txserie1_inter_data : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal Inst_txserie1_fifoLevel : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Inst_txserie1_RCONF_REG : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_rxserie1_RCONF_REG : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_rxserie1_inter_fifo : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_rxserie1_RC1_RHR : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_rxserie1_flagreg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Inst_txserie1_flagreg : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal Inst_rxserie1_RFLAG_output : STD_LOGIC_VECTOR ( 7 downto 7 ); + signal Inst_rxserie1_RFLAG_REG : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal Inst_txserie1_RFLAG_REG : STD_LOGIC_VECTOR ( 3 downto 0 ); signal Inst_rxserie1_RC1_n0018 : STD_LOGIC_VECTOR ( 3 downto 0 ); signal Inst_rxserie1_RC1_RSR : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Inst_rxserie1_RC1_n0040 : STD_LOGIC_VECTOR ( 3 downto 1 ); signal Inst_rxserie1_RC1_RXCNT : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Inst_txserie1_CLOCK1_compteur_n0005 : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal Inst_txserie1_CLOCK1_compteur : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal Inst_txserie1_CLOCK1_compteur_n0001 : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal Inst_rxserie1_CLOCK1_compteur_n0005 : STD_LOGIC_VECTOR ( 9 downto 0 ); signal Inst_rxserie1_CLOCK1_compteur : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal Inst_rxserie1_CLOCK1_compteur_n0001 : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal Inst_txserie1_TX1_TSR : STD_LOGIC_VECTOR ( 7 downto 0 ); begin - Inst_rxserie1_FIFO1_state_write_FFd1_In1 : X_LUT4 + Inst_txserie1_RFLAG_REG_2 : X_FF generic map( - INIT => X"FF04" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_FIFO1_state_write_FFd1, - ADR2 => Inst_rxserie1_rxread, - ADR3 => Inst_rxserie1_FIFO1_state_write_FFd2, - O => Inst_rxserie1_FIFO1_state_write_FFd1_In + I => Inst_txserie1_flagreg(2), + CE => Inst_txserie1_RFLAG_n0007, + RST => Inst_txserie1_RFLAG_REG_2_GSR_OR, + SET => Inst_txserie1_flagreg(2), + CLK => bus_clk, + O => Inst_txserie1_RFLAG_REG(2) ); Inst_decodisa_n00021 : X_LUT3 generic map( @@ -1182,9 +1483,30 @@ begin ADR2 => AEN_IBUF, O => bus_clk ); + Inst_txserie1_FIFO1_state_write_FFd1_In1 : X_LUT3 + generic map( + INIT => X"BA" + ) + port map ( + ADR0 => Inst_txserie1_FIFO1_state_write_FFd2, + ADR1 => N8727, + ADR2 => Inst_txserie1_FIFO1_state_write_FFd1, + O => Inst_txserie1_FIFO1_state_write_FFd1_In + ); XST_GND : X_ZERO port map ( - O => Inst_rxserie1_FIFO1_state_read_FFd2 + O => Inst_rxserie1_RFLAG_output(7) + ); + Inst_txserie1_TX1_n0019_SW0 : X_LUT4 + generic map( + INIT => X"DC8C" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0033, + ADR1 => Inst_txserie1_TX1_TSR(0), + ADR2 => Inst_txserie1_TX1_TSR(1), + ADR3 => Inst_txserie1_TX1_TXPARITY, + O => N14920 ); Inst_rxserie1_geneck1 : X_LUT2 generic map( @@ -1192,67 +1514,53 @@ begin ) port map ( ADR0 => Inst_rxserie1_RCONF_REG(4), - ADR1 => clk_ref_IBUF, + ADR1 => clk_ref_BUFGP, O => Inst_rxserie1_geneck ); - Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_2_1 : X_LUT4 - generic map( - INIT => X"10FE" - ) + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_5 : X_XOR2 port map ( - ADR0 => Inst_rxserie1_CLOCK1_n0005, - ADR1 => rst_IBUF, - ADR2 => Inst_rxserie1_CLOCK1_compteur_n0005(2), - ADR3 => Inst_rxserie1_RCONF_REG(1), - O => Inst_rxserie1_CLOCK1_compteur_n0001(2) + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, + O => Inst_rxserie1_CLOCK1_compteur_n0005(5) ); - Inst_rxserie1_FIFO1_state_write_FFd3_In1 : X_LUT4 + Inst_rxserie1_FIFO1_state_write_FFd2_In1 : X_LUT3 generic map( - INIT => X"EEE0" + INIT => X"04" ) port map ( ADR0 => Inst_rxserie1_rxread, - ADR1 => Inst_rxserie1_flagreg(2), - ADR2 => Inst_rxserie1_FIFO1_state_write_FFd1, - ADR3 => Inst_rxserie1_FIFO1_state_write_FFd3, - O => Inst_rxserie1_FIFO1_state_write_FFd3_In + ADR1 => Inst_rxserie1_FIFO1_state_write_FFd3, + ADR2 => Inst_rxserie1_flagreg(2), + O => Inst_rxserie1_FIFO1_state_write_FFd2_In ); - Inst_rxserie1_state_rx_read_FFd2_0 : X_FF + Inst_rxserie1_irqFIFO1 : X_LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - I => Inst_rxserie1_state_rx_read_FFd3, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_state_rx_read_FFd2, - CE => VCC, - SET => GND, - RST => GSR + ADR0 => Inst_rxserie1_flagreg(1), + ADR1 => Inst_rxserie1_flagreg(0), + O => irqrxFIFO_OBUF ); - Inst_rxserie1_state_rx_read_FFd1_In11 : X_LUT2 + irqrxRX1 : X_LUT2 generic map( - INIT => X"8" + INIT => X"5" ) port map ( - ADR0 => Inst_rxserie1_RC1_RXDATARDY, - ADR1 => Inst_rxserie1_state_rx_read_FFd1, - O => N11003 + ADR0 => Inst_rxserie1_flagreg(3), + O => irqrxRX_OBUF, + ADR1 => GND ); - Inst_rxserie1_RCONF_REG_7 : X_FF + Inst_rxserie1_irqERR1 : X_LUT4 generic map( - INIT => '0' + INIT => X"FFFE" ) port map ( - I => N11001, - CE => Inst_rxserie1_RCONF_n0007, - RST => Inst_rxserie1_RCONF_REG_7_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => bus_clk, - O => Inst_rxserie1_RCONF_REG(7) - ); - XST_VCC : X_ONE - port map ( - O => Inst_rxserie1_I7_N1369 + ADR0 => Inst_rxserie1_RC1_FRAMING_ERR, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_RC1_PARITY_ERR, + ADR3 => Inst_rxserie1_RC1_OVERRUN, + O => irqrxERR_OBUF ); Inst_rxserie1_I7_0 : X_TRI port map ( @@ -1260,38 +1568,28 @@ begin CTL => NlwInverterSignal_Inst_rxserie1_I7_0_T, O => bus_data_7_IOBUF ); - Inst_rxserie1_state_rx_read_FFd4_1 : X_SFF - generic map( - INIT => '1' - ) + XST_VCC : X_ONE port map ( - I => Inst_rxserie1_I7_N1369, - SRST => Inst_rxserie1_RC1_RXDATARDY, - CE => Inst_rxserie1_state_rx_read_FFd1, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_state_rx_read_FFd4, - SET => GSR, - RST => GND, - SSET => GND + O => N6239 ); - Inst_rxserie1_RCONF_REG_0 : X_FF + Inst_txserie1_RFLAG_REG_1 : X_FF generic map( INIT => '0' ) port map ( - I => N10987, - CE => Inst_rxserie1_RCONF_n0007, - RST => Inst_rxserie1_RCONF_REG_0_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, + I => Inst_txserie1_fifoLevel(1), + CE => Inst_txserie1_RFLAG_n0007, + RST => Inst_txserie1_RFLAG_REG_1_GSR_OR, + SET => Inst_txserie1_fifoLevel(1), CLK => bus_clk, - O => Inst_rxserie1_RCONF_REG(0) + O => Inst_txserie1_RFLAG_REG(1) ); - Inst_rxserie1_rxread_2 : X_SFF + Inst_rxserie1_rxread_0 : X_SFF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_I7_N1369, + I => N6239, SRST => Inst_rxserie1_state_rx_read_FFd2, CLK => Inst_rxserie1_CLOCK1_ckout, O => Inst_rxserie1_rxread, @@ -1300,7 +1598,7 @@ begin RST => GSR, SSET => GND ); - Inst_rxserie1_state_rx_read_FFd3_3 : X_FF + Inst_rxserie1_state_rx_read_FFd3_1 : X_FF generic map( INIT => '0' ) @@ -1312,10 +1610,10 @@ begin SET => GND, RST => GSR ); - Inst_rxserie1_RC1_Madd_n0040_inst_cy_10_4 : X_MUX2 + Inst_rxserie1_RC1_Madd_n0040_inst_cy_10_2 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_state_read_FFd2, - IA => Inst_rxserie1_I7_N1369, + IB => Inst_rxserie1_RFLAG_output(7), + IA => N6239, SEL => Inst_rxserie1_RC1_Madd_n0040_inst_lut2_10, O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10 ); @@ -1331,16 +1629,27 @@ begin CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(0) ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_5 : X_XOR2 + Inst_rxserie1_RCONF_REG_0 : X_FF + generic map( + INIT => '0' + ) port map ( - I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, - I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, - O => Inst_rxserie1_CLOCK1_compteur_n0005(5) + I => N15385, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_0_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(0) ); - bus_adr_3_IBUF_5 : X_BUF + Inst_rxserie1_I7_EnableTr_INV1 : X_LUT3 + generic map( + INIT => X"DF" + ) port map ( - I => bus_adr(3), - O => bus_adr_3_IBUF + ADR0 => cs(1), + ADR1 => rst_BUFGP, + ADR2 => rw, + O => Inst_rxserie1_I7_N1528 ); Inst_rxserie1_I7_7 : X_TRI port map ( @@ -1384,22 +1693,18 @@ begin CTL => NlwInverterSignal_Inst_rxserie1_I7_1_T, O => bus_data_6_IOBUF ); - Inst_rxserie1_FIFO1_state_write_FFd2_In1 : X_LUT3 + Inst_rxserie1_FIFO1_state_read_FFd3_In1 : X_LUT4 generic map( - INIT => X"04" + INIT => X"2000" ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_FIFO1_state_write_FFd3, - ADR2 => Inst_rxserie1_rxread, - O => Inst_rxserie1_FIFO1_state_write_FFd2_In - ); - bus_adr_2_IBUF_6 : X_BUF - port map ( - I => bus_adr(2), - O => bus_adr_2_IBUF + ADR0 => Inst_rxserie1_FIFO1_state_read_FFd4, + ADR1 => rst_BUFGP, + ADR2 => rw, + ADR3 => cs(1), + O => Inst_rxserie1_FIFO1_state_read_FFd3_In ); - Inst_rxserie1_FIFO1_wr_en_7 : X_FF + Inst_rxserie1_FIFO1_wr_en_3 : X_FF generic map( INIT => '0' ) @@ -1411,61 +1716,68 @@ begin CE => VCC, SET => GND ); - Inst_rxserie1_RCONF_REG_6 : X_FF + Inst_rxserie1_state_rx_read_FFd2_4 : X_FF generic map( INIT => '0' ) port map ( - I => N10999, - CE => Inst_rxserie1_RCONF_n0007, - RST => Inst_rxserie1_RCONF_REG_6_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => bus_clk, - O => Inst_rxserie1_RCONF_REG(6) + I => Inst_rxserie1_state_rx_read_FFd3, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_state_rx_read_FFd2, + CE => VCC, + SET => GND, + RST => GSR ); - Inst_rxserie1_FIFO1_state_read_FFd4_N14551 : X_LUT2 + Inst_rxserie1_FIFO1_state_read_FFd4_N16431 : X_LUT2 generic map( INIT => X"5" ) port map ( - ADR0 => rst_IBUF, - O => Inst_rxserie1_FIFO1_state_read_FFd4_N1455, + ADR0 => rst_BUFGP, + O => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, ADR1 => GND ); - Inst_rxserie1_FIFO1_state_write_FFd1_8 : X_FF + Inst_txserie1_FIFO1_state_write_FFd3_In1 : X_LUT3 generic map( - INIT => '0' + INIT => X"E0" ) port map ( - I => Inst_rxserie1_FIFO1_state_write_FFd1_In, - CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1455, - CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C, - O => Inst_rxserie1_FIFO1_state_write_FFd1, - SET => GND, - RST => GSR + ADR0 => Inst_txserie1_FIFO1_state_write_FFd3, + ADR1 => Inst_txserie1_FIFO1_state_write_FFd1, + ADR2 => N8727, + O => Inst_txserie1_FIFO1_state_write_FFd3_In ); - bus_adr_4_IBUF_9 : X_BUF + Inst_rxserie1_FIFO1_rd_en_5 : X_FF + generic map( + INIT => '0' + ) port map ( - I => bus_adr(4), - O => bus_adr_4_IBUF + I => Inst_rxserie1_FIFO1_state_read_FFd3_In, + RST => Inst_rxserie1_FIFO1_rd_en_GSR_OR, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_rd_en_C, + O => Inst_rxserie1_FIFO1_rd_en, + CE => VCC, + SET => GND ); - Inst_rxserie1_state_rx_read_FFd3_In1 : X_LUT2 + Inst_rxserie1_state_rx_read_FFd1_In11 : X_LUT2 generic map( INIT => X"8" ) port map ( ADR0 => Inst_rxserie1_RC1_RXDATARDY, - ADR1 => Inst_rxserie1_state_rx_read_FFd4, - O => Inst_rxserie1_state_rx_read_FFd3_In + ADR1 => Inst_rxserie1_state_rx_read_FFd1, + O => N15406 ); - Inst_rxserie1_RC1_RXCNT_2_rt_10 : X_LUT2 + Ker87251 : X_LUT4 generic map( - INIT => X"A" + INIT => X"FEFF" ) port map ( - ADR0 => Inst_rxserie1_RC1_RXCNT(2), - O => Inst_rxserie1_RC1_RXCNT_2_rt, - ADR1 => GND + ADR0 => IOW_IBUF, + ADR1 => AEN_IBUF, + ADR2 => rst_BUFGP, + ADR3 => cs(4), + O => N8727 ); Inst_rxserie1_RFLAG_I1_1 : X_TRI port map ( @@ -1479,37 +1791,28 @@ begin CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_2_T, O => bus_data_5_IOBUF ); - Inst_rxserie1_RCONF_REG_5 : X_FF + Inst_rxserie1_RFLAG_n00071 : X_LUT4 generic map( - INIT => '0' + INIT => X"FB00" ) port map ( - I => N10997, - CE => Inst_rxserie1_RCONF_n0007, - RST => Inst_rxserie1_RCONF_REG_5_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => bus_clk, - O => Inst_rxserie1_RCONF_REG(5) + ADR0 => IOR_IBUF, + ADR1 => IOW_IBUF, + ADR2 => AEN_IBUF, + ADR3 => cs(3), + O => Inst_rxserie1_RFLAG_n0007 ); Inst_rxserie1_RFLAG_I1_0 : X_TRI port map ( - I => Inst_rxserie1_FIFO1_state_read_FFd2, + I => Inst_rxserie1_RFLAG_output(7), CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_0_T, O => bus_data_7_IOBUF ); - Inst_rxserie1_state_rx_read_FFd1_11 : X_SFF - generic map( - INIT => '0' - ) + Inst_txserie1_RCONF_I1_1 : X_TRI port map ( - I => N11003, - SSET => Inst_rxserie1_state_rx_read_FFd2, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_state_rx_read_FFd1, - CE => VCC, - SET => GND, - RST => GSR, - SRST => GND + I => Inst_txserie1_RCONF_REG(6), + CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_1_T, + O => bus_data_6_IOBUF ); Inst_rxserie1_RFLAG_I1_EnableTr_INV1 : X_LUT3 generic map( @@ -1517,9 +1820,9 @@ begin ) port map ( ADR0 => cs(3), - ADR1 => rst_IBUF, + ADR1 => rst_BUFGP, ADR2 => rw, - O => Inst_rxserie1_RFLAG_I1_N1369 + O => Inst_rxserie1_RFLAG_I1_N1528 ); Inst_rxserie1_RFLAG_I1_7 : X_TRI port map ( @@ -1551,17 +1854,11 @@ begin CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_3_T, O => bus_data_4_IOBUF ); - Inst_rxserie1_RCONF_REG_4 : X_FF - generic map( - INIT => '0' - ) + Inst_txserie1_RCONF_I1_2 : X_TRI port map ( - I => N10995, - CE => Inst_rxserie1_RCONF_n0007, - RST => Inst_rxserie1_RCONF_REG_4_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => bus_clk, - O => Inst_rxserie1_RCONF_REG(4) + I => Inst_txserie1_RCONF_REG(5), + CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_2_T, + O => bus_data_5_IOBUF ); Inst_rxserie1_RFLAG_REG_6_n00001 : X_LUT2 generic map( @@ -1599,16 +1896,19 @@ begin O => Inst_rxserie1_RFLAG_REG_2_n0000, ADR1 => GND ); - Inst_rxserie1_RFLAG_REG_3_n00001 : X_LUT2 + Inst_rxserie1_FIFO1_state_write_FFd1_6 : X_FF generic map( - INIT => X"5" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_flagreg(3), - O => Inst_rxserie1_RFLAG_REG_3_n0000, - ADR1 => GND - ); - Inst_rxserie1_RFLAG_REG_4_n00001 : X_LUT2 + I => Inst_rxserie1_FIFO1_state_write_FFd1_In, + CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C, + O => Inst_rxserie1_FIFO1_state_write_FFd1, + SET => GND, + RST => GSR + ); + Inst_rxserie1_RFLAG_REG_4_n00001 : X_LUT2 generic map( INIT => X"5" ) @@ -1626,22 +1926,25 @@ begin O => Inst_rxserie1_RFLAG_REG_5_n0000, ADR1 => GND ); - Inst_rxserie1_RCONF_REG_3 : X_FF - generic map( - INIT => '0' - ) + Inst_txserie1_RCONF_I1_0 : X_TRI port map ( - I => N10993, - CE => Inst_rxserie1_RCONF_n0007, - RST => Inst_rxserie1_RCONF_REG_3_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => bus_clk, - O => Inst_rxserie1_RCONF_REG(3) + I => Inst_txserie1_RCONF_REG(7), + CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_0_T, + O => bus_data_7_IOBUF ); - bus_adr_1_IBUF_12 : X_BUF + Inst_rxserie1_state_rx_read_FFd4_7 : X_SFF + generic map( + INIT => '1' + ) port map ( - I => bus_adr(1), - O => bus_adr_1_IBUF + I => N6239, + SRST => Inst_rxserie1_RC1_RXDATARDY, + CE => Inst_rxserie1_state_rx_read_FFd1, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_state_rx_read_FFd4, + SET => GSR, + RST => GND, + SSET => GND ); Inst_rxserie1_RFLAG_REG_6 : X_FF generic map( @@ -1655,17 +1958,14 @@ begin CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(6) ); - Inst_rxserie1_RCONF_REG_1 : X_FF + Inst_rxserie1_state_rx_read_FFd3_In1 : X_LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - I => N10989, - CE => Inst_rxserie1_RCONF_n0007, - RST => Inst_rxserie1_RCONF_REG_1_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => bus_clk, - O => Inst_rxserie1_RCONF_REG(1) + ADR0 => Inst_rxserie1_RC1_RXDATARDY, + ADR1 => Inst_rxserie1_state_rx_read_FFd4, + O => Inst_rxserie1_state_rx_read_FFd3_In ); Inst_rxserie1_RFLAG_REG_5 : X_FF generic map( @@ -1679,17 +1979,15 @@ begin CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(5) ); - Inst_rxserie1_RCONF_REG_2 : X_FF + Inst_txserie1_RCONF_I1_EnableTr_INV1 : X_LUT3 generic map( - INIT => '0' + INIT => X"DF" ) port map ( - I => N10991, - CE => Inst_rxserie1_RCONF_n0007, - RST => Inst_rxserie1_RCONF_REG_2_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => bus_clk, - O => Inst_rxserie1_RCONF_REG(2) + ADR0 => cs(5), + ADR1 => rst_BUFGP, + ADR2 => rw, + O => Inst_txserie1_RCONF_I1_N1528 ); Inst_rxserie1_RFLAG_REG_4 : X_FF generic map( @@ -1703,10 +2001,11 @@ begin CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(4) ); - bus_adr_6_IBUF_13 : X_BUF + Inst_txserie1_RCONF_I1_7 : X_TRI port map ( - I => bus_adr(6), - O => bus_adr_6_IBUF + I => Inst_txserie1_RCONF_REG(0), + CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_7_T, + O => bus_data_0_IOBUF ); Inst_rxserie1_RFLAG_REG_3 : X_FF generic map( @@ -1720,10 +2019,11 @@ begin CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(3) ); - bus_adr_7_IBUF_14 : X_BUF + Inst_txserie1_RCONF_I1_6 : X_TRI port map ( - I => bus_adr(7), - O => bus_adr_7_IBUF + I => Inst_txserie1_RCONF_REG(1), + CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_6_T, + O => bus_data_1_IOBUF ); Inst_rxserie1_RFLAG_REG_2 : X_FF generic map( @@ -1737,10 +2037,17 @@ begin CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(2) ); - bus_adr_5_IBUF_15 : X_BUF + Inst_rxserie1_FIFO1_state_write_FFd2_8 : X_FF + generic map( + INIT => '0' + ) port map ( - I => bus_adr(5), - O => bus_adr_5_IBUF + I => Inst_rxserie1_FIFO1_state_write_FFd2_In, + CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C, + O => Inst_rxserie1_FIFO1_state_write_FFd2, + SET => GND, + RST => GSR ); Inst_rxserie1_RFLAG_REG_1 : X_FF generic map( @@ -1754,12 +2061,31 @@ begin CLK => bus_clk, O => Inst_rxserie1_RFLAG_REG(1) ); - bus_adr_8_IBUF_16 : X_BUF + Inst_txserie1_RFLAG_REG_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_flagreg(3), + CE => Inst_txserie1_RFLAG_n0007, + RST => Inst_txserie1_RFLAG_REG_3_GSR_OR, + SET => Inst_txserie1_flagreg(3), + CLK => bus_clk, + O => Inst_txserie1_RFLAG_REG(3) + ); + Inst_txserie1_FIFO1_state_write_FFd2_9 : X_FF + generic map( + INIT => '0' + ) port map ( - I => bus_adr(8), - O => bus_adr_8_IBUF + I => Inst_txserie1_FIFO1_state_write_FFd2_In, + CE => Inst_txserie1_FIFO1_dready_N1514, + CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd2_C, + O => Inst_txserie1_FIFO1_state_write_FFd2, + SET => GND, + RST => GSR ); - Inst_rxserie1_RFLAG_n00071 : X_LUT4 + Inst_txserie1_RCONF_n00071 : X_LUT4 generic map( INIT => X"FB00" ) @@ -1767,8 +2093,8 @@ begin ADR0 => IOR_IBUF, ADR1 => IOW_IBUF, ADR2 => AEN_IBUF, - ADR3 => cs(3), - O => Inst_rxserie1_RFLAG_n0007 + ADR3 => cs(5), + O => Inst_txserie1_RCONF_n0007 ); Inst_rxserie1_RCONF_I1_1 : X_TRI port map ( @@ -1782,16 +2108,11 @@ begin CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_2_T, O => bus_data_5_IOBUF ); - N48051 : X_LUT4 - generic map( - INIT => X"CFDF" - ) + Inst_txserie1_RCONF_I1_5 : X_TRI port map ( - ADR0 => cs(3), - ADR1 => rst_IBUF, - ADR2 => rw, - ADR3 => cs(2), - O => N4805 + I => Inst_txserie1_RCONF_REG(2), + CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_5_T, + O => bus_data_2_IOBUF ); Inst_rxserie1_RCONF_I1_0 : X_TRI port map ( @@ -1799,16 +2120,11 @@ begin CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_0_T, O => bus_data_7_IOBUF ); - Inst_rxserie1_RCONF_n00071 : X_LUT4 - generic map( - INIT => X"FB00" - ) + Inst_txserie1_RCONF_I1_4 : X_TRI port map ( - ADR0 => IOR_IBUF, - ADR1 => IOW_IBUF, - ADR2 => AEN_IBUF, - ADR3 => cs(2), - O => Inst_rxserie1_RCONF_n0007 + I => Inst_txserie1_RCONF_REG(3), + CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_4_T, + O => bus_data_3_IOBUF ); Inst_rxserie1_RCONF_I1_EnableTr_INV1 : X_LUT3 generic map( @@ -1816,9 +2132,9 @@ begin ) port map ( ADR0 => cs(2), - ADR1 => rst_IBUF, + ADR1 => rst_BUFGP, ADR2 => rw, - O => Inst_rxserie1_RCONF_I1_N1369 + O => Inst_rxserie1_RCONF_I1_N1528 ); Inst_rxserie1_RCONF_I1_7 : X_TRI port map ( @@ -1850,2404 +2166,5338 @@ begin CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_3_T, O => bus_data_4_IOBUF ); - Inst_rxserie1_FIFO1_state_write_FFd3_17 : X_FF - generic map( - INIT => '1' - ) + Inst_txserie1_RCONF_I1_3 : X_TRI port map ( - I => Inst_rxserie1_FIFO1_state_write_FFd3_In, - CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1455, - CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C, - O => Inst_rxserie1_FIFO1_state_write_FFd3, - SET => GSR, - RST => GND + I => Inst_txserie1_RCONF_REG(4), + CTL => NlwInverterSignal_Inst_txserie1_RCONF_I1_3_T, + O => bus_data_4_IOBUF ); - Inst_rxserie1_FIFO1_state_write_FFd2_18 : X_FF + Inst_rxserie1_state_rx_read_FFd1_10 : X_SFF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_FIFO1_state_write_FFd2_In, - CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1455, - CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C, - O => Inst_rxserie1_FIFO1_state_write_FFd2, + I => N15406, + SSET => Inst_rxserie1_state_rx_read_FFd2, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_state_rx_read_FFd1, + CE => VCC, SET => GND, - RST => GSR + RST => GSR, + SRST => GND ); - Inst_rxserie1_CLOCK1_compteur_2_n00001 : X_LUT2 + txout1_OBUF : X_BUF + port map ( + I => Inst_txserie1_TX1_TX, + O => txout1_OBUF_GTS_TRI + ); + Inst_txserie1_RCONF_REG_2 : X_FF generic map( - INIT => X"8" + INIT => '0' ) port map ( - ADR0 => rst_IBUF, - ADR1 => Inst_rxserie1_RCONF_REG(1), - O => Inst_rxserie1_CLOCK1_compteur_0_2_n0000 + I => N15389, + CE => Inst_txserie1_RCONF_n0007, + RST => Inst_txserie1_RCONF_REG_2_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_txserie1_RCONF_REG(2) ); - Inst_rxserie1_CLOCK1_n000539_SW0 : X_LUT4 + Inst_txserie1_RCONF_REG_7 : X_FF generic map( - INIT => X"FFFE" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(6), - ADR1 => Inst_rxserie1_CLOCK1_compteur(7), - ADR2 => Inst_rxserie1_CLOCK1_compteur(8), - ADR3 => Inst_rxserie1_CLOCK1_compteur(9), - O => N11021 + I => N15399, + CE => Inst_txserie1_RCONF_n0007, + RST => Inst_txserie1_RCONF_REG_7_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_txserie1_RCONF_REG(7) ); - Inst_decodisa_n00031 : X_LUT3 + Inst_txserie1_RCONF_REG_3 : X_FF generic map( - INIT => X"04" + INIT => '0' ) port map ( - ADR0 => IOR_IBUF, - ADR1 => IOW_IBUF, - ADR2 => AEN_IBUF, - O => rw + I => N15391, + CE => Inst_txserie1_RCONF_n0007, + RST => Inst_txserie1_RCONF_REG_3_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_txserie1_RCONF_REG(3) ); - Inst_rxserie1_RC1_Madd_n0040_inst_cy_12_19 : X_MUX2 + Inst_txserie1_RCONF_REG_5 : X_FF + generic map( + INIT => '0' + ) port map ( - IB => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11, - IA => Inst_rxserie1_FIFO1_state_read_FFd2, - SEL => Inst_rxserie1_RC1_RXCNT_2_rt, - O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_12 + I => N15395, + CE => Inst_txserie1_RCONF_n0007, + RST => Inst_txserie1_RCONF_REG_5_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_txserie1_RCONF_REG(5) ); - Inst_rxserie1_RC1_Madd_n0040_inst_sum_12 : X_XOR2 + Inst_txserie1_RCONF_REG_4 : X_FF + generic map( + INIT => '0' + ) port map ( - I0 => Inst_rxserie1_RC1_RXCNT_2_rt, - I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11, - O => Inst_rxserie1_RC1_n0040(2) + I => N15393, + CE => Inst_txserie1_RCONF_n0007, + RST => Inst_txserie1_RCONF_REG_4_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_txserie1_RCONF_REG(4) ); - Inst_rxserie1_RC1_n00631 : X_LUT4 + Inst_rxserie1_RCONF_REG_7 : X_FF generic map( - INIT => X"44F4" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_READ2, - ADR1 => Inst_rxserie1_RC1_READ1, - ADR2 => Inst_rxserie1_RC1_IDLE, - ADR3 => Inst_rxserie1_RC1_IDLE1, - O => Inst_rxserie1_RC1_n0063 + I => N15399, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_7_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(7) ); - Inst_rxserie1_RC1_n00621 : X_LUT3 + Inst_txserie1_RCONF_REG_6 : X_FF generic map( - INIT => X"BA" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_N7296, - ADR1 => Inst_rxserie1_RC1_READ2, - ADR2 => Inst_rxserie1_RC1_READ1, - O => Inst_rxserie1_RC1_n0062 + I => N15397, + CE => Inst_txserie1_RCONF_n0007, + RST => Inst_txserie1_RCONF_REG_6_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_txserie1_RCONF_REG(6) ); - Inst_rxserie1_RC1_Ker72941 : X_LUT3 + Inst_rxserie1_RCONF_REG_6 : X_FF generic map( - INIT => X"04" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE1, - ADR1 => Inst_rxserie1_RC1_IDLE, - ADR2 => Inst_rxserie1_RC1_RXDATARDY, - O => Inst_rxserie1_RC1_N7296 + I => N15397, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_6_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(6) ); - Inst_rxserie1_RC1_RXCNT_1_rt_20 : X_LUT2 + Inst_rxserie1_FIFO1_state_read_FFd3_11 : X_FF generic map( - INIT => X"A" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_RXCNT(1), - O => Inst_rxserie1_RC1_RXCNT_1_rt, - ADR1 => GND + I => Inst_rxserie1_FIFO1_state_read_FFd3_In, + CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd3_C, + O => Inst_rxserie1_FIFO1_state_read_FFd3, + SET => GND, + RST => GSR ); - Inst_rxserie1_RC1_n00501 : X_LUT3 + Inst_rxserie1_RCONF_REG_5 : X_FF generic map( - INIT => X"EF" + INIT => '0' ) port map ( - ADR0 => rxin1_IBUF, - ADR1 => Inst_rxserie1_RC1_RX1, - ADR2 => Inst_rxserie1_RC1_IDLE, - O => Inst_rxserie1_RC1_n0050 + I => N15395, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_5_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(5) ); - Inst_rxserie1_RC1_RHR_6 : X_FF + Inst_rxserie1_FIFO1_state_read_FFd2_12 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_RSR(6), - CE => Inst_rxserie1_RC1_N7296, - RST => Inst_rxserie1_RC1_RHR_6_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RHR(6), - SET => GND + I => Inst_rxserie1_FIFO1_state_read_FFd3, + CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd2_C, + O => Inst_rxserie1_FIFO1_state_read_FFd2, + SET => GND, + RST => GSR ); - Inst_rxserie1_RC1_RHR_3 : X_FF + Inst_rxserie1_RCONF_REG_4 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_RSR(3), - CE => Inst_rxserie1_RC1_N7296, - RST => Inst_rxserie1_RC1_RHR_3_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RHR(3), - SET => GND + I => N15393, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_4_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(4) ); - Inst_rxserie1_RC1_RHR_5 : X_FF + Inst_rxserie1_FIFO1_state_read_FFd1_13 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_RSR(5), - CE => Inst_rxserie1_RC1_N7296, - RST => Inst_rxserie1_RC1_RHR_5_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RHR(5), - SET => GND + I => Inst_rxserie1_FIFO1_state_read_FFd1_In, + CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd1_C, + O => Inst_rxserie1_FIFO1_state_read_FFd1, + SET => GND, + RST => GSR ); - Inst_rxserie1_RC1_RHR_4 : X_FF + Inst_rxserie1_RCONF_REG_3 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_RSR(4), - CE => Inst_rxserie1_RC1_N7296, - RST => Inst_rxserie1_RC1_RHR_4_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RHR(4), - SET => GND + I => N15391, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_3_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(3) ); - Inst_rxserie1_RC1_RHR_0 : X_FF + Inst_rxserie1_FIFO1_state_read_FFd4_In1 : X_LUT4 generic map( - INIT => '0' + INIT => X"AAA8" ) port map ( - I => Inst_rxserie1_RC1_RSR(0), - CE => Inst_rxserie1_RC1_N7296, - RST => Inst_rxserie1_RC1_RHR_0_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RHR(0), - SET => GND + ADR0 => Inst_rxserie1_I7_N1528, + ADR1 => Inst_rxserie1_FIFO1_state_read_FFd2, + ADR2 => Inst_rxserie1_FIFO1_state_read_FFd4, + ADR3 => Inst_rxserie1_FIFO1_state_read_FFd1, + O => Inst_rxserie1_FIFO1_state_read_FFd4_In ); - Inst_rxserie1_RC1_RHR_2 : X_FF + Inst_rxserie1_RCONF_REG_2 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_RSR(2), - CE => Inst_rxserie1_RC1_N7296, - RST => Inst_rxserie1_RC1_RHR_2_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RHR(2), - SET => GND + I => N15389, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_2_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(2) ); - Inst_rxserie1_RC1_RHR_1 : X_FF + Inst_txserie1_FIFO1_state_write_FFd1_14 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_RSR(1), - CE => Inst_rxserie1_RC1_N7296, - RST => Inst_rxserie1_RC1_RHR_1_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RHR(1), - SET => GND - ); - Inst_rxserie1_RC1_n00411 : X_LUT3 - generic map( - INIT => X"A2" - ) - port map ( - ADR0 => Inst_rxserie1_RC1_RXDATARDY, - ADR1 => Inst_rxserie1_RC1_READ1, - ADR2 => Inst_rxserie1_RC1_READ2, - O => Inst_rxserie1_RC1_n0041 + I => Inst_txserie1_FIFO1_state_write_FFd1_In, + CE => Inst_txserie1_FIFO1_dready_N1514, + CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd1_C, + O => Inst_txserie1_FIFO1_state_write_FFd1, + SET => GND, + RST => GSR ); - Inst_rxserie1_RC1_READ2_21 : X_FF + Inst_rxserie1_RCONF_REG_1 : X_FF generic map( - INIT => '1' + INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_READ1, - SET => Inst_rxserie1_RC1_READ2_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_READ2, - CE => VCC, - RST => GND + I => N15387, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_1_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(1) ); - Inst_rxserie1_RC1_n00311 : X_LUT2 + Inst_txserie1_RCONF_REG_1 : X_FF generic map( - INIT => X"D" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_READ1, - ADR1 => Inst_rxserie1_RC1_READ2, - O => Inst_rxserie1_RC1_n0031 + I => N15387, + CE => Inst_txserie1_RCONF_n0007, + RST => Inst_txserie1_RCONF_REG_1_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_txserie1_RCONF_REG(1) ); - Inst_rxserie1_RC1_n0018_1_1 : X_LUT3 + Inst_txserie1_TX1_n003410 : X_LUT4 generic map( - INIT => X"A2" + INIT => X"FFFE" ) port map ( - ADR0 => Inst_rxserie1_RC1_n0040(1), - ADR1 => Inst_rxserie1_RC1_IDLE, - ADR2 => Inst_rxserie1_RC1_HUNT, - O => Inst_rxserie1_RC1_n0018(1) + ADR0 => Inst_txserie1_TX1_TAG2, + ADR1 => Inst_txserie1_TX1_TAG1, + ADR2 => Inst_txserie1_TX1_TSR(7), + ADR3 => Inst_txserie1_TX1_TSR(6), + O => CHOICE144 ); - Inst_rxserie1_RC1_n00361 : X_LUT3 + Inst_rxserie1_CLOCK1_n000539 : X_LUT4 generic map( - INIT => X"40" + INIT => X"0100" ) port map ( - ADR0 => rxin1_IBUF, - ADR1 => Inst_rxserie1_RC1_IDLE, - ADR2 => Inst_rxserie1_RC1_RX1, - O => Inst_rxserie1_RC1_n0036 + ADR0 => Inst_rxserie1_CLOCK1_compteur(0), + ADR1 => Inst_rxserie1_CLOCK1_compteur(1), + ADR2 => N15425, + ADR3 => CHOICE135, + O => Inst_rxserie1_CLOCK1_n0005 ); - Inst_rxserie1_RC1_n00351 : X_LUT3 + Inst_txserie1_state_txload_2_SW18 : X_LUT4 generic map( - INIT => X"51" + INIT => X"EA00" ) port map ( - ADR0 => Inst_rxserie1_RC1_RXSTOP, - ADR1 => Inst_rxserie1_RC1_READ1, - ADR2 => Inst_rxserie1_RC1_READ2, - O => Inst_rxserie1_RC1_n0035 + ADR0 => Inst_txserie1_state_txload_2_Q, + ADR1 => Inst_txserie1_FIFO1_dready, + ADR2 => Inst_txserie1_state_txload_0_Q, + ADR3 => CHOICE41, + O => Inst_txserie1_state_txload_2_Q ); - Inst_rxserie1_RC1_n00341 : X_LUT3 + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_2_1 : X_LUT4 generic map( - INIT => X"A2" + INIT => X"10FE" ) port map ( - ADR0 => Inst_rxserie1_RC1_PARITYGEN, - ADR1 => Inst_rxserie1_RC1_READ1, - ADR2 => Inst_rxserie1_RC1_READ2, - O => Inst_rxserie1_RC1_n0034 - ); - Inst_rxserie1_RC1_Madd_n0040_inst_cy_11_22 : X_MUX2 - port map ( - IB => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10, - IA => Inst_rxserie1_FIFO1_state_read_FFd2, - SEL => Inst_rxserie1_RC1_RXCNT_1_rt, - O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11 + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => rst_BUFGP, + ADR2 => Inst_rxserie1_CLOCK1_compteur_n0005(2), + ADR3 => Inst_rxserie1_RCONF_REG(1), + O => Inst_rxserie1_CLOCK1_compteur_n0001(2) ); - Inst_rxserie1_RC1_n00291 : X_LUT2 + Inst_rxserie1_RCONF_n00071 : X_LUT4 generic map( - INIT => X"E" + INIT => X"FB00" ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => Inst_rxserie1_RC1_RSR(1), - O => Inst_rxserie1_RC1_n0029 + ADR0 => IOR_IBUF, + ADR1 => IOW_IBUF, + ADR2 => AEN_IBUF, + ADR3 => cs(2), + O => Inst_rxserie1_RCONF_n0007 ); - Inst_rxserie1_RC1_n00281 : X_LUT2 + Inst_rxserie1_RC1_n0018_0_1 : X_LUT3 generic map( - INIT => X"E" + INIT => X"75" ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => Inst_rxserie1_RC1_RSR(2), - O => Inst_rxserie1_RC1_n0028 + ADR0 => Inst_rxserie1_RC1_RXCNT(0), + ADR1 => Inst_rxserie1_RC1_HUNT, + ADR2 => Inst_rxserie1_RC1_IDLE, + O => Inst_rxserie1_RC1_n0018(0) ); - Inst_rxserie1_RC1_n00271 : X_LUT2 + Inst_txserie1_FIFO1_state_write_FFd2_In1 : X_LUT2 generic map( - INIT => X"E" + INIT => X"4" ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => Inst_rxserie1_RC1_RSR(3), - O => Inst_rxserie1_RC1_n0027 + ADR0 => N8727, + ADR1 => Inst_txserie1_FIFO1_state_write_FFd3, + O => Inst_txserie1_FIFO1_state_write_FFd2_In ); - Inst_rxserie1_RC1_n00261 : X_LUT2 + Inst_txserie1_minIRQ1 : X_LUT2 generic map( - INIT => X"E" + INIT => X"8" ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => Inst_rxserie1_RC1_RSR(4), - O => Inst_rxserie1_RC1_n0026 + ADR0 => Inst_txserie1_flagreg(2), + ADR1 => Inst_txserie1_RCONF_REG(2), + O => irqtx_OBUF ); - Inst_rxserie1_RC1_n00251 : X_LUT2 + Inst_txserie1_fifopurge1 : X_LUT2 generic map( INIT => X"E" ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => Inst_rxserie1_RC1_RSR(5), - O => Inst_rxserie1_RC1_n0025 + ADR0 => rst_BUFGP, + ADR1 => Inst_txserie1_RCONF_REG(3), + O => Inst_txserie1_fifopurge ); - Inst_rxserie1_RC1_n00241 : X_LUT2 + Inst_txserie1_txload_15 : X_LATCHE generic map( - INIT => X"E" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => Inst_rxserie1_RC1_RSR(6), - O => Inst_rxserie1_RC1_n0024 + I => Inst_txserie1_n0010, + CLK => NlwInverterSignal_Inst_txserie1_txload_G, + O => Inst_txserie1_txload, + GE => VCC, + SET => GND, + RST => GSR ); - Inst_rxserie1_RC1_n00231 : X_LUT2 + Inst_txserie1_RFLAG_REG_0 : X_FF generic map( - INIT => X"E" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => Inst_rxserie1_RC1_RSR(7), - O => Inst_rxserie1_RC1_n0023 + I => Inst_txserie1_fifoLevel(0), + CE => Inst_txserie1_RFLAG_n0007, + RST => Inst_txserie1_RFLAG_REG_0_GSR_OR, + SET => Inst_txserie1_fifoLevel(0), + CLK => bus_clk, + O => Inst_txserie1_RFLAG_REG(0) ); - Inst_rxserie1_RC1_n00221 : X_LUT2 + Inst_txserie1_RCONF_REG_0 : X_FF generic map( - INIT => X"E" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => Inst_rxserie1_RC1_RXPARITY, - O => Inst_rxserie1_RC1_n0022 + I => N15385, + CE => Inst_txserie1_RCONF_n0007, + RST => Inst_txserie1_RCONF_REG_0_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => bus_clk, + O => Inst_txserie1_RCONF_REG(0) ); - Inst_rxserie1_RC1_n00211 : X_LUT2 + Inst_txserie1_TX1_CNT_1 : X_FF generic map( - INIT => X"4" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => rxin1_IBUF, - O => Inst_rxserie1_RC1_n0021 + I => Inst_txserie1_TX1_CNT_n0000(1), + RST => Inst_txserie1_TX1_CNT_1_GSR_OR, + CLK => Inst_txserie1_CLOCK1_ckout, + O => Inst_txserie1_TX1_CNT(1), + CE => VCC, + SET => GND ); - Inst_rxserie1_RC1_n00201 : X_LUT3 + Inst_rxserie1_FIFO1_state_read_FFd4_16 : X_FF generic map( - INIT => X"F6" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_RC1_RXSTOP, - ADR1 => Inst_rxserie1_RC1_PARITYGEN, - ADR2 => Inst_rxserie1_RC1_IDLE, - O => Inst_rxserie1_RC1_n0020 + I => Inst_rxserie1_FIFO1_state_read_FFd4_In, + CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd4_C, + O => Inst_rxserie1_FIFO1_state_read_FFd4, + SET => GSR, + RST => GND ); - Inst_rxserie1_RC1_n00191 : X_LUT2 - generic map( - INIT => X"E" - ) + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_5 : X_XOR2 port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => Inst_rxserie1_RC1_RXSTOP, - O => Inst_rxserie1_RC1_n0019 + I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, + I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, + O => Inst_txserie1_CLOCK1_compteur_n0005(5) ); - Inst_rxserie1_RC1_n00511 : X_LUT3 + Inst_txserie1_FIFO1_dready_N15141 : X_LUT2 generic map( - INIT => X"DF" + INIT => X"1" ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => rxin1_IBUF, - ADR2 => Inst_rxserie1_RC1_RX1, - O => Inst_rxserie1_RC1_n0051 - ); - Inst_rxserie1_RC1_Madd_n0040_inst_sum_11 : X_XOR2 - port map ( - I0 => Inst_rxserie1_RC1_RXCNT_1_rt, - I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10, - O => Inst_rxserie1_RC1_n0040(1) + ADR0 => rst_BUFGP, + ADR1 => Inst_txserie1_RCONF_REG(3), + O => Inst_txserie1_FIFO1_dready_N1514 ); - Inst_rxserie1_RC1_n0018_2_1 : X_LUT3 + Inst_txserie1_FIFO1_wr_en_17 : X_FF generic map( - INIT => X"A2" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_n0040(2), - ADR1 => Inst_rxserie1_RC1_IDLE, - ADR2 => Inst_rxserie1_RC1_HUNT, - O => Inst_rxserie1_RC1_n0018(2) + I => Inst_txserie1_FIFO1_state_write_FFd2_In, + RST => Inst_txserie1_FIFO1_wr_en_GSR_OR, + CLK => NlwInverterSignal_Inst_txserie1_FIFO1_wr_en_C, + O => Inst_txserie1_FIFO1_wr_en, + CE => VCC, + SET => GND ); - Inst_rxserie1_RC1_n0018_3_1 : X_LUT3 + Inst_txserie1_FIFO1_dready_18 : X_FF generic map( - INIT => X"A2" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_RC1_n0040(3), - ADR1 => Inst_rxserie1_RC1_IDLE, - ADR2 => Inst_rxserie1_RC1_HUNT, - O => Inst_rxserie1_RC1_n0018(3) + I => Inst_txserie1_FIFO1_state_read_FFd3, + CE => Inst_txserie1_FIFO1_dready_N1514, + CLK => NlwInverterSignal_Inst_txserie1_FIFO1_dready_C, + O => Inst_txserie1_FIFO1_dready, + SET => GND, + RST => GSR ); - Inst_rxserie1_RC1_IDLE1_23 : X_FF + Inst_txserie1_FIFO1_state_write_FFd3_19 : X_FF generic map( INIT => '1' ) port map ( - I => Inst_rxserie1_RC1_IDLE, - SET => Inst_rxserie1_RC1_IDLE1_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_IDLE1, - CE => VCC, + I => Inst_txserie1_FIFO1_state_write_FFd3_In, + CE => Inst_txserie1_FIFO1_dready_N1514, + CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd3_C, + O => Inst_txserie1_FIFO1_state_write_FFd3, + SET => GSR, RST => GND ); - Inst_rxserie1_RC1_n00151 : X_LUT2 + Inst_rxserie1_FIFO1_state_write_FFd1_In1 : X_LUT4 generic map( - INIT => X"1" + INIT => X"FF10" ) port map ( - ADR0 => Inst_rxserie1_RC1_IDLE, - ADR1 => Inst_rxserie1_RC1_RSR(0), - O => Inst_rxserie1_RC1_n0015 + ADR0 => Inst_rxserie1_rxread, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_state_write_FFd1, + ADR3 => Inst_rxserie1_FIFO1_state_write_FFd2, + O => Inst_rxserie1_FIFO1_state_write_FFd1_In ); - Inst_rxserie1_RC1_READ1_24 : X_FF + Inst_txserie1_FIFO1_rd_en_20 : X_FF generic map( - INIT => '1' + INIT => '0' ) port map ( - I => Inst_rxserie1_rxread, - SET => Inst_rxserie1_RC1_READ1_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_READ1, + I => Inst_txserie1_FIFO1_state_read_FFd3_In, + RST => Inst_txserie1_FIFO1_rd_en_GSR_OR, + CLK => NlwInverterSignal_Inst_txserie1_FIFO1_rd_en_C, + O => Inst_txserie1_FIFO1_rd_en, CE => VCC, - RST => GND + SET => GND ); - Inst_rxserie1_RC1_IDLE_25 : X_FF + Inst_rxserie1_FIFO1_state_write_FFd3_In1 : X_LUT4 generic map( - INIT => '1' + INIT => X"EEE0" ) port map ( - I => Inst_rxserie1_RC1_n0015, - SET => Inst_rxserie1_RC1_IDLE_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_IDLE, - CE => VCC, - RST => GND + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_rxread, + ADR2 => Inst_rxserie1_FIFO1_state_write_FFd1, + ADR3 => Inst_rxserie1_FIFO1_state_write_FFd3, + O => Inst_rxserie1_FIFO1_state_write_FFd3_In ); - Inst_rxserie1_RC1_HUNT_26 : X_FF + Inst_txserie1_n00101 : X_LUT3 generic map( - INIT => '0' + INIT => X"04" ) port map ( - I => Inst_rxserie1_RC1_n0036, - CE => Inst_rxserie1_RC1_n0050, - RST => Inst_rxserie1_RC1_HUNT_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_HUNT, - SET => GND + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_state_txload_2_Q, + ADR2 => Inst_txserie1_TX1_TXDATARDY, + O => Inst_txserie1_n0010 ); - Inst_rxserie1_RC1_RXCNT_1 : X_FF - generic map( - INIT => '0' - ) + Inst_txserie1_RFLAG_I1_1 : X_TRI port map ( - I => Inst_rxserie1_RC1_n0018(1), - CE => Inst_rxserie1_RC1_n0051, - RST => Inst_rxserie1_RC1_RXCNT_1_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RXCNT(1), - SET => GND + I => Inst_rxserie1_RFLAG_output(7), + CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_1_T, + O => bus_data_6_IOBUF + ); + Inst_txserie1_RFLAG_I1_2 : X_TRI + port map ( + I => Inst_rxserie1_RFLAG_output(7), + CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_2_T, + O => bus_data_5_IOBUF ); - Inst_rxserie1_RC1_RX1_27 : X_FF + Inst_txserie1_FIFO1_state_read_FFd3_21 : X_FF generic map( - INIT => '1' + INIT => '0' ) port map ( - I => rxin1_IBUF, - SET => Inst_rxserie1_RC1_RX1_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RX1, - CE => VCC, - RST => GND + I => Inst_txserie1_FIFO1_state_read_FFd3_In, + CE => Inst_txserie1_FIFO1_dready_N1514, + CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd3_C, + O => Inst_txserie1_FIFO1_state_read_FFd3, + SET => GND, + RST => GSR + ); + Inst_txserie1_RFLAG_I1_0 : X_TRI + port map ( + I => Inst_rxserie1_RFLAG_output(7), + CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_0_T, + O => bus_data_7_IOBUF + ); + irqtx_OBUF_22 : X_BUF + port map ( + I => irqtx_OBUF, + O => irqtx_OBUF_GTS_TRI + ); + Inst_txserie1_RFLAG_I1_7 : X_TRI + port map ( + I => Inst_txserie1_RFLAG_REG(0), + CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_7_T, + O => bus_data_0_IOBUF ); - Inst_rxserie1_RC1_RXCLK_28 : X_FF + Inst_txserie1_RFLAG_I1_6 : X_TRI + port map ( + I => Inst_txserie1_RFLAG_REG(1), + CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_6_T, + O => bus_data_1_IOBUF + ); + Inst_txserie1_RFLAG_I1_5 : X_TRI + port map ( + I => Inst_txserie1_RFLAG_REG(2), + CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_5_T, + O => bus_data_2_IOBUF + ); + Inst_txserie1_RFLAG_I1_4 : X_TRI + port map ( + I => Inst_txserie1_RFLAG_REG(3), + CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_4_T, + O => bus_data_3_IOBUF + ); + Inst_txserie1_RFLAG_I1_3 : X_TRI + port map ( + I => Inst_rxserie1_RFLAG_output(7), + CTL => NlwInverterSignal_Inst_txserie1_RFLAG_I1_3_T, + O => bus_data_4_IOBUF + ); + Inst_txserie1_FIFO1_state_read_FFd1_23 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_RXCNT(3), - RST => Inst_rxserie1_RC1_RXCLK_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RXCLK, - CE => VCC, - SET => GND + I => Inst_txserie1_FIFO1_state_read_FFd1_In, + CE => Inst_txserie1_FIFO1_dready_N1514, + CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd1_C, + O => Inst_txserie1_FIFO1_state_read_FFd1, + SET => GND, + RST => GSR ); - Inst_rxserie1_RC1_RXPARITY_29 : X_FF + Inst_rxserie1_CLOCK1_n000539_SW0 : X_LUT4 generic map( - INIT => '1' + INIT => X"FFFE" ) port map ( - I => Inst_rxserie1_RC1_n0019, - SET => Inst_rxserie1_RC1_RXPARITY_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_RXPARITY, - CE => VCC, - RST => GND + ADR0 => Inst_rxserie1_CLOCK1_compteur(2), + ADR1 => Inst_rxserie1_CLOCK1_compteur(3), + ADR2 => Inst_rxserie1_CLOCK1_compteur(6), + ADR3 => Inst_rxserie1_CLOCK1_compteur(7), + O => N15425 ); - Inst_rxserie1_RC1_PARITYGEN_30 : X_FF + Inst_txserie1_RFLAG_REG_0_n00001 : X_LUT2 generic map( - INIT => '1' + INIT => X"5" ) port map ( - I => Inst_rxserie1_RC1_n0020, - SET => Inst_rxserie1_RC1_PARITYGEN_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_PARITYGEN, - CE => VCC, - RST => GND + ADR0 => Inst_txserie1_fifoLevel(0), + O => Inst_txserie1_RFLAG_REG_0_n0000, + ADR1 => GND ); - Inst_rxserie1_RC1_RXSTOP_31 : X_FF + Inst_txserie1_RFLAG_REG_1_n00001 : X_LUT2 generic map( - INIT => '0' + INIT => X"5" ) port map ( - I => Inst_rxserie1_RC1_n0021, - RST => Inst_rxserie1_RC1_RXSTOP_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_RXSTOP, - CE => VCC, - SET => GND + ADR0 => Inst_txserie1_fifoLevel(1), + O => Inst_txserie1_RFLAG_REG_1_n0000, + ADR1 => GND ); - Inst_rxserie1_RC1_RSR_7 : X_FF + Inst_txserie1_RFLAG_REG_2_n00001 : X_LUT2 generic map( - INIT => '1' + INIT => X"5" ) port map ( - I => Inst_rxserie1_RC1_n0022, - SET => Inst_rxserie1_RC1_RSR_7_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_RSR(7), - CE => VCC, - RST => GND + ADR0 => Inst_txserie1_flagreg(2), + O => Inst_txserie1_RFLAG_REG_2_n0000, + ADR1 => GND ); - Inst_rxserie1_RC1_RSR_6 : X_FF + Inst_txserie1_RFLAG_REG_3_n00001 : X_LUT2 generic map( - INIT => '1' + INIT => X"5" ) port map ( - I => Inst_rxserie1_RC1_n0023, - SET => Inst_rxserie1_RC1_RSR_6_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_RSR(6), - CE => VCC, - RST => GND + ADR0 => Inst_txserie1_flagreg(3), + O => Inst_txserie1_RFLAG_REG_3_n0000, + ADR1 => GND ); - Inst_rxserie1_RC1_RSR_5 : X_FF + Inst_txserie1_RFLAG_I1_EnableTr_INV1 : X_LUT3 generic map( - INIT => '1' + INIT => X"DF" ) port map ( - I => Inst_rxserie1_RC1_n0024, - SET => Inst_rxserie1_RC1_RSR_5_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_RSR(5), - CE => VCC, - RST => GND + ADR0 => cs(6), + ADR1 => rst_BUFGP, + ADR2 => rw, + O => Inst_txserie1_RFLAG_I1_N1528 ); - Inst_rxserie1_RC1_RSR_4 : X_FF + Inst_txserie1_FIFO1_state_read_FFd4_24 : X_FF generic map( INIT => '1' ) port map ( - I => Inst_rxserie1_RC1_n0025, - SET => Inst_rxserie1_RC1_RSR_4_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_RSR(4), - CE => VCC, + I => Inst_txserie1_FIFO1_state_read_FFd4_In, + CE => Inst_txserie1_FIFO1_dready_N1514, + CLK => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd4_C, + O => Inst_txserie1_FIFO1_state_read_FFd4, + SET => GSR, RST => GND ); - Inst_rxserie1_RC1_RSR_3 : X_FF + Inst_rxserie1_FIFO1_state_write_FFd3_25 : X_FF generic map( INIT => '1' ) port map ( - I => Inst_rxserie1_RC1_n0026, - SET => Inst_rxserie1_RC1_RSR_3_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_RSR(3), - CE => VCC, + I => Inst_rxserie1_FIFO1_state_write_FFd3_In, + CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1643, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C, + O => Inst_rxserie1_FIFO1_state_write_FFd3, + SET => GSR, RST => GND ); - Inst_rxserie1_RC1_RSR_2 : X_FF + Inst_txserie1_FIFO1_state_read_FFd1_In1 : X_LUT4 generic map( - INIT => '1' + INIT => X"0C08" ) port map ( - I => Inst_rxserie1_RC1_n0027, - SET => Inst_rxserie1_RC1_RSR_2_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_RSR(2), - CE => VCC, - RST => GND + ADR0 => Inst_txserie1_FIFO1_state_read_FFd1, + ADR1 => Inst_txserie1_txready, + ADR2 => Inst_txserie1_flagreg(3), + ADR3 => Inst_txserie1_FIFO1_dready, + O => Inst_txserie1_FIFO1_state_read_FFd1_In ); - Inst_rxserie1_RC1_RSR_1 : X_FF + Inst_txserie1_CLOCK1_compteur_0_rt_26 : X_LUT2 generic map( - INIT => '1' + INIT => X"A" ) port map ( - I => Inst_rxserie1_RC1_n0028, - SET => Inst_rxserie1_RC1_RSR_1_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_RSR(1), - CE => VCC, - RST => GND + ADR0 => Inst_txserie1_CLOCK1_compteur(0), + O => Inst_txserie1_CLOCK1_compteur_0_rt, + ADR1 => GND ); - Inst_rxserie1_RC1_RSR_0 : X_FF + Inst_decodisa_n00031 : X_LUT3 generic map( - INIT => '1' + INIT => X"04" ) port map ( - I => Inst_rxserie1_RC1_n0029, - SET => Inst_rxserie1_RC1_RSR_0_GSR_OR, - CLK => Inst_rxserie1_RC1_RXCLK, - O => Inst_rxserie1_RC1_RSR(0), - CE => VCC, - RST => GND + ADR0 => IOR_IBUF, + ADR1 => IOW_IBUF, + ADR2 => AEN_IBUF, + O => rw ); - Inst_rxserie1_RC1_RHR_7 : X_FF + Inst_rxserie1_RC1_Madd_n0040_inst_cy_12_27 : X_MUX2 + port map ( + IB => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11, + IA => Inst_rxserie1_RFLAG_output(7), + SEL => Inst_rxserie1_RC1_RXCNT_2_rt, + O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_12 + ); + Inst_rxserie1_RC1_Madd_n0040_inst_sum_12 : X_XOR2 + port map ( + I0 => Inst_rxserie1_RC1_RXCNT_2_rt, + I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11, + O => Inst_rxserie1_RC1_n0040(2) + ); + Inst_rxserie1_RC1_n00631 : X_LUT4 + generic map( + INIT => X"44F4" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_READ2, + ADR1 => Inst_rxserie1_RC1_READ1, + ADR2 => Inst_rxserie1_RC1_IDLE, + ADR3 => Inst_rxserie1_RC1_IDLE1, + O => Inst_rxserie1_RC1_n0063 + ); + Inst_rxserie1_RC1_n00621 : X_LUT3 + generic map( + INIT => X"BA" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_N10580, + ADR1 => Inst_rxserie1_RC1_READ2, + ADR2 => Inst_rxserie1_RC1_READ1, + O => Inst_rxserie1_RC1_n0062 + ); + Inst_rxserie1_RC1_Ker105781 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE1, + ADR1 => Inst_rxserie1_RC1_IDLE, + ADR2 => Inst_rxserie1_RC1_RXDATARDY, + O => Inst_rxserie1_RC1_N10580 + ); + Inst_txserie1_TX1_Mmux_n0020_Result1 : X_LUT4 + generic map( + INIT => X"DC8C" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TAG1, + ADR2 => Inst_txserie1_TX1_TXDATARDY, + ADR3 => Inst_txserie1_TX1_THR(7), + O => Inst_txserie1_TX1_n0020 + ); + Inst_rxserie1_RC1_n00501 : X_LUT3 + generic map( + INIT => X"FD" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RX1, + ADR2 => rxin1_IBUF, + O => Inst_rxserie1_RC1_n0050 + ); + Inst_rxserie1_RC1_RHR_6 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_RSR(7), - CE => Inst_rxserie1_RC1_N7296, - RST => Inst_rxserie1_RC1_RHR_7_GSR_OR, + I => Inst_rxserie1_RC1_RSR(6), + CE => Inst_rxserie1_RC1_N10580, + RST => Inst_rxserie1_RC1_RHR_6_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RHR(7), + O => Inst_rxserie1_RC1_RHR(6), SET => GND ); - Inst_rxserie1_RC1_RXDATARDY_32 : X_FF + Inst_rxserie1_RC1_RHR_3 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_n0031, - CE => Inst_rxserie1_RC1_n0062, - RST => Inst_rxserie1_RC1_RXDATARDY_GSR_OR, + I => Inst_rxserie1_RC1_RSR(3), + CE => Inst_rxserie1_RC1_N10580, + RST => Inst_rxserie1_RC1_RHR_3_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RXDATARDY, + O => Inst_rxserie1_RC1_RHR(3), SET => GND ); - Inst_rxserie1_RC1_OVERRUN_33 : X_FF + Inst_rxserie1_RC1_RHR_5 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_n0041, - CE => Inst_rxserie1_RC1_n0063, - RST => Inst_rxserie1_RC1_OVERRUN_GSR_OR, + I => Inst_rxserie1_RC1_RSR(5), + CE => Inst_rxserie1_RC1_N10580, + RST => Inst_rxserie1_RC1_RHR_5_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_OVERRUN, + O => Inst_rxserie1_RC1_RHR(5), SET => GND ); - Inst_rxserie1_RC1_PARITY_ERR_34 : X_FF + Inst_rxserie1_RC1_RHR_4 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_n0034, - CE => Inst_rxserie1_RC1_n0062, - RST => Inst_rxserie1_RC1_PARITY_ERR_GSR_OR, + I => Inst_rxserie1_RC1_RSR(4), + CE => Inst_rxserie1_RC1_N10580, + RST => Inst_rxserie1_RC1_RHR_4_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_PARITY_ERR, + O => Inst_rxserie1_RC1_RHR(4), SET => GND ); - Inst_rxserie1_RC1_FRAMING_ERR_35 : X_FF + Inst_rxserie1_RC1_RHR_0 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_n0035, - CE => Inst_rxserie1_RC1_n0062, - RST => Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR, + I => Inst_rxserie1_RC1_RSR(0), + CE => Inst_rxserie1_RC1_N10580, + RST => Inst_rxserie1_RC1_RHR_0_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_FRAMING_ERR, + O => Inst_rxserie1_RC1_RHR(0), SET => GND ); - Inst_rxserie1_RC1_RXCNT_3 : X_FF + Inst_rxserie1_RC1_RHR_2 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_n0018(3), - CE => Inst_rxserie1_RC1_n0051, - RST => Inst_rxserie1_RC1_RXCNT_3_GSR_OR, + I => Inst_rxserie1_RC1_RSR(2), + CE => Inst_rxserie1_RC1_N10580, + RST => Inst_rxserie1_RC1_RHR_2_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RXCNT(3), + O => Inst_rxserie1_RC1_RHR(2), SET => GND ); - Inst_rxserie1_RC1_RXCNT_2 : X_FF + Inst_rxserie1_RC1_RHR_1 : X_FF generic map( INIT => '0' ) port map ( - I => Inst_rxserie1_RC1_n0018(2), - CE => Inst_rxserie1_RC1_n0051, - RST => Inst_rxserie1_RC1_RXCNT_2_GSR_OR, + I => Inst_rxserie1_RC1_RSR(1), + CE => Inst_rxserie1_RC1_N10580, + RST => Inst_rxserie1_RC1_RHR_1_GSR_OR, CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RXCNT(2), + O => Inst_rxserie1_RC1_RHR(1), SET => GND ); - Inst_rxserie1_RC1_RXCNT_0 : X_FF + Inst_rxserie1_RC1_n00411 : X_LUT3 generic map( - INIT => '1' + INIT => X"A2" ) port map ( - I => Inst_rxserie1_RC1_n0018(0), - CE => Inst_rxserie1_RC1_n0051, - SET => Inst_rxserie1_RC1_RXCNT_0_GSR_OR, - CLK => Inst_rxserie1_CLOCK1_ckout, - O => Inst_rxserie1_RC1_RXCNT(0), - RST => GND + ADR0 => Inst_rxserie1_RC1_RXDATARDY, + ADR1 => Inst_rxserie1_RC1_READ1, + ADR2 => Inst_rxserie1_RC1_READ2, + O => Inst_rxserie1_RC1_n0041 ); - bus_adr_0_IBUF_36 : X_BUF + Inst_rxserie1_RC1_READ2_28 : X_FF + generic map( + INIT => '1' + ) port map ( - I => bus_adr(0), - O => bus_adr_0_IBUF + I => Inst_rxserie1_RC1_READ1, + SET => Inst_rxserie1_RC1_READ2_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_READ2, + CE => VCC, + RST => GND ); - Inst_rxserie1_RC1_Madd_n0040_inst_sum_13 : X_XOR2 + Inst_rxserie1_RC1_n00311 : X_LUT2 + generic map( + INIT => X"D" + ) port map ( - I0 => Inst_rxserie1_RC1_RXCNT_3_rt, - I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_12, - O => Inst_rxserie1_RC1_n0040(3) + ADR0 => Inst_rxserie1_RC1_READ1, + ADR1 => Inst_rxserie1_RC1_READ2, + O => Inst_rxserie1_RC1_n0031 ); - Inst_rxserie1_RC1_Madd_n0040_inst_lut2_101 : X_LUT2 + Inst_rxserie1_RC1_n0018_1_1 : X_LUT3 generic map( - INIT => X"5" + INIT => X"A2" ) port map ( - ADR0 => Inst_rxserie1_RC1_RXCNT(0), - O => Inst_rxserie1_RC1_Madd_n0040_inst_lut2_10, - ADR1 => GND + ADR0 => Inst_rxserie1_RC1_n0040(1), + ADR1 => Inst_rxserie1_RC1_IDLE, + ADR2 => Inst_rxserie1_RC1_HUNT, + O => Inst_rxserie1_RC1_n0018(1) ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_8 : X_XOR2 + Inst_rxserie1_RC1_n00361 : X_LUT3 + generic map( + INIT => X"40" + ) port map ( - I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, - I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, - O => Inst_rxserie1_CLOCK1_compteur_n0005(8) + ADR0 => rxin1_IBUF, + ADR1 => Inst_rxserie1_RC1_IDLE, + ADR2 => Inst_rxserie1_RC1_RX1, + O => Inst_rxserie1_RC1_n0036 ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8_37 : X_MUX2 + Inst_rxserie1_RC1_n00351 : X_LUT3 + generic map( + INIT => X"51" + ) port map ( - IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, - IA => Inst_rxserie1_CLOCK1_compteur(8), - SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8 + ADR0 => Inst_rxserie1_RC1_RXSTOP, + ADR1 => Inst_rxserie1_RC1_READ1, + ADR2 => Inst_rxserie1_RC1_READ2, + O => Inst_rxserie1_RC1_n0035 ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_6 : X_XOR2 + Inst_rxserie1_RC1_n00341 : X_LUT3 + generic map( + INIT => X"A2" + ) port map ( - I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, - I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, - O => Inst_rxserie1_CLOCK1_compteur_n0005(6) + ADR0 => Inst_rxserie1_RC1_PARITYGEN, + ADR1 => Inst_rxserie1_RC1_READ1, + ADR2 => Inst_rxserie1_RC1_READ2, + O => Inst_rxserie1_RC1_n0034 ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7_38 : X_MUX2 + Inst_rxserie1_RC1_Madd_n0040_inst_cy_11_29 : X_MUX2 port map ( - IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, - IA => Inst_rxserie1_CLOCK1_compteur(7), - SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7 + IB => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10, + IA => Inst_rxserie1_RFLAG_output(7), + SEL => Inst_rxserie1_RC1_RXCNT_1_rt, + O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11 ); - Inst_rxserie1_CLOCK1_compteur_0_n00011 : X_LUT2 + Inst_rxserie1_RC1_n00291 : X_LUT2 generic map( - INIT => X"8" + INIT => X"E" ) port map ( - ADR0 => rst_IBUF, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(0), - O => Inst_rxserie1_CLOCK1_compteur_0_0_n0001 - ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_7 : X_XOR2 - port map ( - I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, - I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, - O => Inst_rxserie1_CLOCK1_compteur_n0005(7) + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(1), + O => Inst_rxserie1_RC1_n0029 ); - Inst_rxserie1_CLOCK1_n000539 : X_LUT4 + Inst_rxserie1_RC1_n00281 : X_LUT2 generic map( - INIT => X"0100" + INIT => X"E" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(4), - ADR1 => Inst_rxserie1_CLOCK1_compteur(5), - ADR2 => N11021, - ADR3 => CHOICE64, - O => Inst_rxserie1_CLOCK1_n0005 + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(2), + O => Inst_rxserie1_RC1_n0028 ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_61 : X_LUT2 + Inst_rxserie1_RC1_n00271 : X_LUT2 generic map( - INIT => X"5" + INIT => X"E" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(6), - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, - ADR1 => GND + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(3), + O => Inst_rxserie1_RC1_n0027 ); - Inst_rxserie1_CLOCK1_ckout_39 : X_FF + Inst_rxserie1_RC1_n00261 : X_LUT2 generic map( - INIT => '0' + INIT => X"E" ) port map ( - I => Inst_rxserie1_CLOCK1_n0005, - RST => Inst_rxserie1_CLOCK1_ckout_GSR_OR, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_ckout, - CE => VCC, - SET => GND + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(4), + O => Inst_rxserie1_RC1_n0026 ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_71 : X_LUT2 + Inst_rxserie1_RC1_n00251 : X_LUT2 generic map( - INIT => X"5" + INIT => X"E" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(7), - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, - ADR1 => GND + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(5), + O => Inst_rxserie1_RC1_n0025 ); - Inst_rxserie1_CLOCK1_compteur_n00061 : X_LUT2 + Inst_rxserie1_RC1_n00241 : X_LUT2 generic map( INIT => X"E" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_n0005, - ADR1 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_n0006 + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(6), + O => Inst_rxserie1_RC1_n0024 ); - Inst_rxserie1_RC1_n0018_0_1 : X_LUT3 + Inst_rxserie1_RC1_n00231 : X_LUT2 generic map( - INIT => X"75" + INIT => X"E" ) port map ( - ADR0 => Inst_rxserie1_RC1_RXCNT(0), - ADR1 => Inst_rxserie1_RC1_HUNT, - ADR2 => Inst_rxserie1_RC1_IDLE, - O => Inst_rxserie1_RC1_n0018(0) + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(7), + O => Inst_rxserie1_RC1_n0023 ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_91 : X_LUT2 + Inst_rxserie1_RC1_n00221 : X_LUT2 generic map( - INIT => X"5" + INIT => X"E" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(9), - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, - ADR1 => GND + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RXPARITY, + O => Inst_rxserie1_RC1_n0022 ); - Inst_rxserie1_CLOCK1_compteur_0_n00001 : X_LUT2 + Inst_rxserie1_RC1_n00211 : X_LUT2 generic map( INIT => X"4" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(0), - ADR1 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_0_0_n0000 + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => rxin1_IBUF, + O => Inst_rxserie1_RC1_n0021 ); - Inst_rxserie1_CLOCK1_compteur_9 : X_FF + Inst_rxserie1_RC1_n00201 : X_LUT3 generic map( - INIT => '0' + INIT => X"F6" ) port map ( - I => Inst_rxserie1_CLOCK1_compteur_n0001(9), - RST => Inst_rxserie1_CLOCK1_compteur_9_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_compteur(9), - CE => VCC + ADR0 => Inst_rxserie1_RC1_RXSTOP, + ADR1 => Inst_rxserie1_RC1_PARITYGEN, + ADR2 => Inst_rxserie1_RC1_IDLE, + O => Inst_rxserie1_RC1_n0020 ); - Inst_rxserie1_CLOCK1_compteur_8 : X_FF + Inst_rxserie1_RC1_n00191 : X_LUT2 generic map( - INIT => '0' + INIT => X"E" ) port map ( - I => Inst_rxserie1_CLOCK1_compteur_n0001(8), - RST => Inst_rxserie1_CLOCK1_compteur_8_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_compteur(8), - CE => VCC + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RXSTOP, + O => Inst_rxserie1_RC1_n0019 ); - Inst_rxserie1_CLOCK1_compteur_0 : X_FF + Inst_txserie1_TX1_n00481 : X_LUT4 generic map( - INIT => '0' + INIT => X"8F88" ) port map ( - I => Inst_rxserie1_CLOCK1_compteur_n0001(0), - RST => Inst_rxserie1_CLOCK1_compteur_0_GSR_OR, - SET => Inst_rxserie1_CLOCK1_compteur_0_0_n0001, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_compteur(0), - CE => VCC + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TXDONE1, + ADR2 => Inst_txserie1_TX1_WRITE2, + ADR3 => Inst_txserie1_TX1_WRITE1, + O => Inst_txserie1_TX1_n0048 ); - Inst_rxserie1_CLOCK1_compteur_1 : X_FF - generic map( - INIT => '0' - ) + Inst_rxserie1_RC1_Madd_n0040_inst_sum_11 : X_XOR2 port map ( - I => Inst_rxserie1_CLOCK1_compteur_n0001(1), - RST => Inst_rxserie1_CLOCK1_compteur_1_GSR_OR, - SET => Inst_rxserie1_CLOCK1_compteur_0_1_n0001, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_compteur(1), - CE => VCC + I0 => Inst_rxserie1_RC1_RXCNT_1_rt, + I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10, + O => Inst_rxserie1_RC1_n0040(1) ); - Inst_rxserie1_CLOCK1_compteur_2 : X_FF + Inst_rxserie1_RC1_n0018_2_1 : X_LUT3 generic map( - INIT => '0' + INIT => X"A2" ) port map ( - I => Inst_rxserie1_CLOCK1_compteur_n0001(2), - RST => Inst_rxserie1_CLOCK1_compteur_2_GSR_OR, - SET => Inst_rxserie1_CLOCK1_compteur_0_2_n0001, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_compteur(2), - CE => VCC + ADR0 => Inst_rxserie1_RC1_n0040(2), + ADR1 => Inst_rxserie1_RC1_IDLE, + ADR2 => Inst_rxserie1_RC1_HUNT, + O => Inst_rxserie1_RC1_n0018(2) ); - Inst_rxserie1_CLOCK1_compteur_3 : X_FF + Inst_rxserie1_RC1_n0018_3_1 : X_LUT3 generic map( - INIT => '0' + INIT => X"A2" ) port map ( - I => Inst_rxserie1_CLOCK1_compteur_n0001(3), - RST => Inst_rxserie1_CLOCK1_compteur_3_GSR_OR, - SET => Inst_rxserie1_CLOCK1_compteur_0_3_n0001, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_compteur(3), - CE => VCC + ADR0 => Inst_rxserie1_RC1_n0040(3), + ADR1 => Inst_rxserie1_RC1_IDLE, + ADR2 => Inst_rxserie1_RC1_HUNT, + O => Inst_rxserie1_RC1_n0018(3) ); - Inst_rxserie1_CLOCK1_compteur_4 : X_FF + Inst_rxserie1_RC1_IDLE1_30 : X_FF generic map( - INIT => '0' + INIT => '1' ) port map ( - I => Inst_rxserie1_CLOCK1_compteur_n0001(4), - RST => Inst_rxserie1_CLOCK1_compteur_4_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_compteur(4), - CE => VCC + I => Inst_rxserie1_RC1_IDLE, + SET => Inst_rxserie1_RC1_IDLE1_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_IDLE1, + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_5 : X_FF + Inst_rxserie1_RC1_n00151 : X_LUT2 generic map( - INIT => '0' + INIT => X"1" ) port map ( - I => Inst_rxserie1_CLOCK1_compteur_n0001(5), - RST => Inst_rxserie1_CLOCK1_compteur_5_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_compteur(5), - CE => VCC + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(0), + O => Inst_rxserie1_RC1_n0015 ); - Inst_rxserie1_CLOCK1_compteur_6 : X_FF + Inst_rxserie1_RC1_READ1_31 : X_FF generic map( - INIT => '0' + INIT => '1' ) port map ( - I => Inst_rxserie1_CLOCK1_compteur_n0001(6), - RST => Inst_rxserie1_CLOCK1_compteur_6_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_compteur(6), - CE => VCC + I => Inst_rxserie1_rxread, + SET => Inst_rxserie1_RC1_READ1_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_READ1, + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_7 : X_FF + Inst_rxserie1_RC1_IDLE_32 : X_FF generic map( - INIT => '0' + INIT => '1' ) port map ( - I => Inst_rxserie1_CLOCK1_compteur_n0001(7), - RST => Inst_rxserie1_CLOCK1_compteur_7_GSR_OR, - SET => Inst_rxserie1_FIFO1_state_read_FFd2, - CLK => Inst_rxserie1_geneck, - O => Inst_rxserie1_CLOCK1_compteur(7), - CE => VCC - ); - bus_adr_9_IBUF_40 : X_BUF - port map ( - I => bus_adr(9), - O => bus_adr_9_IBUF - ); - bus_adr_15_IBUF_41 : X_BUF - port map ( - I => bus_adr(15), - O => bus_adr_15_IBUF - ); - bus_adr_10_IBUF_42 : X_BUF - port map ( - I => bus_adr(10), - O => bus_adr_10_IBUF - ); - clk_ref_IBUF_43 : X_BUF - port map ( - I => clk_ref, - O => clk_ref_IBUF - ); - bus_adr_11_IBUF_44 : X_BUF - port map ( - I => bus_adr(11), - O => bus_adr_11_IBUF - ); - IOW_IBUF_45 : X_BUF - port map ( - I => IOW, - O => IOW_IBUF - ); - bus_adr_12_IBUF_46 : X_BUF - port map ( - I => bus_adr(12), - O => bus_adr_12_IBUF - ); - IOR_IBUF_47 : X_BUF - port map ( - I => IOR, - O => IOR_IBUF - ); - bus_adr_13_IBUF_48 : X_BUF - port map ( - I => bus_adr(13), - O => bus_adr_13_IBUF - ); - AEN_IBUF_49 : X_BUF - port map ( - I => AEN, - O => AEN_IBUF - ); - bus_adr_14_IBUF_50 : X_BUF - port map ( - I => bus_adr(14), - O => bus_adr_14_IBUF - ); - rxin1_IBUF_51 : X_BUF - port map ( - I => rxin1, - O => rxin1_IBUF + I => Inst_rxserie1_RC1_n0015, + SET => Inst_rxserie1_RC1_IDLE_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_IDLE, + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_3_n00011 : X_LUT2 + Inst_rxserie1_RC1_HUNT_33 : X_FF generic map( - INIT => X"8" + INIT => '0' ) port map ( - ADR0 => rst_IBUF, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(3), - O => Inst_rxserie1_CLOCK1_compteur_0_3_n0001 + I => Inst_rxserie1_RC1_n0036, + CE => Inst_rxserie1_RC1_n0050, + RST => Inst_rxserie1_RC1_HUNT_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_HUNT, + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_3_n00001 : X_LUT2 + Inst_rxserie1_RC1_RXCNT_1 : X_FF generic map( - INIT => X"4" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(3), - ADR1 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_0_3_n0000 - ); - rst_IBUF_52 : X_BUF - port map ( - I => rst, - O => rst_IBUF + I => Inst_rxserie1_RC1_n0018(1), + CE => Inst_rxserie1_RC1_n0051, + RST => Inst_rxserie1_RC1_RXCNT_1_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXCNT(1), + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_2_n00011 : X_LUT2 + Inst_rxserie1_RC1_RX1_34 : X_FF generic map( - INIT => X"4" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_RCONF_REG(1), - ADR1 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_0_2_n0001 + I => rxin1_IBUF, + SET => Inst_rxserie1_RC1_RX1_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RX1, + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_1_n00011 : X_LUT2 + Inst_rxserie1_RC1_RXCLK_35 : X_FF generic map( - INIT => X"8" + INIT => '0' ) port map ( - ADR0 => rst_IBUF, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(1), - O => Inst_rxserie1_CLOCK1_compteur_0_1_n0001 + I => Inst_rxserie1_RC1_RXCNT(3), + RST => Inst_rxserie1_RC1_RXCLK_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXCLK, + CE => VCC, + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_1_n00001 : X_LUT2 + Inst_rxserie1_RC1_RXPARITY_36 : X_FF generic map( - INIT => X"4" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(1), - ADR1 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_0_1_n0000 + I => Inst_rxserie1_RC1_n0019, + SET => Inst_rxserie1_RC1_RXPARITY_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RXPARITY, + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_0_1 : X_LUT4 + Inst_rxserie1_RC1_PARITYGEN_37 : X_FF generic map( - INIT => X"E444" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(0), - ADR2 => Inst_rxserie1_RCONF_REG(1), - ADR3 => Inst_rxserie1_RCONF_REG(0), - O => Inst_rxserie1_CLOCK1_compteur_n0001(0) + I => Inst_rxserie1_RC1_n0020, + SET => Inst_rxserie1_RC1_PARITYGEN_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_PARITYGEN, + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_1_1 : X_LUT4 + Inst_rxserie1_RC1_RXSTOP_38 : X_FF generic map( - INIT => X"4EE4" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(1), - ADR2 => Inst_rxserie1_RCONF_REG(0), - ADR3 => Inst_rxserie1_RCONF_REG(1), - O => Inst_rxserie1_CLOCK1_compteur_n0001(1) + I => Inst_rxserie1_RC1_n0021, + RST => Inst_rxserie1_RC1_RXSTOP_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RXSTOP, + CE => VCC, + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_4_1 : X_LUT3 + Inst_rxserie1_RC1_RSR_7 : X_FF generic map( - INIT => X"04" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_n0005, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(4), - ADR2 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_n0001(4) + I => Inst_rxserie1_RC1_n0022, + SET => Inst_rxserie1_RC1_RSR_7_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(7), + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_3_1 : X_LUT4 + Inst_rxserie1_RC1_RSR_6 : X_FF generic map( - INIT => X"444E" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(3), - ADR2 => Inst_rxserie1_RCONF_REG(1), - ADR3 => Inst_rxserie1_RCONF_REG(0), - O => Inst_rxserie1_CLOCK1_compteur_n0001(3) + I => Inst_rxserie1_RC1_n0023, + SET => Inst_rxserie1_RC1_RSR_6_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(6), + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_5_1 : X_LUT3 + Inst_rxserie1_RC1_RSR_5 : X_FF generic map( - INIT => X"04" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_n0005, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(5), - ADR2 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_n0001(5) + I => Inst_rxserie1_RC1_n0024, + SET => Inst_rxserie1_RC1_RSR_5_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(5), + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_6_1 : X_LUT3 + Inst_rxserie1_RC1_RSR_4 : X_FF generic map( - INIT => X"04" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_n0005, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(6), - ADR2 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_n0001(6) + I => Inst_rxserie1_RC1_n0025, + SET => Inst_rxserie1_RC1_RSR_4_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(4), + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_7_1 : X_LUT3 + Inst_rxserie1_RC1_RSR_3 : X_FF generic map( - INIT => X"04" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_n0005, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(7), - ADR2 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_n0001(7) + I => Inst_rxserie1_RC1_n0026, + SET => Inst_rxserie1_RC1_RSR_3_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(3), + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_8_1 : X_LUT3 + Inst_rxserie1_RC1_RSR_2 : X_FF generic map( - INIT => X"04" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_n0005, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(8), - ADR2 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_n0001(8) + I => Inst_rxserie1_RC1_n0027, + SET => Inst_rxserie1_RC1_RSR_2_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(2), + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_9_1 : X_LUT3 + Inst_rxserie1_RC1_RSR_1 : X_FF generic map( - INIT => X"04" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_n0005, - ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(9), - ADR2 => rst_IBUF, - O => Inst_rxserie1_CLOCK1_compteur_n0001(9) + I => Inst_rxserie1_RC1_n0028, + SET => Inst_rxserie1_RC1_RSR_1_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(1), + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_81 : X_LUT2 + Inst_rxserie1_RC1_RSR_0 : X_FF generic map( - INIT => X"5" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(8), - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, - ADR1 => GND + I => Inst_rxserie1_RC1_n0029, + SET => Inst_rxserie1_RC1_RSR_0_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(0), + CE => VCC, + RST => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6_53 : X_MUX2 + Inst_rxserie1_RC1_RHR_7 : X_FF + generic map( + INIT => '0' + ) port map ( - IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, - IA => Inst_rxserie1_CLOCK1_compteur(6), - SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6 + I => Inst_rxserie1_RC1_RSR(7), + CE => Inst_rxserie1_RC1_N10580, + RST => Inst_rxserie1_RC1_RHR_7_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RHR(7), + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_9 : X_XOR2 + Inst_rxserie1_RC1_RXDATARDY_39 : X_FF + generic map( + INIT => '0' + ) port map ( - I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, - I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8, - O => Inst_rxserie1_CLOCK1_compteur_n0005(9) + I => Inst_rxserie1_RC1_n0031, + CE => Inst_rxserie1_RC1_n0062, + RST => Inst_rxserie1_RC1_RXDATARDY_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXDATARDY, + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0_54 : X_MUX2 + Inst_rxserie1_RC1_OVERRUN_40 : X_FF + generic map( + INIT => '0' + ) port map ( - IB => Inst_rxserie1_I7_N1369, - IA => Inst_rxserie1_FIFO1_state_read_FFd2, - SEL => Inst_rxserie1_CLOCK1_compteur_0_rt, - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0 + I => Inst_rxserie1_RC1_n0041, + CE => Inst_rxserie1_RC1_n0063, + RST => Inst_rxserie1_RC1_OVERRUN_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_OVERRUN, + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_0 : X_XOR2 + Inst_rxserie1_RC1_PARITY_ERR_41 : X_FF + generic map( + INIT => '0' + ) port map ( - I0 => Inst_rxserie1_CLOCK1_compteur_0_rt, - I1 => Inst_rxserie1_I7_N1369, - O => Inst_rxserie1_CLOCK1_compteur_n0005(0) + I => Inst_rxserie1_RC1_n0034, + CE => Inst_rxserie1_RC1_n0062, + RST => Inst_rxserie1_RC1_PARITY_ERR_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_PARITY_ERR, + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_11 : X_LUT2 + Inst_rxserie1_RC1_FRAMING_ERR_42 : X_FF generic map( - INIT => X"5" + INIT => '0' ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(1), - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, - ADR1 => GND + I => Inst_rxserie1_RC1_n0035, + CE => Inst_rxserie1_RC1_n0062, + RST => Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_FRAMING_ERR, + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1_55 : X_MUX2 + Inst_rxserie1_RC1_RXCNT_3 : X_FF + generic map( + INIT => '0' + ) port map ( - IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, - IA => Inst_rxserie1_CLOCK1_compteur(1), - SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1 + I => Inst_rxserie1_RC1_n0018(3), + CE => Inst_rxserie1_RC1_n0051, + RST => Inst_rxserie1_RC1_RXCNT_3_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXCNT(3), + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_1 : X_XOR2 + Inst_rxserie1_RC1_RXCNT_2 : X_FF + generic map( + INIT => '0' + ) port map ( - I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, - I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, - O => Inst_rxserie1_CLOCK1_compteur_n0005(1) + I => Inst_rxserie1_RC1_n0018(2), + CE => Inst_rxserie1_RC1_n0051, + RST => Inst_rxserie1_RC1_RXCNT_2_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXCNT(2), + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_21 : X_LUT2 + Inst_rxserie1_RC1_RXCNT_0 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0018(0), + CE => Inst_rxserie1_RC1_n0051, + SET => Inst_rxserie1_RC1_RXCNT_0_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXCNT(0), + RST => GND + ); + irqrxFIFO_OBUF_43 : X_BUF + port map ( + I => irqrxFIFO_OBUF, + O => irqrxFIFO_OBUF_GTS_TRI + ); + Inst_rxserie1_RC1_Madd_n0040_inst_sum_13 : X_XOR2 + port map ( + I0 => Inst_rxserie1_RC1_RXCNT_3_rt, + I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_12, + O => Inst_rxserie1_RC1_n0040(3) + ); + Inst_rxserie1_RC1_Madd_n0040_inst_lut2_101 : X_LUT2 generic map( INIT => X"5" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(2), - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, + ADR0 => Inst_rxserie1_RC1_RXCNT(0), + O => Inst_rxserie1_RC1_Madd_n0040_inst_lut2_10, ADR1 => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2_56 : X_MUX2 + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_8 : X_XOR2 port map ( - IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, - IA => Inst_rxserie1_CLOCK1_compteur(2), - SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2 + I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, + I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, + O => Inst_txserie1_CLOCK1_compteur_n0005(8) ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_2 : X_XOR2 + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8_44 : X_MUX2 port map ( - I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, - I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, - O => Inst_rxserie1_CLOCK1_compteur_n0005(2) + IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, + IA => Inst_txserie1_CLOCK1_compteur(8), + SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8 ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_31 : X_LUT2 + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_6 : X_XOR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, + I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, + O => Inst_txserie1_CLOCK1_compteur_n0005(6) + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7_45 : X_MUX2 + port map ( + IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, + IA => Inst_txserie1_CLOCK1_compteur(7), + SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7 + ); + Inst_txserie1_CLOCK1_compteur_0_n00011 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0001(0), + O => Inst_txserie1_CLOCK1_compteur_0_0_n0001 + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_7 : X_XOR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, + I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, + O => Inst_txserie1_CLOCK1_compteur_n0005(7) + ); + Inst_txserie1_CLOCK1_n000539 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur(4), + ADR1 => Inst_txserie1_CLOCK1_compteur(5), + ADR2 => N15429, + ADR3 => CHOICE116, + O => Inst_txserie1_CLOCK1_n0005 + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_61 : X_LUT2 generic map( INIT => X"5" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(3), - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, + ADR0 => Inst_txserie1_CLOCK1_compteur(6), + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, ADR1 => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3_57 : X_MUX2 + Inst_txserie1_CLOCK1_ckout_46 : X_FF + generic map( + INIT => '0' + ) port map ( - IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, - IA => Inst_rxserie1_CLOCK1_compteur(3), - SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3 + I => Inst_txserie1_CLOCK1_n0005, + RST => Inst_txserie1_CLOCK1_ckout_GSR_OR, + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_ckout, + CE => VCC, + SET => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_3 : X_XOR2 + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_71 : X_LUT2 + generic map( + INIT => X"5" + ) port map ( - I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, - I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, - O => Inst_rxserie1_CLOCK1_compteur_n0005(3) + ADR0 => Inst_txserie1_CLOCK1_compteur(7), + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, + ADR1 => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_41 : X_LUT2 + Inst_txserie1_CLOCK1_compteur_n00061 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_n0005, + ADR1 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_n0006 + ); + Inst_txserie1_FIFO1_state_read_FFd3_In1 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => Inst_txserie1_flagreg(3), + ADR1 => Inst_txserie1_TX1_n0034, + ADR2 => Inst_txserie1_TX1_TXDATARDY, + ADR3 => Inst_txserie1_FIFO1_state_read_FFd4, + O => Inst_txserie1_FIFO1_state_read_FFd3_In + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_91 : X_LUT2 generic map( INIT => X"5" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(4), - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, + ADR0 => Inst_txserie1_CLOCK1_compteur(9), + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, ADR1 => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4_58 : X_MUX2 + Inst_txserie1_CLOCK1_compteur_0_n00001 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur_n0001(0), + ADR1 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_0_0_n0000 + ); + Inst_txserie1_CLOCK1_compteur_9 : X_FF + generic map( + INIT => '0' + ) port map ( - IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, - IA => Inst_rxserie1_CLOCK1_compteur(4), - SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 + I => Inst_txserie1_CLOCK1_compteur_n0001(9), + RST => Inst_txserie1_CLOCK1_compteur_9_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_compteur(9), + CE => VCC + ); + Inst_txserie1_CLOCK1_compteur_8 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_CLOCK1_compteur_n0001(8), + RST => Inst_txserie1_CLOCK1_compteur_8_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_compteur(8), + CE => VCC + ); + Inst_txserie1_CLOCK1_compteur_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_CLOCK1_compteur_n0001(0), + RST => Inst_txserie1_CLOCK1_compteur_0_GSR_OR, + SET => Inst_txserie1_CLOCK1_compteur_0_0_n0001, + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_compteur(0), + CE => VCC + ); + Inst_txserie1_CLOCK1_compteur_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_CLOCK1_compteur_n0001(1), + RST => Inst_txserie1_CLOCK1_compteur_1_GSR_OR, + SET => Inst_txserie1_CLOCK1_compteur_0_1_n0001, + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_compteur(1), + CE => VCC + ); + Inst_txserie1_CLOCK1_compteur_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_CLOCK1_compteur_n0001(2), + RST => Inst_txserie1_CLOCK1_compteur_2_GSR_OR, + SET => Inst_txserie1_CLOCK1_compteur_0_2_n0001, + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_compteur(2), + CE => VCC + ); + Inst_txserie1_CLOCK1_compteur_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_CLOCK1_compteur_n0001(3), + RST => Inst_txserie1_CLOCK1_compteur_3_GSR_OR, + SET => Inst_txserie1_CLOCK1_compteur_0_3_n0001, + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_compteur(3), + CE => VCC + ); + Inst_txserie1_CLOCK1_compteur_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_CLOCK1_compteur_n0001(4), + RST => Inst_txserie1_CLOCK1_compteur_4_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_compteur(4), + CE => VCC + ); + Inst_txserie1_CLOCK1_compteur_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_CLOCK1_compteur_n0001(5), + RST => Inst_txserie1_CLOCK1_compteur_5_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_compteur(5), + CE => VCC + ); + Inst_txserie1_CLOCK1_compteur_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_CLOCK1_compteur_n0001(6), + RST => Inst_txserie1_CLOCK1_compteur_6_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_compteur(6), + CE => VCC + ); + Inst_txserie1_CLOCK1_compteur_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_CLOCK1_compteur_n0001(7), + RST => Inst_txserie1_CLOCK1_compteur_7_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => clk_ref_BUFGP, + O => Inst_txserie1_CLOCK1_compteur(7), + CE => VCC + ); + Inst_txserie1_state_txload_2_SW15 : X_LUT3 + generic map( + INIT => X"01" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => Inst_txserie1_TX1_n0034, + ADR2 => Inst_txserie1_TX1_TXDATARDY, + O => CHOICE41 + ); + bus_adr_9_IBUF_47 : X_BUF + port map ( + I => bus_adr(9), + O => bus_adr_9_IBUF + ); + irqrxRX_OBUF_48 : X_BUF + port map ( + I => irqrxRX_OBUF, + O => irqrxRX_OBUF_GTS_TRI + ); + bus_adr_10_IBUF_49 : X_BUF + port map ( + I => bus_adr(10), + O => bus_adr_10_IBUF + ); + irqrxERR_OBUF_50 : X_BUF + port map ( + I => irqrxERR_OBUF, + O => irqrxERR_OBUF_GTS_TRI + ); + bus_adr_11_IBUF_51 : X_BUF + port map ( + I => bus_adr(11), + O => bus_adr_11_IBUF + ); + bus_adr_0_IBUF_52 : X_BUF + port map ( + I => bus_adr(0), + O => bus_adr_0_IBUF + ); + bus_adr_12_IBUF_53 : X_BUF + port map ( + I => bus_adr(12), + O => bus_adr_12_IBUF + ); + bus_adr_1_IBUF_54 : X_BUF + port map ( + I => bus_adr(1), + O => bus_adr_1_IBUF + ); + bus_adr_13_IBUF_55 : X_BUF + port map ( + I => bus_adr(13), + O => bus_adr_13_IBUF + ); + bus_adr_2_IBUF_56 : X_BUF + port map ( + I => bus_adr(2), + O => bus_adr_2_IBUF + ); + bus_adr_14_IBUF_57 : X_BUF + port map ( + I => bus_adr(14), + O => bus_adr_14_IBUF + ); + Inst_txserie1_CLOCK1_compteur_3_n00011 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0001(3), + O => Inst_txserie1_CLOCK1_compteur_0_3_n0001 + ); + Inst_txserie1_CLOCK1_compteur_3_n00001 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur_n0001(3), + ADR1 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_0_3_n0000 + ); + bus_adr_15_IBUF_58 : X_BUF + port map ( + I => bus_adr(15), + O => bus_adr_15_IBUF + ); + Inst_txserie1_CLOCK1_compteur_2_n00011 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_txserie1_RCONF_REG(1), + ADR1 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_0_2_n0001 + ); + Inst_txserie1_CLOCK1_compteur_1_n00011 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0001(1), + O => Inst_txserie1_CLOCK1_compteur_0_1_n0001 + ); + Inst_txserie1_CLOCK1_compteur_1_n00001 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur_n0001(1), + ADR1 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_0_1_n0000 + ); + Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_0_1 : X_LUT4 + generic map( + INIT => X"E444" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur_n0006, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(0), + ADR2 => Inst_txserie1_RCONF_REG(1), + ADR3 => Inst_txserie1_RCONF_REG(0), + O => Inst_txserie1_CLOCK1_compteur_n0001(0) + ); + Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_1_1 : X_LUT4 + generic map( + INIT => X"4EE4" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur_n0006, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(1), + ADR2 => Inst_txserie1_RCONF_REG(0), + ADR3 => Inst_txserie1_RCONF_REG(1), + O => Inst_txserie1_CLOCK1_compteur_n0001(1) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_4_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(4), + ADR2 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_n0001(4) + ); + Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_3_1 : X_LUT4 + generic map( + INIT => X"444E" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur_n0006, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(3), + ADR2 => Inst_txserie1_RCONF_REG(1), + ADR3 => Inst_txserie1_RCONF_REG(0), + O => Inst_txserie1_CLOCK1_compteur_n0001(3) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_5_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(5), + ADR2 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_n0001(5) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_6_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(6), + ADR2 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_n0001(6) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_7_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(7), + ADR2 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_n0001(7) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_8_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(8), + ADR2 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_n0001(8) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_9_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(9), + ADR2 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_n0001(9) + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_81 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur(8), + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, + ADR1 => GND + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6_59 : X_MUX2 + port map ( + IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, + IA => Inst_txserie1_CLOCK1_compteur(6), + SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6 + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_9 : X_XOR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, + I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8, + O => Inst_txserie1_CLOCK1_compteur_n0005(9) + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0_60 : X_MUX2 + port map ( + IB => N6239, + IA => Inst_rxserie1_RFLAG_output(7), + SEL => Inst_txserie1_CLOCK1_compteur_0_rt, + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0 + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_0 : X_XOR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_0_rt, + I1 => N6239, + O => Inst_txserie1_CLOCK1_compteur_n0005(0) + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_11 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur(1), + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, + ADR1 => GND + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1_61 : X_MUX2 + port map ( + IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, + IA => Inst_txserie1_CLOCK1_compteur(1), + SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1 + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_1 : X_XOR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, + I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, + O => Inst_txserie1_CLOCK1_compteur_n0005(1) + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_21 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur(2), + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, + ADR1 => GND + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2_62 : X_MUX2 + port map ( + IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, + IA => Inst_txserie1_CLOCK1_compteur(2), + SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2 + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_2 : X_XOR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, + I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, + O => Inst_txserie1_CLOCK1_compteur_n0005(2) + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_31 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur(3), + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, + ADR1 => GND + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3_63 : X_MUX2 + port map ( + IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, + IA => Inst_txserie1_CLOCK1_compteur(3), + SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3 + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_3 : X_XOR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, + I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, + O => Inst_txserie1_CLOCK1_compteur_n0005(3) + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_41 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur(4), + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, + ADR1 => GND + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4_64 : X_MUX2 + port map ( + IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, + IA => Inst_txserie1_CLOCK1_compteur(4), + SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_sum_4 : X_XOR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, + I1 => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, + O => Inst_txserie1_CLOCK1_compteur_n0005(4) + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_51 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur(5), + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, + ADR1 => GND + ); + Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5_65 : X_MUX2 + port map ( + IB => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, + IA => Inst_txserie1_CLOCK1_compteur(5), + SEL => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, + O => Inst_txserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_8 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, + O => Inst_rxserie1_CLOCK1_compteur_n0005(8) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8_66 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, + IA => Inst_rxserie1_CLOCK1_compteur(8), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_6 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, + O => Inst_rxserie1_CLOCK1_compteur_n0005(6) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7_67 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, + IA => Inst_rxserie1_CLOCK1_compteur(7), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7 + ); + Inst_rxserie1_CLOCK1_compteur_0_n00011 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(0), + O => Inst_rxserie1_CLOCK1_compteur_0_0_n0001 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_7 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, + O => Inst_rxserie1_CLOCK1_compteur_n0005(7) + ); + Inst_txserie1_TX1_n003417 : X_LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + ADR0 => CHOICE144, + ADR1 => Inst_txserie1_TX1_TSR(5), + ADR2 => Inst_txserie1_TX1_TSR(4), + ADR3 => N15433, + O => Inst_txserie1_TX1_n0034 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_61 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(6), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_ckout_68 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_n0005, + RST => Inst_rxserie1_CLOCK1_ckout_GSR_OR, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_ckout, + CE => VCC, + SET => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_71 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(7), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_n00061 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_n0006 + ); + Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_9_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_n0005, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(9), + ADR2 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_n0001(9) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_91 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(9), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_0_n00001 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(0), + ADR1 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_0_0_n0000 + ); + Inst_rxserie1_CLOCK1_compteur_9 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(9), + RST => Inst_rxserie1_CLOCK1_compteur_9_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(9), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_8 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(8), + RST => Inst_rxserie1_CLOCK1_compteur_8_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(8), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(0), + RST => Inst_rxserie1_CLOCK1_compteur_0_GSR_OR, + SET => Inst_rxserie1_CLOCK1_compteur_0_0_n0001, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(0), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(1), + RST => Inst_rxserie1_CLOCK1_compteur_1_GSR_OR, + SET => Inst_rxserie1_CLOCK1_compteur_0_1_n0001, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(1), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(2), + RST => Inst_rxserie1_CLOCK1_compteur_2_GSR_OR, + SET => Inst_rxserie1_CLOCK1_compteur_0_2_n0001, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(2), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(3), + RST => Inst_rxserie1_CLOCK1_compteur_3_GSR_OR, + SET => Inst_rxserie1_CLOCK1_compteur_0_3_n0001, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(3), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(4), + RST => Inst_rxserie1_CLOCK1_compteur_4_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(4), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(5), + RST => Inst_rxserie1_CLOCK1_compteur_5_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(5), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(6), + RST => Inst_rxserie1_CLOCK1_compteur_6_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(6), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(7), + RST => Inst_rxserie1_CLOCK1_compteur_7_GSR_OR, + SET => Inst_rxserie1_RFLAG_output(7), + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(7), + CE => VCC + ); + bus_adr_3_IBUF_69 : X_BUF + port map ( + I => bus_adr(3), + O => bus_adr_3_IBUF + ); + Inst_txserie1_CLOCK1_compteur_2_n00001 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => Inst_txserie1_RCONF_REG(1), + O => Inst_txserie1_CLOCK1_compteur_0_2_n0000 + ); + bus_adr_4_IBUF_70 : X_BUF + port map ( + I => bus_adr(4), + O => bus_adr_4_IBUF + ); + IOW_IBUF_71 : X_BUF + port map ( + I => IOW, + O => IOW_IBUF + ); + bus_adr_5_IBUF_72 : X_BUF + port map ( + I => bus_adr(5), + O => bus_adr_5_IBUF + ); + IOR_IBUF_73 : X_BUF + port map ( + I => IOR, + O => IOR_IBUF + ); + bus_adr_6_IBUF_74 : X_BUF + port map ( + I => bus_adr(6), + O => bus_adr_6_IBUF + ); + AEN_IBUF_75 : X_BUF + port map ( + I => AEN, + O => AEN_IBUF + ); + bus_adr_7_IBUF_76 : X_BUF + port map ( + I => bus_adr(7), + O => bus_adr_7_IBUF + ); + rxin1_IBUF_77 : X_BUF + port map ( + I => rxin1, + O => rxin1_IBUF + ); + bus_adr_8_IBUF_78 : X_BUF + port map ( + I => bus_adr(8), + O => bus_adr_8_IBUF + ); + Inst_rxserie1_CLOCK1_compteur_3_n00011 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(3), + O => Inst_rxserie1_CLOCK1_compteur_0_3_n0001 + ); + Inst_rxserie1_CLOCK1_compteur_3_n00001 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(3), + ADR1 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_0_3_n0000 + ); + Inst_rxserie1_CLOCK1_compteur_2_n00011 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_rxserie1_RCONF_REG(1), + ADR1 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_0_2_n0001 + ); + Inst_rxserie1_CLOCK1_compteur_1_n00011 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(1), + O => Inst_rxserie1_CLOCK1_compteur_0_1_n0001 + ); + Inst_rxserie1_CLOCK1_compteur_1_n00001 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(1), + ADR1 => rst_BUFGP, + O => Inst_rxserie1_CLOCK1_compteur_0_1_n0000 + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_0_1 : X_LUT4 + generic map( + INIT => X"E444" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(0), + ADR2 => Inst_rxserie1_RCONF_REG(1), + ADR3 => Inst_rxserie1_RCONF_REG(0), + O => Inst_rxserie1_CLOCK1_compteur_n0001(0) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_1_1 : X_LUT4 + generic map( + INIT => X"4EE4" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(1), + ADR2 => Inst_rxserie1_RCONF_REG(0), + ADR3 => Inst_rxserie1_RCONF_REG(1), + O => Inst_rxserie1_CLOCK1_compteur_n0001(1) + ); + Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_2_1 : X_LUT4 + generic map( + INIT => X"10FE" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_n0005, + ADR1 => rst_BUFGP, + ADR2 => Inst_txserie1_CLOCK1_compteur_n0005(2), + ADR3 => Inst_txserie1_RCONF_REG(1), + O => Inst_txserie1_CLOCK1_compteur_n0001(2) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_3_1 : X_LUT4 + generic map( + INIT => X"444E" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(3), + ADR2 => Inst_rxserie1_RCONF_REG(1), + ADR3 => Inst_rxserie1_RCONF_REG(0), + O => Inst_rxserie1_CLOCK1_compteur_n0001(3) + ); + Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_4_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_n0005, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(4), + ADR2 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_n0001(4) + ); + Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_5_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_n0005, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(5), + ADR2 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_n0001(5) + ); + Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_6_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_n0005, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(6), + ADR2 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_n0001(6) + ); + Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_7_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_n0005, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(7), + ADR2 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_n0001(7) + ); + Inst_txserie1_CLOCK1_compteur_Mmux_n0001_Result_8_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_n0005, + ADR1 => Inst_txserie1_CLOCK1_compteur_n0005(8), + ADR2 => rst_BUFGP, + O => Inst_txserie1_CLOCK1_compteur_n0001(8) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_81 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(8), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6_79 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, + IA => Inst_rxserie1_CLOCK1_compteur(6), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_9 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8, + O => Inst_rxserie1_CLOCK1_compteur_n0005(9) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0_80 : X_MUX2 + port map ( + IB => N6239, + IA => Inst_rxserie1_RFLAG_output(7), + SEL => Inst_rxserie1_CLOCK1_compteur_0_rt, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_0 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_0_rt, + I1 => N6239, + O => Inst_rxserie1_CLOCK1_compteur_n0005(0) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_11 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(1), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1_81 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, + IA => Inst_rxserie1_CLOCK1_compteur(1), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_1 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, + O => Inst_rxserie1_CLOCK1_compteur_n0005(1) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_21 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(2), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2_82 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, + IA => Inst_rxserie1_CLOCK1_compteur(2), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_2 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, + O => Inst_rxserie1_CLOCK1_compteur_n0005(2) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_31 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(3), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3_83 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, + IA => Inst_rxserie1_CLOCK1_compteur(3), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_3 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, + O => Inst_rxserie1_CLOCK1_compteur_n0005(3) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_41 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(4), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4_84 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, + IA => Inst_rxserie1_CLOCK1_compteur(4), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_4 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, + O => Inst_rxserie1_CLOCK1_compteur_n0005(4) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_51 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(5), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5_85 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, + IA => Inst_rxserie1_CLOCK1_compteur(5), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 + ); + Inst_rxserie1_RC1_n00511 : X_LUT3 + generic map( + INIT => X"DF" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => rxin1_IBUF, + ADR2 => Inst_rxserie1_RC1_RX1, + O => Inst_rxserie1_RC1_n0051 + ); + Inst_txserie1_TX1_n00391 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_n0039, + ADR1 => GND + ); + Inst_txserie1_TX1_THR_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_inter_data(6), + RST => Inst_txserie1_TX1_THR_6_GSR_OR, + CLK => Inst_txserie1_txload, + O => Inst_txserie1_TX1_THR(6), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_THR_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_inter_data(5), + RST => Inst_txserie1_TX1_THR_5_GSR_OR, + CLK => Inst_txserie1_txload, + O => Inst_txserie1_TX1_THR(5), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_THR_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_inter_data(3), + RST => Inst_txserie1_TX1_THR_3_GSR_OR, + CLK => Inst_txserie1_txload, + O => Inst_txserie1_TX1_THR(3), + CE => VCC, + SET => GND + ); + Inst_rxserie1_CLOCK1_n000529 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(8), + ADR1 => Inst_rxserie1_CLOCK1_compteur(9), + ADR2 => Inst_rxserie1_CLOCK1_compteur(4), + ADR3 => Inst_rxserie1_CLOCK1_compteur(5), + O => CHOICE135 + ); + Inst_txserie1_TX1_n00339 : X_LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + ADR0 => Inst_txserie1_TX1_TSR(3), + ADR1 => Inst_txserie1_TX1_TSR(2), + ADR2 => Inst_txserie1_TX1_TAG2, + ADR3 => Inst_txserie1_TX1_TAG1, + O => CHOICE98 + ); + Inst_txserie1_TX1_n00321 : X_LUT3 + generic map( + INIT => X"01" + ) + port map ( + ADR0 => Inst_txserie1_TX1_CNT(2), + ADR1 => Inst_txserie1_TX1_CNT(0), + ADR2 => Inst_txserie1_TX1_CNT(1), + O => Inst_txserie1_TX1_n0032 + ); + Inst_txserie1_TX1_n00311 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_txserie1_TX1_WRITE2, + ADR1 => Inst_txserie1_TX1_WRITE1, + O => Inst_txserie1_TX1_n0031 + ); + Inst_txserie1_TX1_n00301 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TXDATARDY, + O => Inst_txserie1_TX1_n0030 + ); + Inst_txserie1_TX1_TSR_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0027, + RST => Inst_txserie1_TX1_TSR_0_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TSR(0), + CE => VCC, + SET => GND + ); + Inst_rxserie1_RC1_RXCNT_3_rt_86 : X_LUT2 + generic map( + INIT => X"A" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXCNT(3), + O => Inst_rxserie1_RC1_RXCNT_3_rt, + ADR1 => GND + ); + Inst_rxserie1_RC1_RXCNT_2_rt_87 : X_LUT2 + generic map( + INIT => X"A" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXCNT(2), + O => Inst_rxserie1_RC1_RXCNT_2_rt, + ADR1 => GND + ); + Inst_txserie1_TX1_n00181 : X_LUT4 + generic map( + INIT => X"6F66" + ) + port map ( + ADR0 => Inst_txserie1_TX1_TSR(0), + ADR1 => Inst_txserie1_TX1_TXPARITY, + ADR2 => Inst_txserie1_TX1_n0034, + ADR3 => Inst_txserie1_TX1_TXDATARDY, + O => Inst_txserie1_TX1_n0018 + ); + Inst_txserie1_TX1_TSR_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0026, + RST => Inst_txserie1_TX1_TSR_1_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TSR(1), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_TXRDY1 : X_LUT2 + generic map( + INIT => X"1" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TXDATARDY, + O => Inst_txserie1_txready + ); + Inst_rxserie1_CLOCK1_compteur_2_n00001 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => Inst_rxserie1_RCONF_REG(1), + O => Inst_rxserie1_CLOCK1_compteur_0_2_n0000 + ); + Inst_txserie1_TX1_THR_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_inter_data(4), + RST => Inst_txserie1_TX1_THR_4_GSR_OR, + CLK => Inst_txserie1_txload, + O => Inst_txserie1_TX1_THR(4), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_CNT_Madd_n0000_n00061 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_txserie1_TX1_CNT(0), + O => Inst_txserie1_TX1_CNT_n0000(0), + ADR1 => GND + ); + Inst_txserie1_TX1_n00171 : X_LUT3 + generic map( + INIT => X"BA" + ) + port map ( + ADR0 => Inst_txserie1_TX1_TAG2, + ADR1 => Inst_txserie1_TX1_n0034, + ADR2 => Inst_txserie1_TX1_TXDATARDY, + O => Inst_txserie1_TX1_n0017 + ); + Inst_txserie1_TX1_Mmux_n0027_Result1 : X_LUT4 + generic map( + INIT => X"DC8C" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TSR(1), + ADR2 => Inst_txserie1_TX1_TXDATARDY, + ADR3 => Inst_txserie1_TX1_THR(0), + O => Inst_txserie1_TX1_n0027 + ); + Inst_txserie1_TX1_Mmux_n0026_Result1 : X_LUT4 + generic map( + INIT => X"DC8C" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TSR(2), + ADR2 => Inst_txserie1_TX1_TXDATARDY, + ADR3 => Inst_txserie1_TX1_THR(1), + O => Inst_txserie1_TX1_n0026 + ); + Inst_txserie1_TX1_Mmux_n0025_Result1 : X_LUT4 + generic map( + INIT => X"DC8C" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TSR(3), + ADR2 => Inst_txserie1_TX1_TXDATARDY, + ADR3 => Inst_txserie1_TX1_THR(2), + O => Inst_txserie1_TX1_n0025 + ); + Inst_txserie1_TX1_Mmux_n0024_Result1 : X_LUT4 + generic map( + INIT => X"DC8C" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TSR(4), + ADR2 => Inst_txserie1_TX1_TXDATARDY, + ADR3 => Inst_txserie1_TX1_THR(3), + O => Inst_txserie1_TX1_n0024 + ); + Inst_txserie1_TX1_Mmux_n0023_Result1 : X_LUT4 + generic map( + INIT => X"DC8C" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TSR(5), + ADR2 => Inst_txserie1_TX1_TXDATARDY, + ADR3 => Inst_txserie1_TX1_THR(4), + O => Inst_txserie1_TX1_n0023 + ); + Inst_txserie1_TX1_Mmux_n0022_Result1 : X_LUT4 + generic map( + INIT => X"DC8C" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TSR(6), + ADR2 => Inst_txserie1_TX1_TXDATARDY, + ADR3 => Inst_txserie1_TX1_THR(5), + O => Inst_txserie1_TX1_n0022 + ); + Inst_txserie1_TX1_Mmux_n0021_Result1 : X_LUT4 + generic map( + INIT => X"DC8C" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => Inst_txserie1_TX1_TSR(7), + ADR2 => Inst_txserie1_TX1_TXDATARDY, + ADR3 => Inst_txserie1_TX1_THR(6), + O => Inst_txserie1_TX1_n0021 + ); + Inst_txserie1_TX1_TXDONE1_88 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_txserie1_TX1_TXDONE, + SET => Inst_txserie1_TX1_TXDONE1_GSR_OR, + CLK => Inst_txserie1_CLOCK1_ckout, + O => Inst_txserie1_TX1_TXDONE1, + CE => VCC, + RST => GND + ); + Inst_txserie1_TX1_WRITE1_89 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_txserie1_txload, + SET => Inst_txserie1_TX1_WRITE1_GSR_OR, + CLK => Inst_txserie1_CLOCK1_ckout, + O => Inst_txserie1_TX1_WRITE1, + CE => VCC, + RST => GND + ); + Inst_txserie1_TX1_WRITE2_90 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_txserie1_TX1_WRITE1, + SET => Inst_txserie1_TX1_WRITE2_GSR_OR, + CLK => Inst_txserie1_CLOCK1_ckout, + O => Inst_txserie1_TX1_WRITE2, + CE => VCC, + RST => GND + ); + Inst_txserie1_TX1_TXDATARDY_91 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0031, + CE => Inst_txserie1_TX1_n0048, + RST => Inst_txserie1_TX1_TXDATARDY_GSR_OR, + CLK => Inst_txserie1_CLOCK1_ckout, + O => Inst_txserie1_TX1_TXDATARDY, + SET => GND + ); + Inst_txserie1_TX1_THR_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_inter_data(7), + RST => Inst_txserie1_TX1_THR_7_GSR_OR, + CLK => Inst_txserie1_txload, + O => Inst_txserie1_TX1_THR(7), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_TXCLK_92 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0039, + CE => Inst_txserie1_TX1_n0032, + RST => Inst_txserie1_TX1_TXCLK_GSR_OR, + CLK => Inst_txserie1_CLOCK1_ckout, + O => Inst_txserie1_TX1_TXCLK, + SET => GND + ); + Inst_txserie1_TX1_CNT_Madd_n0000_Mxor_Result_2_Result1 : X_LUT3 + generic map( + INIT => X"6A" + ) + port map ( + ADR0 => Inst_txserie1_TX1_CNT(2), + ADR1 => Inst_txserie1_TX1_CNT(0), + ADR2 => Inst_txserie1_TX1_CNT(1), + O => Inst_txserie1_TX1_CNT_n0000(2) + ); + Inst_txserie1_TX1_TAG2_93 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0030, + RST => Inst_txserie1_TX1_TAG2_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TAG2, + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_TAG1_94 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0017, + RST => Inst_txserie1_TX1_TAG1_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TAG1, + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_TXPARITY_95 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_txserie1_TX1_n0018, + SET => Inst_txserie1_TX1_TXPARITY_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TXPARITY, + CE => VCC, + RST => GND + ); + Inst_txserie1_TX1_TX_96 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_txserie1_TX1_n0019, + SET => Inst_txserie1_TX1_TX_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TX, + CE => VCC, + RST => GND + ); + Inst_txserie1_TX1_TSR_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0020, + RST => Inst_txserie1_TX1_TSR_7_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TSR(7), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_TSR_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0021, + RST => Inst_txserie1_TX1_TSR_6_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TSR(6), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_TSR_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0022, + RST => Inst_txserie1_TX1_TSR_5_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TSR(5), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_TSR_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0023, + RST => Inst_txserie1_TX1_TSR_4_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TSR(4), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_TSR_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0024, + RST => Inst_txserie1_TX1_TSR_3_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TSR(3), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_TSR_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_n0025, + RST => Inst_txserie1_TX1_TSR_2_GSR_OR, + CLK => Inst_txserie1_TX1_TXCLK, + O => Inst_txserie1_TX1_TSR(2), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_THR_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_inter_data(0), + RST => Inst_txserie1_TX1_THR_0_GSR_OR, + CLK => Inst_txserie1_txload, + O => Inst_txserie1_TX1_THR(0), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_THR_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_inter_data(1), + RST => Inst_txserie1_TX1_THR_1_GSR_OR, + CLK => Inst_txserie1_txload, + O => Inst_txserie1_TX1_THR(1), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_THR_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_inter_data(2), + RST => Inst_txserie1_TX1_THR_2_GSR_OR, + CLK => Inst_txserie1_txload, + O => Inst_txserie1_TX1_THR(2), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_CNT_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_CNT_n0000(2), + RST => Inst_txserie1_TX1_CNT_2_GSR_OR, + CLK => Inst_txserie1_CLOCK1_ckout, + O => Inst_txserie1_TX1_CNT(2), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_CNT_Madd_n0000_Mxor_Result_1_Result1 : X_LUT2 + generic map( + INIT => X"6" + ) + port map ( + ADR0 => Inst_txserie1_TX1_CNT(0), + ADR1 => Inst_txserie1_TX1_CNT(1), + O => Inst_txserie1_TX1_CNT_n0000(1) + ); + Inst_txserie1_TX1_CNT_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_txserie1_TX1_CNT_n0000(0), + RST => Inst_txserie1_TX1_CNT_0_GSR_OR, + CLK => Inst_txserie1_CLOCK1_ckout, + O => Inst_txserie1_TX1_CNT(0), + CE => VCC, + SET => GND + ); + Inst_txserie1_TX1_n003417_SW0 : X_LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + ADR0 => Inst_txserie1_TX1_TSR(3), + ADR1 => Inst_txserie1_TX1_TSR(2), + ADR2 => Inst_txserie1_TX1_TSR(1), + ADR3 => Inst_txserie1_TX1_TSR(0), + O => N15433 + ); + Inst_rxserie1_CLOCK1_compteur_0_rt_97 : X_LUT2 + generic map( + INIT => X"A" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(0), + O => Inst_rxserie1_CLOCK1_compteur_0_rt, + ADR1 => GND + ); + Inst_txserie1_TX1_n003310 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => CHOICE95, + ADR1 => CHOICE98, + O => Inst_txserie1_TX1_n0033 + ); + Inst_txserie1_CLOCK1_n000539_SW0 : X_LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur(6), + ADR1 => Inst_txserie1_CLOCK1_compteur(7), + ADR2 => Inst_txserie1_CLOCK1_compteur(8), + ADR3 => Inst_txserie1_CLOCK1_compteur(9), + O => N15429 + ); + Inst_txserie1_TX1_n00334 : X_LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + ADR0 => Inst_txserie1_TX1_TSR(7), + ADR1 => Inst_txserie1_TX1_TSR(6), + ADR2 => Inst_txserie1_TX1_TSR(5), + ADR3 => Inst_txserie1_TX1_TSR(4), + O => CHOICE95 + ); + Inst_decodisa_reg_select24 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => bus_adr_15_IBUF, + ADR1 => bus_adr_8_IBUF, + ADR2 => AEN_IBUF, + O => CHOICE68 + ); + Inst_txserie1_CLOCK1_n000529 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => Inst_txserie1_CLOCK1_compteur(0), + ADR1 => Inst_txserie1_CLOCK1_compteur(1), + ADR2 => Inst_txserie1_CLOCK1_compteur(2), + ADR3 => Inst_txserie1_CLOCK1_compteur(3), + O => CHOICE116 + ); + Inst_txserie1_TX1_n0019_98 : X_LUT3 + generic map( + INIT => X"8D" + ) + port map ( + ADR0 => Inst_txserie1_TX1_n0034, + ADR1 => N14920, + ADR2 => Inst_txserie1_TX1_TXDATARDY, + O => Inst_txserie1_TX1_n0019 + ); + Inst_txserie1_state_txload_0_SW112 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => CHOICE36, + O => Inst_txserie1_state_txload_0_Q + ); + Inst_txserie1_FIFO1_state_read_FFd4_In_99 : X_LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + ADR0 => N15477, + ADR1 => Inst_txserie1_flagreg(3), + ADR2 => Inst_txserie1_TX1_n0034, + ADR3 => Inst_txserie1_TX1_TXDATARDY, + O => Inst_txserie1_FIFO1_state_read_FFd4_In + ); + Inst_txserie1_FIFO1_state_read_FFd4_In_SW1 : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => Inst_txserie1_FIFO1_dready, + ADR1 => Inst_txserie1_FIFO1_state_read_FFd4, + ADR2 => Inst_txserie1_FIFO1_state_read_FFd1, + O => N15477 + ); + Inst_decodisa_reg_select32_SW0 : X_LUT4 + generic map( + INIT => X"FEFF" + ) + port map ( + ADR0 => bus_adr_14_IBUF, + ADR1 => bus_adr_13_IBUF, + ADR2 => bus_adr_12_IBUF, + ADR3 => CHOICE68, + O => N15437 + ); + Inst_rxserie1_FIFO1_state_read_FFd1_In_100 : X_LUT4 + generic map( + INIT => X"0C08" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_state_read_FFd2, + ADR1 => cs(1), + ADR2 => N14869, + ADR3 => Inst_rxserie1_FIFO1_state_read_FFd1, + O => Inst_rxserie1_FIFO1_state_read_FFd1_In + ); + Inst_txserie1_RFLAG_n00071 : X_LUT4 + generic map( + INIT => X"FB00" + ) + port map ( + ADR0 => IOR_IBUF, + ADR1 => IOW_IBUF, + ADR2 => AEN_IBUF, + ADR3 => cs(6), + O => Inst_txserie1_RFLAG_n0007 + ); + Inst_rxserie1_RC1_RXCNT_1_rt_101 : X_LUT2 + generic map( + INIT => X"A" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXCNT(1), + O => Inst_rxserie1_RC1_RXCNT_1_rt, + ADR1 => GND + ); + Inst_rxserie1_FIFO1_state_read_FFd1_In_SW0 : X_LUT4 + generic map( + INIT => X"FEFF" + ) + port map ( + ADR0 => rst_BUFGP, + ADR1 => IOR_IBUF, + ADR2 => AEN_IBUF, + ADR3 => IOW_IBUF, + O => N14869 + ); + Inst_decodisa_reg_select32 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_9_IBUF, + ADR1 => bus_adr_10_IBUF, + ADR2 => bus_adr_11_IBUF, + ADR3 => N15437, + O => Inst_decodisa_reg_select + ); + N6828_102 : X_LUT4 + generic map( + INIT => X"F7F5" + ) + port map ( + ADR0 => rw, + ADR1 => cs(3), + ADR2 => rst_BUFGP, + ADR3 => N14659, + O => N6828 + ); + Inst_txserie1_state_txload_0_SW111 : X_LUT4 + generic map( + INIT => X"4544" + ) + port map ( + ADR0 => Inst_txserie1_txready, + ADR1 => Inst_txserie1_state_txload_2_Q, + ADR2 => Inst_txserie1_FIFO1_dready, + ADR3 => Inst_txserie1_state_txload_0_Q, + O => CHOICE36 + ); + N6828_SW0 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => cs(5), + ADR1 => cs(6), + ADR2 => cs(1), + ADR3 => cs(2), + O => N14659 + ); + Inst_txserie1_TX1_TXDONE2 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => CHOICE144, + ADR1 => Inst_txserie1_TX1_TSR(5), + ADR2 => Inst_txserie1_TX1_TSR(4), + ADR3 => N15433, + O => Inst_txserie1_TX1_TXDONE + ); + bus_data_6_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_6_IOBUF + ); + bus_data_3_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_3_IOBUF + ); + bus_data_2_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_2_IOBUF + ); + bus_data_4_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_4_IOBUF + ); + bus_data_5_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_5_IOBUF + ); + bus_data_0_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_0_IOBUF + ); + bus_data_7_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_7_IOBUF + ); + bus_data_1_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_1_IOBUF + ); + bus_data_6_IOBUF_OBUFT : X_TRI + port map ( + CTL => bus_data_6_IOBUF_OBUFT_GTS_AND, + I => bus_data_6_IOBUF, + O => bus_data(6) + ); + bus_data_6_IOBUF_IBUF : X_BUF + port map ( + I => bus_data(6), + O => N15397 + ); + Inst_rxserie1_FIFO1_fifo0_BU232 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N47, + O => Inst_rxserie1_inter_fifo(7), + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU230 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N48, + O => Inst_rxserie1_inter_fifo(6), + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU228 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N49, + O => Inst_rxserie1_inter_fifo(5), + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU226 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N50, + O => Inst_rxserie1_inter_fifo(4), + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU224 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N51, + O => Inst_rxserie1_inter_fifo(3), + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU222 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N52, + O => Inst_rxserie1_inter_fifo(2), + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU220 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N53, + O => Inst_rxserie1_inter_fifo(1), + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU218 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N54, + O => Inst_rxserie1_inter_fifo(0), + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU214 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(7), + Q => Inst_rxserie1_FIFO1_fifo0_N47, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU213 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(6), + Q => Inst_rxserie1_FIFO1_fifo0_N48, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU212 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(5), + Q => Inst_rxserie1_FIFO1_fifo0_N49, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU211 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(4), + Q => Inst_rxserie1_FIFO1_fifo0_N50, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU210 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(3), + Q => Inst_rxserie1_FIFO1_fifo0_N51, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU209 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(2), + Q => Inst_rxserie1_FIFO1_fifo0_N52, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU208 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(1), + Q => Inst_rxserie1_FIFO1_fifo0_N53, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU207 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(0), + Q => Inst_rxserie1_FIFO1_fifo0_N54, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU204 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N1, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N1271, + O => Inst_rxserie1_flagreg(3), + SSET => rst_BUFGP, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU203 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N1143, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N1142, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1271 + ); + Inst_rxserie1_FIFO1_fifo0_BU196 : X_LUT4 + generic map( + INIT => X"2222" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N73, + ADR1 => Inst_rxserie1_FIFO1_wr_en, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1143 + ); + Inst_rxserie1_FIFO1_fifo0_BU190 : X_LUT4 + generic map( + INIT => X"4040" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_wr_en, + ADR1 => Inst_rxserie1_FIFO1_rd_en, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N74, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1142 + ); + Inst_rxserie1_FIFO1_fifo0_BU183 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1110, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N74, + SEL => Inst_rxserie1_FIFO1_fifo0_N1113 + ); + Inst_rxserie1_FIFO1_fifo0_BU182 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1113 + ); + Inst_rxserie1_FIFO1_fifo0_BU180 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1104, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1110, + SEL => Inst_rxserie1_FIFO1_fifo0_N1107 + ); + Inst_rxserie1_FIFO1_fifo0_BU179 : X_LUT4 + generic map( + INIT => X"9009" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N17, + O => Inst_rxserie1_FIFO1_fifo0_N1107 + ); + Inst_rxserie1_FIFO1_fifo0_BU177 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1104, + SEL => Inst_rxserie1_FIFO1_fifo0_N1101 + ); + Inst_rxserie1_FIFO1_fifo0_BU176 : X_LUT4 + generic map( + INIT => X"9009" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N1, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N19, + O => Inst_rxserie1_FIFO1_fifo0_N1101 + ); + Inst_rxserie1_FIFO1_fifo0_BU172 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1037, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N73, + SEL => Inst_rxserie1_FIFO1_fifo0_N1040 + ); + Inst_rxserie1_FIFO1_fifo0_BU171 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1040 + ); + Inst_rxserie1_FIFO1_fifo0_BU169 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1031, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1037, + SEL => Inst_rxserie1_FIFO1_fifo0_N1034 + ); + Inst_rxserie1_FIFO1_fifo0_BU168 : X_LUT4 + generic map( + INIT => X"9009" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N17, + O => Inst_rxserie1_FIFO1_fifo0_N1034 + ); + Inst_rxserie1_FIFO1_fifo0_BU166 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1031, + SEL => Inst_rxserie1_FIFO1_fifo0_N1028 + ); + Inst_rxserie1_FIFO1_fifo0_BU165 : X_LUT4 + generic map( + INIT => X"9009" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N19, + O => Inst_rxserie1_FIFO1_fifo0_N1028 + ); + Inst_rxserie1_FIFO1_fifo0_BU161 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => NLW_Inst_rxserie1_FIFO1_fifo0_BU161_O_UNCONNECTED + ); + Inst_rxserie1_FIFO1_fifo0_BU155 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_fifo0_N17, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_flagreg(1) + ); + Inst_rxserie1_FIFO1_fifo0_BU149 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_flagreg(0) + ); + Inst_rxserie1_FIFO1_fifo0_BU143 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_fifo0_N19, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => NLW_Inst_rxserie1_FIFO1_fifo0_BU143_O_UNCONNECTED + ); + Inst_rxserie1_FIFO1_fifo0_BU137 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => NLW_Inst_rxserie1_FIFO1_fifo0_BU137_O_UNCONNECTED + ); + Inst_rxserie1_FIFO1_fifo0_BU131 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N716, + O => Inst_rxserie1_flagreg(2), + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU129 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N735, + I1 => Inst_rxserie1_FIFO1_fifo0_N738, + O => Inst_rxserie1_FIFO1_fifo0_N716 + ); + Inst_rxserie1_FIFO1_fifo0_BU128 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N738 + ); + Inst_rxserie1_FIFO1_fifo0_BU126 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N715, + O => Inst_rxserie1_FIFO1_fifo0_N17, + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU124 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N730, + I1 => Inst_rxserie1_FIFO1_fifo0_N733, + O => Inst_rxserie1_FIFO1_fifo0_N715 + ); + Inst_rxserie1_FIFO1_fifo0_BU123 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N730, + IA => Inst_rxserie1_FIFO1_fifo0_N17, + O => Inst_rxserie1_FIFO1_fifo0_N735, + SEL => Inst_rxserie1_FIFO1_fifo0_N733 + ); + Inst_rxserie1_FIFO1_fifo0_BU122 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N17, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N733 + ); + Inst_rxserie1_FIFO1_fifo0_BU120 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N714, + O => Inst_rxserie1_FIFO1_fifo0_N18, + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU118 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N725, + I1 => Inst_rxserie1_FIFO1_fifo0_N728, + O => Inst_rxserie1_FIFO1_fifo0_N714 + ); + Inst_rxserie1_FIFO1_fifo0_BU117 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N725, + IA => Inst_rxserie1_FIFO1_fifo0_N18, + O => Inst_rxserie1_FIFO1_fifo0_N730, + SEL => Inst_rxserie1_FIFO1_fifo0_N728 + ); + Inst_rxserie1_FIFO1_fifo0_BU116 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N18, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N728 + ); + Inst_rxserie1_FIFO1_fifo0_BU114 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N713, + O => Inst_rxserie1_FIFO1_fifo0_N19, + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU112 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N720, + I1 => Inst_rxserie1_FIFO1_fifo0_N723, + O => Inst_rxserie1_FIFO1_fifo0_N713 + ); + Inst_rxserie1_FIFO1_fifo0_BU111 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N720, + IA => Inst_rxserie1_FIFO1_fifo0_N19, + O => Inst_rxserie1_FIFO1_fifo0_N725, + SEL => Inst_rxserie1_FIFO1_fifo0_N723 + ); + Inst_rxserie1_FIFO1_fifo0_BU110 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N19, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N723 + ); + Inst_rxserie1_FIFO1_fifo0_BU108 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N712, + O => Inst_rxserie1_FIFO1_fifo0_N20, + SRST => rst_BUFGP, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU106 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N718, + I1 => Inst_rxserie1_FIFO1_fifo0_N717, + O => Inst_rxserie1_FIFO1_fifo0_N712 + ); + Inst_rxserie1_FIFO1_fifo0_BU105 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N718, + IA => Inst_rxserie1_FIFO1_fifo0_N20, + O => Inst_rxserie1_FIFO1_fifo0_N720, + SEL => Inst_rxserie1_FIFO1_fifo0_N717 + ); + Inst_rxserie1_FIFO1_fifo0_BU104 : X_LUT4 + generic map( + INIT => X"6666" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N20, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N717 + ); + Inst_rxserie1_FIFO1_fifo0_BU102 : X_LUT4 + generic map( + INIT => X"5555" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N718 + ); + Inst_rxserie1_FIFO1_fifo0_BU97 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N592, + O => Inst_rxserie1_FIFO1_fifo0_N4, + SSET => rst_BUFGP, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU95 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N606, + I1 => Inst_rxserie1_FIFO1_fifo0_N609, + O => Inst_rxserie1_FIFO1_fifo0_N592 + ); + Inst_rxserie1_FIFO1_fifo0_BU94 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N4, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N609 + ); + Inst_rxserie1_FIFO1_fifo0_BU92 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N591, + O => Inst_rxserie1_FIFO1_fifo0_N5, + SSET => rst_BUFGP, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU90 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N601, + I1 => Inst_rxserie1_FIFO1_fifo0_N604, + O => Inst_rxserie1_FIFO1_fifo0_N591 + ); + Inst_rxserie1_FIFO1_fifo0_BU89 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N601, + IA => Inst_rxserie1_FIFO1_fifo0_N5, + O => Inst_rxserie1_FIFO1_fifo0_N606, + SEL => Inst_rxserie1_FIFO1_fifo0_N604 + ); + Inst_rxserie1_FIFO1_fifo0_BU88 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N5, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N604 + ); + Inst_rxserie1_FIFO1_fifo0_BU86 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N590, + O => Inst_rxserie1_FIFO1_fifo0_N6, + SSET => rst_BUFGP, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU84 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N596, + I1 => Inst_rxserie1_FIFO1_fifo0_N599, + O => Inst_rxserie1_FIFO1_fifo0_N590 + ); + Inst_rxserie1_FIFO1_fifo0_BU83 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N596, + IA => Inst_rxserie1_FIFO1_fifo0_N6, + O => Inst_rxserie1_FIFO1_fifo0_N601, + SEL => Inst_rxserie1_FIFO1_fifo0_N599 + ); + Inst_rxserie1_FIFO1_fifo0_BU82 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N6, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N599 + ); + Inst_rxserie1_FIFO1_fifo0_BU80 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N589, + O => Inst_rxserie1_FIFO1_fifo0_N7, + SSET => rst_BUFGP, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU78 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N594, + I1 => Inst_rxserie1_FIFO1_fifo0_N593, + O => Inst_rxserie1_FIFO1_fifo0_N589 + ); + Inst_rxserie1_FIFO1_fifo0_BU77 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N594, + IA => Inst_rxserie1_FIFO1_fifo0_N7, + O => Inst_rxserie1_FIFO1_fifo0_N596, + SEL => Inst_rxserie1_FIFO1_fifo0_N593 + ); + Inst_rxserie1_FIFO1_fifo0_BU76 : X_LUT4 + generic map( + INIT => X"6666" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N7, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N593 + ); + Inst_rxserie1_FIFO1_fifo0_BU74 : X_LUT4 + generic map( + INIT => X"5555" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N594 + ); + Inst_rxserie1_FIFO1_fifo0_BU69 : X_LUT4 + generic map( + INIT => X"6666" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N2, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N33 + ); + Inst_rxserie1_FIFO1_fifo0_BU63 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N1, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N505, + O => Inst_rxserie1_FIFO1_fifo0_wr_ack, + SSET => rst_BUFGP, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU62 : X_LUT4 + generic map( + INIT => X"bbbb" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_wr_en, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N505 ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_4 : X_XOR2 + Inst_rxserie1_FIFO1_fifo0_BU55 : X_SFF + generic map( + INIT => '1' + ) port map ( - I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, - I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, - O => Inst_rxserie1_CLOCK1_compteur_n0005(4) + CE => Inst_rxserie1_FIFO1_fifo0_N1, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N456, + O => Inst_rxserie1_FIFO1_fifo0_wr_err, + SSET => rst_BUFGP, + SET => GSR, + RST => GND, + SRST => GND ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_51 : X_LUT2 + Inst_rxserie1_FIFO1_fifo0_BU54 : X_LUT4 generic map( - INIT => X"5" + INIT => X"7777" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(5), - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, - ADR1 => GND + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_wr_en, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N456 ); - Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5_59 : X_MUX2 + Inst_rxserie1_FIFO1_fifo0_BU47 : X_LUT4 + generic map( + INIT => X"2222" + ) port map ( - IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, - IA => Inst_rxserie1_CLOCK1_compteur(5), - SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, - O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 + ADR0 => Inst_rxserie1_FIFO1_wr_en, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N38 ); - Inst_rxserie1_CLOCK1_n000529 : X_LUT4 + Inst_rxserie1_FIFO1_fifo0_BU41 : X_LUT4 generic map( - INIT => X"0001" + INIT => X"2222" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(0), - ADR1 => Inst_rxserie1_CLOCK1_compteur(1), - ADR2 => Inst_rxserie1_CLOCK1_compteur(2), - ADR3 => Inst_rxserie1_CLOCK1_compteur(3), - O => CHOICE64 + ADR0 => Inst_rxserie1_FIFO1_wr_en, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N3 ); - Inst_rxserie1_RC1_RXCNT_3_rt_60 : X_LUT2 + Inst_rxserie1_FIFO1_fifo0_BU35 : X_SFF generic map( - INIT => X"A" + INIT => '1' ) port map ( - ADR0 => Inst_rxserie1_RC1_RXCNT(3), - O => Inst_rxserie1_RC1_RXCNT_3_rt, - ADR1 => GND + CE => Inst_rxserie1_FIFO1_fifo0_N1, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N333, + O => Inst_rxserie1_FIFO1_fifo0_rd_ack, + SSET => rst_BUFGP, + SET => GSR, + RST => GND, + SRST => GND ); - Inst_rxserie1_CLOCK1_compteur_0_rt_61 : X_LUT2 + Inst_rxserie1_FIFO1_fifo0_BU34 : X_LUT4 generic map( - INIT => X"A" + INIT => X"bbbb" ) port map ( - ADR0 => Inst_rxserie1_CLOCK1_compteur(0), - O => Inst_rxserie1_CLOCK1_compteur_0_rt, - ADR1 => GND + ADR0 => Inst_rxserie1_flagreg(3), + ADR1 => Inst_rxserie1_FIFO1_rd_en, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N333 ); - Inst_decodisa_reg_select24 : X_LUT3 + Inst_rxserie1_FIFO1_fifo0_BU27 : X_SFF generic map( - INIT => X"04" + INIT => '1' ) port map ( - ADR0 => bus_adr_15_IBUF, - ADR1 => bus_adr_8_IBUF, - ADR2 => AEN_IBUF, - O => CHOICE45 + CE => Inst_rxserie1_FIFO1_fifo0_N1, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N284, + O => Inst_rxserie1_FIFO1_fifo0_rd_err, + SSET => rst_BUFGP, + SET => GSR, + RST => GND, + SRST => GND ); - Inst_decodisa_reg_select32 : X_LUT4 + Inst_rxserie1_FIFO1_fifo0_BU26 : X_LUT4 generic map( - INIT => X"0001" + INIT => X"7777" ) port map ( - ADR0 => bus_adr_9_IBUF, - ADR1 => bus_adr_10_IBUF, - ADR2 => bus_adr_11_IBUF, - ADR3 => N11025, - O => Inst_decodisa_reg_select + ADR0 => Inst_rxserie1_flagreg(3), + ADR1 => Inst_rxserie1_FIFO1_rd_en, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N284 ); - Inst_decodisa_reg_select32_SW0 : X_LUT4 + Inst_rxserie1_FIFO1_fifo0_BU19 : X_LUT4 generic map( - INIT => X"FFEF" + INIT => X"2222" ) port map ( - ADR0 => bus_adr_12_IBUF, - ADR1 => bus_adr_13_IBUF, - ADR2 => CHOICE45, - ADR3 => bus_adr_14_IBUF, - O => N11025 + ADR0 => Inst_rxserie1_FIFO1_rd_en, + ADR1 => Inst_rxserie1_flagreg(3), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N37 ); - bus_data_5_IOBUF_PULLUP : X_PU + Inst_rxserie1_FIFO1_fifo0_BU13 : X_LUT4 + generic map( + INIT => X"2222" + ) port map ( - O => bus_data_5_IOBUF + ADR0 => Inst_rxserie1_FIFO1_rd_en, + ADR1 => Inst_rxserie1_flagreg(3), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N2 ); - bus_data_0_IOBUF_PULLUP : X_PU + Inst_rxserie1_FIFO1_fifo0_BU7 : X_LUT4 + generic map( + INIT => X"eeee" + ) port map ( - O => bus_data_0_IOBUF + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => NLW_Inst_rxserie1_FIFO1_fifo0_BU7_O_UNCONNECTED ); - bus_data_7_IOBUF_PULLUP : X_PU + Inst_rxserie1_FIFO1_fifo0_GND : X_ZERO port map ( - O => bus_data_7_IOBUF + O => Inst_rxserie1_FIFO1_fifo0_N0 ); - bus_data_1_IOBUF_PULLUP : X_PU + Inst_rxserie1_FIFO1_fifo0_VCC : X_ONE port map ( - O => bus_data_1_IOBUF + O => Inst_rxserie1_FIFO1_fifo0_N1 ); - bus_data_6_IOBUF_PULLUP : X_PU + bus_data_5_IOBUF_OBUFT : X_TRI port map ( - O => bus_data_6_IOBUF + CTL => bus_data_5_IOBUF_OBUFT_GTS_AND, + I => bus_data_5_IOBUF, + O => bus_data(5) ); - bus_data_2_IOBUF_PULLUP : X_PU + bus_data_5_IOBUF_IBUF : X_BUF port map ( - O => bus_data_2_IOBUF + I => bus_data(5), + O => N15395 ); - bus_data_4_IOBUF_PULLUP : X_PU + bus_data_2_IOBUF_OBUFT : X_TRI port map ( - O => bus_data_4_IOBUF + CTL => bus_data_2_IOBUF_OBUFT_GTS_AND, + I => bus_data_2_IOBUF, + O => bus_data(2) ); - bus_data_3_IOBUF_PULLUP : X_PU + bus_data_2_IOBUF_IBUF : X_BUF port map ( - O => bus_data_3_IOBUF + I => bus_data(2), + O => N15389 ); - Inst_rxserie1_FIFO1_fifo0_BU232 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU232 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N37, + CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N47, - O => Inst_rxserie1_inter_fifo(7), - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N47, + O => Inst_txserie1_inter_data(7), + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU230 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU230 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N37, + CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N48, - O => Inst_rxserie1_inter_fifo(6), - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N48, + O => Inst_txserie1_inter_data(6), + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU228 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU228 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N37, + CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N49, - O => Inst_rxserie1_inter_fifo(5), - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N49, + O => Inst_txserie1_inter_data(5), + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU226 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU226 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N37, + CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N50, - O => Inst_rxserie1_inter_fifo(4), - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N50, + O => Inst_txserie1_inter_data(4), + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU224 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU224 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N37, + CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N51, - O => Inst_rxserie1_inter_fifo(3), - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N51, + O => Inst_txserie1_inter_data(3), + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU222 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU222 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N37, + CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N52, - O => Inst_rxserie1_inter_fifo(2), - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N52, + O => Inst_txserie1_inter_data(2), + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU220 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU220 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N37, + CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N53, - O => Inst_rxserie1_inter_fifo(1), - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N53, + O => Inst_txserie1_inter_data(1), + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU218 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU218 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N37, + CE => Inst_txserie1_FIFO1_fifo0_N37, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N54, - O => Inst_rxserie1_inter_fifo(0), - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N54, + O => Inst_txserie1_inter_data(0), + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU214 : X_SRL16E + Inst_txserie1_FIFO1_fifo0_BU214 : X_SRL16E generic map( INIT => X"0000" ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N38, - D => Inst_rxserie1_RC1_RHR(7), - Q => Inst_rxserie1_FIFO1_fifo0_N47, + CE => Inst_txserie1_FIFO1_fifo0_N38, + D => N15399, + Q => Inst_txserie1_FIFO1_fifo0_N47, CLK => clk_speed_BUFGP, - A0 => Inst_rxserie1_FIFO1_fifo0_N7, - A1 => Inst_rxserie1_FIFO1_fifo0_N6, - A2 => Inst_rxserie1_FIFO1_fifo0_N5, - A3 => Inst_rxserie1_FIFO1_fifo0_N4 + A0 => Inst_txserie1_FIFO1_fifo0_N7, + A1 => Inst_txserie1_FIFO1_fifo0_N6, + A2 => Inst_txserie1_FIFO1_fifo0_N5, + A3 => Inst_txserie1_FIFO1_fifo0_N4 ); - Inst_rxserie1_FIFO1_fifo0_BU213 : X_SRL16E + Inst_txserie1_FIFO1_fifo0_BU213 : X_SRL16E generic map( INIT => X"0000" ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N38, - D => Inst_rxserie1_RC1_RHR(6), - Q => Inst_rxserie1_FIFO1_fifo0_N48, + CE => Inst_txserie1_FIFO1_fifo0_N38, + D => N15397, + Q => Inst_txserie1_FIFO1_fifo0_N48, CLK => clk_speed_BUFGP, - A0 => Inst_rxserie1_FIFO1_fifo0_N7, - A1 => Inst_rxserie1_FIFO1_fifo0_N6, - A2 => Inst_rxserie1_FIFO1_fifo0_N5, - A3 => Inst_rxserie1_FIFO1_fifo0_N4 + A0 => Inst_txserie1_FIFO1_fifo0_N7, + A1 => Inst_txserie1_FIFO1_fifo0_N6, + A2 => Inst_txserie1_FIFO1_fifo0_N5, + A3 => Inst_txserie1_FIFO1_fifo0_N4 ); - Inst_rxserie1_FIFO1_fifo0_BU212 : X_SRL16E + Inst_txserie1_FIFO1_fifo0_BU212 : X_SRL16E generic map( INIT => X"0000" ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N38, - D => Inst_rxserie1_RC1_RHR(5), - Q => Inst_rxserie1_FIFO1_fifo0_N49, + CE => Inst_txserie1_FIFO1_fifo0_N38, + D => N15395, + Q => Inst_txserie1_FIFO1_fifo0_N49, CLK => clk_speed_BUFGP, - A0 => Inst_rxserie1_FIFO1_fifo0_N7, - A1 => Inst_rxserie1_FIFO1_fifo0_N6, - A2 => Inst_rxserie1_FIFO1_fifo0_N5, - A3 => Inst_rxserie1_FIFO1_fifo0_N4 + A0 => Inst_txserie1_FIFO1_fifo0_N7, + A1 => Inst_txserie1_FIFO1_fifo0_N6, + A2 => Inst_txserie1_FIFO1_fifo0_N5, + A3 => Inst_txserie1_FIFO1_fifo0_N4 ); - Inst_rxserie1_FIFO1_fifo0_BU211 : X_SRL16E + Inst_txserie1_FIFO1_fifo0_BU211 : X_SRL16E generic map( INIT => X"0000" ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N38, - D => Inst_rxserie1_RC1_RHR(4), - Q => Inst_rxserie1_FIFO1_fifo0_N50, + CE => Inst_txserie1_FIFO1_fifo0_N38, + D => N15393, + Q => Inst_txserie1_FIFO1_fifo0_N50, CLK => clk_speed_BUFGP, - A0 => Inst_rxserie1_FIFO1_fifo0_N7, - A1 => Inst_rxserie1_FIFO1_fifo0_N6, - A2 => Inst_rxserie1_FIFO1_fifo0_N5, - A3 => Inst_rxserie1_FIFO1_fifo0_N4 + A0 => Inst_txserie1_FIFO1_fifo0_N7, + A1 => Inst_txserie1_FIFO1_fifo0_N6, + A2 => Inst_txserie1_FIFO1_fifo0_N5, + A3 => Inst_txserie1_FIFO1_fifo0_N4 ); - Inst_rxserie1_FIFO1_fifo0_BU210 : X_SRL16E + Inst_txserie1_FIFO1_fifo0_BU210 : X_SRL16E generic map( INIT => X"0000" ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N38, - D => Inst_rxserie1_RC1_RHR(3), - Q => Inst_rxserie1_FIFO1_fifo0_N51, + CE => Inst_txserie1_FIFO1_fifo0_N38, + D => N15391, + Q => Inst_txserie1_FIFO1_fifo0_N51, CLK => clk_speed_BUFGP, - A0 => Inst_rxserie1_FIFO1_fifo0_N7, - A1 => Inst_rxserie1_FIFO1_fifo0_N6, - A2 => Inst_rxserie1_FIFO1_fifo0_N5, - A3 => Inst_rxserie1_FIFO1_fifo0_N4 + A0 => Inst_txserie1_FIFO1_fifo0_N7, + A1 => Inst_txserie1_FIFO1_fifo0_N6, + A2 => Inst_txserie1_FIFO1_fifo0_N5, + A3 => Inst_txserie1_FIFO1_fifo0_N4 ); - Inst_rxserie1_FIFO1_fifo0_BU209 : X_SRL16E + Inst_txserie1_FIFO1_fifo0_BU209 : X_SRL16E generic map( INIT => X"0000" ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N38, - D => Inst_rxserie1_RC1_RHR(2), - Q => Inst_rxserie1_FIFO1_fifo0_N52, + CE => Inst_txserie1_FIFO1_fifo0_N38, + D => N15389, + Q => Inst_txserie1_FIFO1_fifo0_N52, CLK => clk_speed_BUFGP, - A0 => Inst_rxserie1_FIFO1_fifo0_N7, - A1 => Inst_rxserie1_FIFO1_fifo0_N6, - A2 => Inst_rxserie1_FIFO1_fifo0_N5, - A3 => Inst_rxserie1_FIFO1_fifo0_N4 + A0 => Inst_txserie1_FIFO1_fifo0_N7, + A1 => Inst_txserie1_FIFO1_fifo0_N6, + A2 => Inst_txserie1_FIFO1_fifo0_N5, + A3 => Inst_txserie1_FIFO1_fifo0_N4 ); - Inst_rxserie1_FIFO1_fifo0_BU208 : X_SRL16E + Inst_txserie1_FIFO1_fifo0_BU208 : X_SRL16E generic map( INIT => X"0000" ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N38, - D => Inst_rxserie1_RC1_RHR(1), - Q => Inst_rxserie1_FIFO1_fifo0_N53, + CE => Inst_txserie1_FIFO1_fifo0_N38, + D => N15387, + Q => Inst_txserie1_FIFO1_fifo0_N53, CLK => clk_speed_BUFGP, - A0 => Inst_rxserie1_FIFO1_fifo0_N7, - A1 => Inst_rxserie1_FIFO1_fifo0_N6, - A2 => Inst_rxserie1_FIFO1_fifo0_N5, - A3 => Inst_rxserie1_FIFO1_fifo0_N4 + A0 => Inst_txserie1_FIFO1_fifo0_N7, + A1 => Inst_txserie1_FIFO1_fifo0_N6, + A2 => Inst_txserie1_FIFO1_fifo0_N5, + A3 => Inst_txserie1_FIFO1_fifo0_N4 ); - Inst_rxserie1_FIFO1_fifo0_BU207 : X_SRL16E + Inst_txserie1_FIFO1_fifo0_BU207 : X_SRL16E generic map( INIT => X"0000" ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N38, - D => Inst_rxserie1_RC1_RHR(0), - Q => Inst_rxserie1_FIFO1_fifo0_N54, + CE => Inst_txserie1_FIFO1_fifo0_N38, + D => N15385, + Q => Inst_txserie1_FIFO1_fifo0_N54, CLK => clk_speed_BUFGP, - A0 => Inst_rxserie1_FIFO1_fifo0_N7, - A1 => Inst_rxserie1_FIFO1_fifo0_N6, - A2 => Inst_rxserie1_FIFO1_fifo0_N5, - A3 => Inst_rxserie1_FIFO1_fifo0_N4 + A0 => Inst_txserie1_FIFO1_fifo0_N7, + A1 => Inst_txserie1_FIFO1_fifo0_N6, + A2 => Inst_txserie1_FIFO1_fifo0_N5, + A3 => Inst_txserie1_FIFO1_fifo0_N4 ); - Inst_rxserie1_FIFO1_fifo0_BU204 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU204 : X_SFF generic map( INIT => '1' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N1, + CE => Inst_txserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N1271, - O => Inst_rxserie1_flagreg(3), - SSET => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N1271, + O => Inst_txserie1_flagreg(3), + SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); - Inst_rxserie1_FIFO1_fifo0_BU203 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU203 : X_LUT4 generic map( INIT => X"eeee" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N1143, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N1142, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N1271 + ADR0 => Inst_txserie1_FIFO1_fifo0_N1143, + ADR1 => Inst_txserie1_FIFO1_fifo0_N1142, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N1271 ); - Inst_rxserie1_FIFO1_fifo0_BU196 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU196 : X_LUT4 generic map( INIT => X"2222" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N73, - ADR1 => Inst_rxserie1_FIFO1_wr_en, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N1143 + ADR0 => Inst_txserie1_FIFO1_fifo0_N73, + ADR1 => Inst_txserie1_FIFO1_wr_en, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N1143 ); - Inst_rxserie1_FIFO1_fifo0_BU190 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU190 : X_LUT4 generic map( INIT => X"4040" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_wr_en, - ADR1 => Inst_rxserie1_FIFO1_state_read_FFd2, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N74, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N1142 + ADR0 => Inst_txserie1_FIFO1_wr_en, + ADR1 => Inst_txserie1_FIFO1_rd_en, + ADR2 => Inst_txserie1_FIFO1_fifo0_N74, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N1142 ); - Inst_rxserie1_FIFO1_fifo0_BU183 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU183 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N1110, - IA => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N74, - SEL => Inst_rxserie1_FIFO1_fifo0_N1113 + IB => Inst_txserie1_FIFO1_fifo0_N1110, + IA => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N74, + SEL => Inst_txserie1_FIFO1_fifo0_N1113 ); - Inst_rxserie1_FIFO1_fifo0_BU182 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU182 : X_LUT4 generic map( INIT => X"9999" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR1 => Inst_rxserie1_flagreg(2), - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N1113 + ADR0 => Inst_txserie1_FIFO1_fifo0_N0, + ADR1 => Inst_txserie1_flagreg(2), + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N1113 ); - Inst_rxserie1_FIFO1_fifo0_BU180 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU180 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N1104, - IA => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N1110, - SEL => Inst_rxserie1_FIFO1_fifo0_N1107 + IB => Inst_txserie1_FIFO1_fifo0_N1104, + IA => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N1110, + SEL => Inst_txserie1_FIFO1_fifo0_N1107 ); - Inst_rxserie1_FIFO1_fifo0_BU179 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU179 : X_LUT4 generic map( INIT => X"9009" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N17, - O => Inst_rxserie1_FIFO1_fifo0_N1107 + ADR0 => Inst_txserie1_FIFO1_fifo0_N0, + ADR1 => Inst_txserie1_FIFO1_fifo0_N18, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N17, + O => Inst_txserie1_FIFO1_fifo0_N1107 ); - Inst_rxserie1_FIFO1_fifo0_BU177 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU177 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N1, - IA => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N1104, - SEL => Inst_rxserie1_FIFO1_fifo0_N1101 + IB => Inst_txserie1_FIFO1_fifo0_N1, + IA => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N1104, + SEL => Inst_txserie1_FIFO1_fifo0_N1101 ); - Inst_rxserie1_FIFO1_fifo0_BU176 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU176 : X_LUT4 generic map( INIT => X"9009" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N1, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N19, - O => Inst_rxserie1_FIFO1_fifo0_N1101 + ADR0 => Inst_txserie1_FIFO1_fifo0_N1, + ADR1 => Inst_txserie1_FIFO1_fifo0_N20, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N19, + O => Inst_txserie1_FIFO1_fifo0_N1101 ); - Inst_rxserie1_FIFO1_fifo0_BU172 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU172 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N1037, - IA => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N73, - SEL => Inst_rxserie1_FIFO1_fifo0_N1040 + IB => Inst_txserie1_FIFO1_fifo0_N1037, + IA => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N73, + SEL => Inst_txserie1_FIFO1_fifo0_N1040 ); - Inst_rxserie1_FIFO1_fifo0_BU171 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU171 : X_LUT4 generic map( INIT => X"9999" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR1 => Inst_rxserie1_flagreg(2), - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N1040 + ADR0 => Inst_txserie1_FIFO1_fifo0_N0, + ADR1 => Inst_txserie1_flagreg(2), + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N1040 ); - Inst_rxserie1_FIFO1_fifo0_BU169 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU169 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N1031, - IA => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N1037, - SEL => Inst_rxserie1_FIFO1_fifo0_N1034 + IB => Inst_txserie1_FIFO1_fifo0_N1031, + IA => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N1037, + SEL => Inst_txserie1_FIFO1_fifo0_N1034 ); - Inst_rxserie1_FIFO1_fifo0_BU168 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU168 : X_LUT4 generic map( INIT => X"9009" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N17, - O => Inst_rxserie1_FIFO1_fifo0_N1034 + ADR0 => Inst_txserie1_FIFO1_fifo0_N0, + ADR1 => Inst_txserie1_FIFO1_fifo0_N18, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N17, + O => Inst_txserie1_FIFO1_fifo0_N1034 ); - Inst_rxserie1_FIFO1_fifo0_BU166 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU166 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N1, - IA => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N1031, - SEL => Inst_rxserie1_FIFO1_fifo0_N1028 + IB => Inst_txserie1_FIFO1_fifo0_N1, + IA => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N1031, + SEL => Inst_txserie1_FIFO1_fifo0_N1028 ); - Inst_rxserie1_FIFO1_fifo0_BU165 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU165 : X_LUT4 generic map( INIT => X"9009" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N19, - O => Inst_rxserie1_FIFO1_fifo0_N1028 + ADR0 => Inst_txserie1_FIFO1_fifo0_N0, + ADR1 => Inst_txserie1_FIFO1_fifo0_N20, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N19, + O => Inst_txserie1_FIFO1_fifo0_N1028 ); - Inst_rxserie1_FIFO1_fifo0_BU161 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU161 : X_LUT4 generic map( INIT => X"eeee" ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_flagreg(2), - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => NLW_Inst_rxserie1_FIFO1_fifo0_BU161_O_UNCONNECTED + ADR0 => Inst_txserie1_flagreg(2), + ADR1 => Inst_txserie1_flagreg(2), + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => NLW_Inst_txserie1_FIFO1_fifo0_BU161_O_UNCONNECTED ); - Inst_rxserie1_FIFO1_fifo0_BU155 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU155 : X_LUT4 generic map( INIT => X"eeee" ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_FIFO1_fifo0_N17, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_flagreg(1) + ADR0 => Inst_txserie1_flagreg(2), + ADR1 => Inst_txserie1_FIFO1_fifo0_N17, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_fifoLevel(1) ); - Inst_rxserie1_FIFO1_fifo0_BU149 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU149 : X_LUT4 generic map( INIT => X"eeee" ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_flagreg(0) + ADR0 => Inst_txserie1_flagreg(2), + ADR1 => Inst_txserie1_FIFO1_fifo0_N18, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_fifoLevel(0) ); - Inst_rxserie1_FIFO1_fifo0_BU143 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU143 : X_LUT4 generic map( INIT => X"eeee" ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_FIFO1_fifo0_N19, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => NLW_Inst_rxserie1_FIFO1_fifo0_BU143_O_UNCONNECTED + ADR0 => Inst_txserie1_flagreg(2), + ADR1 => Inst_txserie1_FIFO1_fifo0_N19, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => NLW_Inst_txserie1_FIFO1_fifo0_BU143_O_UNCONNECTED ); - Inst_rxserie1_FIFO1_fifo0_BU137 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU137 : X_LUT4 generic map( INIT => X"eeee" ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => NLW_Inst_rxserie1_FIFO1_fifo0_BU137_O_UNCONNECTED + ADR0 => Inst_txserie1_flagreg(2), + ADR1 => Inst_txserie1_FIFO1_fifo0_N20, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => NLW_Inst_txserie1_FIFO1_fifo0_BU137_O_UNCONNECTED ); - Inst_rxserie1_FIFO1_fifo0_BU131 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU131 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N33, + CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N716, - O => Inst_rxserie1_flagreg(2), - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N716, + O => Inst_txserie1_flagreg(2), + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU129 : X_XOR2 + Inst_txserie1_FIFO1_fifo0_BU129 : X_XOR2 port map ( - I0 => Inst_rxserie1_FIFO1_fifo0_N735, - I1 => Inst_rxserie1_FIFO1_fifo0_N738, - O => Inst_rxserie1_FIFO1_fifo0_N716 + I0 => Inst_txserie1_FIFO1_fifo0_N735, + I1 => Inst_txserie1_FIFO1_fifo0_N738, + O => Inst_txserie1_FIFO1_fifo0_N716 ); - Inst_rxserie1_FIFO1_fifo0_BU128 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU128 : X_LUT4 generic map( INIT => X"9999" ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N738 + ADR0 => Inst_txserie1_flagreg(2), + ADR1 => Inst_txserie1_FIFO1_fifo0_N3, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N738 ); - Inst_rxserie1_FIFO1_fifo0_BU126 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU126 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N33, + CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N715, - O => Inst_rxserie1_FIFO1_fifo0_N17, - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N715, + O => Inst_txserie1_FIFO1_fifo0_N17, + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU124 : X_XOR2 + Inst_txserie1_FIFO1_fifo0_BU124 : X_XOR2 port map ( - I0 => Inst_rxserie1_FIFO1_fifo0_N730, - I1 => Inst_rxserie1_FIFO1_fifo0_N733, - O => Inst_rxserie1_FIFO1_fifo0_N715 + I0 => Inst_txserie1_FIFO1_fifo0_N730, + I1 => Inst_txserie1_FIFO1_fifo0_N733, + O => Inst_txserie1_FIFO1_fifo0_N715 ); - Inst_rxserie1_FIFO1_fifo0_BU123 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU123 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N730, - IA => Inst_rxserie1_FIFO1_fifo0_N17, - O => Inst_rxserie1_FIFO1_fifo0_N735, - SEL => Inst_rxserie1_FIFO1_fifo0_N733 + IB => Inst_txserie1_FIFO1_fifo0_N730, + IA => Inst_txserie1_FIFO1_fifo0_N17, + O => Inst_txserie1_FIFO1_fifo0_N735, + SEL => Inst_txserie1_FIFO1_fifo0_N733 ); - Inst_rxserie1_FIFO1_fifo0_BU122 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU122 : X_LUT4 generic map( INIT => X"9999" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N17, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N733 + ADR0 => Inst_txserie1_FIFO1_fifo0_N17, + ADR1 => Inst_txserie1_FIFO1_fifo0_N3, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N733 ); - Inst_rxserie1_FIFO1_fifo0_BU120 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU120 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N33, + CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N714, - O => Inst_rxserie1_FIFO1_fifo0_N18, - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N714, + O => Inst_txserie1_FIFO1_fifo0_N18, + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU118 : X_XOR2 + Inst_txserie1_FIFO1_fifo0_BU118 : X_XOR2 port map ( - I0 => Inst_rxserie1_FIFO1_fifo0_N725, - I1 => Inst_rxserie1_FIFO1_fifo0_N728, - O => Inst_rxserie1_FIFO1_fifo0_N714 + I0 => Inst_txserie1_FIFO1_fifo0_N725, + I1 => Inst_txserie1_FIFO1_fifo0_N728, + O => Inst_txserie1_FIFO1_fifo0_N714 ); - Inst_rxserie1_FIFO1_fifo0_BU117 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU117 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N725, - IA => Inst_rxserie1_FIFO1_fifo0_N18, - O => Inst_rxserie1_FIFO1_fifo0_N730, - SEL => Inst_rxserie1_FIFO1_fifo0_N728 + IB => Inst_txserie1_FIFO1_fifo0_N725, + IA => Inst_txserie1_FIFO1_fifo0_N18, + O => Inst_txserie1_FIFO1_fifo0_N730, + SEL => Inst_txserie1_FIFO1_fifo0_N728 ); - Inst_rxserie1_FIFO1_fifo0_BU116 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU116 : X_LUT4 generic map( INIT => X"9999" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N18, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N728 + ADR0 => Inst_txserie1_FIFO1_fifo0_N18, + ADR1 => Inst_txserie1_FIFO1_fifo0_N3, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N728 ); - Inst_rxserie1_FIFO1_fifo0_BU114 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU114 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N33, + CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N713, - O => Inst_rxserie1_FIFO1_fifo0_N19, - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N713, + O => Inst_txserie1_FIFO1_fifo0_N19, + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU112 : X_XOR2 + Inst_txserie1_FIFO1_fifo0_BU112 : X_XOR2 port map ( - I0 => Inst_rxserie1_FIFO1_fifo0_N720, - I1 => Inst_rxserie1_FIFO1_fifo0_N723, - O => Inst_rxserie1_FIFO1_fifo0_N713 + I0 => Inst_txserie1_FIFO1_fifo0_N720, + I1 => Inst_txserie1_FIFO1_fifo0_N723, + O => Inst_txserie1_FIFO1_fifo0_N713 ); - Inst_rxserie1_FIFO1_fifo0_BU111 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU111 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N720, - IA => Inst_rxserie1_FIFO1_fifo0_N19, - O => Inst_rxserie1_FIFO1_fifo0_N725, - SEL => Inst_rxserie1_FIFO1_fifo0_N723 + IB => Inst_txserie1_FIFO1_fifo0_N720, + IA => Inst_txserie1_FIFO1_fifo0_N19, + O => Inst_txserie1_FIFO1_fifo0_N725, + SEL => Inst_txserie1_FIFO1_fifo0_N723 ); - Inst_rxserie1_FIFO1_fifo0_BU110 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU110 : X_LUT4 generic map( INIT => X"9999" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N19, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N723 + ADR0 => Inst_txserie1_FIFO1_fifo0_N19, + ADR1 => Inst_txserie1_FIFO1_fifo0_N3, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N723 ); - Inst_rxserie1_FIFO1_fifo0_BU108 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU108 : X_SFF generic map( INIT => '0' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N33, + CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N712, - O => Inst_rxserie1_FIFO1_fifo0_N20, - SRST => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N712, + O => Inst_txserie1_FIFO1_fifo0_N20, + SRST => Inst_txserie1_fifopurge, SET => GND, RST => GSR, SSET => GND ); - Inst_rxserie1_FIFO1_fifo0_BU106 : X_XOR2 + Inst_txserie1_FIFO1_fifo0_BU106 : X_XOR2 port map ( - I0 => Inst_rxserie1_FIFO1_fifo0_N718, - I1 => Inst_rxserie1_FIFO1_fifo0_N717, - O => Inst_rxserie1_FIFO1_fifo0_N712 + I0 => Inst_txserie1_FIFO1_fifo0_N718, + I1 => Inst_txserie1_FIFO1_fifo0_N717, + O => Inst_txserie1_FIFO1_fifo0_N712 ); - Inst_rxserie1_FIFO1_fifo0_BU105 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU105 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N718, - IA => Inst_rxserie1_FIFO1_fifo0_N20, - O => Inst_rxserie1_FIFO1_fifo0_N720, - SEL => Inst_rxserie1_FIFO1_fifo0_N717 + IB => Inst_txserie1_FIFO1_fifo0_N718, + IA => Inst_txserie1_FIFO1_fifo0_N20, + O => Inst_txserie1_FIFO1_fifo0_N720, + SEL => Inst_txserie1_FIFO1_fifo0_N717 ); - Inst_rxserie1_FIFO1_fifo0_BU104 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU104 : X_LUT4 generic map( INIT => X"6666" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N20, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N717 + ADR0 => Inst_txserie1_FIFO1_fifo0_N20, + ADR1 => Inst_txserie1_FIFO1_fifo0_N3, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N717 ); - Inst_rxserie1_FIFO1_fifo0_BU102 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU102 : X_LUT4 generic map( INIT => X"5555" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N718 + ADR0 => Inst_txserie1_FIFO1_fifo0_N3, + ADR1 => Inst_txserie1_FIFO1_fifo0_N0, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N718 ); - Inst_rxserie1_FIFO1_fifo0_BU97 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU97 : X_SFF generic map( INIT => '1' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N33, + CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N592, - O => Inst_rxserie1_FIFO1_fifo0_N4, - SSET => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N592, + O => Inst_txserie1_FIFO1_fifo0_N4, + SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); - Inst_rxserie1_FIFO1_fifo0_BU95 : X_XOR2 + Inst_txserie1_FIFO1_fifo0_BU95 : X_XOR2 port map ( - I0 => Inst_rxserie1_FIFO1_fifo0_N606, - I1 => Inst_rxserie1_FIFO1_fifo0_N609, - O => Inst_rxserie1_FIFO1_fifo0_N592 + I0 => Inst_txserie1_FIFO1_fifo0_N606, + I1 => Inst_txserie1_FIFO1_fifo0_N609, + O => Inst_txserie1_FIFO1_fifo0_N592 ); - Inst_rxserie1_FIFO1_fifo0_BU94 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU94 : X_LUT4 generic map( INIT => X"9999" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N4, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N609 + ADR0 => Inst_txserie1_FIFO1_fifo0_N4, + ADR1 => Inst_txserie1_FIFO1_fifo0_N3, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N609 ); - Inst_rxserie1_FIFO1_fifo0_BU92 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU92 : X_SFF generic map( INIT => '1' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N33, + CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N591, - O => Inst_rxserie1_FIFO1_fifo0_N5, - SSET => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N591, + O => Inst_txserie1_FIFO1_fifo0_N5, + SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); - Inst_rxserie1_FIFO1_fifo0_BU90 : X_XOR2 + Inst_txserie1_FIFO1_fifo0_BU90 : X_XOR2 port map ( - I0 => Inst_rxserie1_FIFO1_fifo0_N601, - I1 => Inst_rxserie1_FIFO1_fifo0_N604, - O => Inst_rxserie1_FIFO1_fifo0_N591 + I0 => Inst_txserie1_FIFO1_fifo0_N601, + I1 => Inst_txserie1_FIFO1_fifo0_N604, + O => Inst_txserie1_FIFO1_fifo0_N591 ); - Inst_rxserie1_FIFO1_fifo0_BU89 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU89 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N601, - IA => Inst_rxserie1_FIFO1_fifo0_N5, - O => Inst_rxserie1_FIFO1_fifo0_N606, - SEL => Inst_rxserie1_FIFO1_fifo0_N604 + IB => Inst_txserie1_FIFO1_fifo0_N601, + IA => Inst_txserie1_FIFO1_fifo0_N5, + O => Inst_txserie1_FIFO1_fifo0_N606, + SEL => Inst_txserie1_FIFO1_fifo0_N604 ); - Inst_rxserie1_FIFO1_fifo0_BU88 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU88 : X_LUT4 generic map( INIT => X"9999" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N5, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N604 + ADR0 => Inst_txserie1_FIFO1_fifo0_N5, + ADR1 => Inst_txserie1_FIFO1_fifo0_N3, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N604 ); - Inst_rxserie1_FIFO1_fifo0_BU86 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU86 : X_SFF generic map( INIT => '1' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N33, + CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N590, - O => Inst_rxserie1_FIFO1_fifo0_N6, - SSET => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N590, + O => Inst_txserie1_FIFO1_fifo0_N6, + SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); - Inst_rxserie1_FIFO1_fifo0_BU84 : X_XOR2 + Inst_txserie1_FIFO1_fifo0_BU84 : X_XOR2 port map ( - I0 => Inst_rxserie1_FIFO1_fifo0_N596, - I1 => Inst_rxserie1_FIFO1_fifo0_N599, - O => Inst_rxserie1_FIFO1_fifo0_N590 + I0 => Inst_txserie1_FIFO1_fifo0_N596, + I1 => Inst_txserie1_FIFO1_fifo0_N599, + O => Inst_txserie1_FIFO1_fifo0_N590 ); - Inst_rxserie1_FIFO1_fifo0_BU83 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU83 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N596, - IA => Inst_rxserie1_FIFO1_fifo0_N6, - O => Inst_rxserie1_FIFO1_fifo0_N601, - SEL => Inst_rxserie1_FIFO1_fifo0_N599 + IB => Inst_txserie1_FIFO1_fifo0_N596, + IA => Inst_txserie1_FIFO1_fifo0_N6, + O => Inst_txserie1_FIFO1_fifo0_N601, + SEL => Inst_txserie1_FIFO1_fifo0_N599 ); - Inst_rxserie1_FIFO1_fifo0_BU82 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU82 : X_LUT4 generic map( INIT => X"9999" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N6, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N599 + ADR0 => Inst_txserie1_FIFO1_fifo0_N6, + ADR1 => Inst_txserie1_FIFO1_fifo0_N3, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N599 ); - Inst_rxserie1_FIFO1_fifo0_BU80 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU80 : X_SFF generic map( INIT => '1' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N33, + CE => Inst_txserie1_FIFO1_fifo0_N33, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N589, - O => Inst_rxserie1_FIFO1_fifo0_N7, - SSET => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N589, + O => Inst_txserie1_FIFO1_fifo0_N7, + SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); - Inst_rxserie1_FIFO1_fifo0_BU78 : X_XOR2 + Inst_txserie1_FIFO1_fifo0_BU78 : X_XOR2 port map ( - I0 => Inst_rxserie1_FIFO1_fifo0_N594, - I1 => Inst_rxserie1_FIFO1_fifo0_N593, - O => Inst_rxserie1_FIFO1_fifo0_N589 + I0 => Inst_txserie1_FIFO1_fifo0_N594, + I1 => Inst_txserie1_FIFO1_fifo0_N593, + O => Inst_txserie1_FIFO1_fifo0_N589 ); - Inst_rxserie1_FIFO1_fifo0_BU77 : X_MUX2 + Inst_txserie1_FIFO1_fifo0_BU77 : X_MUX2 port map ( - IB => Inst_rxserie1_FIFO1_fifo0_N594, - IA => Inst_rxserie1_FIFO1_fifo0_N7, - O => Inst_rxserie1_FIFO1_fifo0_N596, - SEL => Inst_rxserie1_FIFO1_fifo0_N593 + IB => Inst_txserie1_FIFO1_fifo0_N594, + IA => Inst_txserie1_FIFO1_fifo0_N7, + O => Inst_txserie1_FIFO1_fifo0_N596, + SEL => Inst_txserie1_FIFO1_fifo0_N593 ); - Inst_rxserie1_FIFO1_fifo0_BU76 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU76 : X_LUT4 generic map( INIT => X"6666" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N7, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N593 + ADR0 => Inst_txserie1_FIFO1_fifo0_N7, + ADR1 => Inst_txserie1_FIFO1_fifo0_N3, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N593 ); - Inst_rxserie1_FIFO1_fifo0_BU74 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU74 : X_LUT4 generic map( INIT => X"5555" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N594 + ADR0 => Inst_txserie1_FIFO1_fifo0_N3, + ADR1 => Inst_txserie1_FIFO1_fifo0_N0, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N594 ); - Inst_rxserie1_FIFO1_fifo0_BU69 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU69 : X_LUT4 generic map( INIT => X"6666" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_fifo0_N2, - ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N33 + ADR0 => Inst_txserie1_FIFO1_fifo0_N2, + ADR1 => Inst_txserie1_FIFO1_fifo0_N3, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N33 ); - Inst_rxserie1_FIFO1_fifo0_BU63 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU63 : X_SFF generic map( INIT => '1' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N1, + CE => Inst_txserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N505, - O => Inst_rxserie1_FIFO1_fifo0_wr_ack, - SSET => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N505, + O => Inst_txserie1_FIFO1_fifo0_wr_ack, + SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); - Inst_rxserie1_FIFO1_fifo0_BU62 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU62 : X_LUT4 generic map( INIT => X"bbbb" ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_FIFO1_wr_en, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N505 + ADR0 => Inst_txserie1_flagreg(2), + ADR1 => Inst_txserie1_FIFO1_wr_en, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N505 ); - Inst_rxserie1_FIFO1_fifo0_BU55 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU55 : X_SFF generic map( INIT => '1' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N1, + CE => Inst_txserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N456, - O => Inst_rxserie1_FIFO1_fifo0_wr_err, - SSET => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N456, + O => Inst_txserie1_FIFO1_fifo0_wr_err, + SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); - Inst_rxserie1_FIFO1_fifo0_BU54 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU54 : X_LUT4 generic map( INIT => X"7777" ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_FIFO1_wr_en, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N456 + ADR0 => Inst_txserie1_flagreg(2), + ADR1 => Inst_txserie1_FIFO1_wr_en, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N456 ); - Inst_rxserie1_FIFO1_fifo0_BU47 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU47 : X_LUT4 generic map( INIT => X"2222" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_wr_en, - ADR1 => Inst_rxserie1_flagreg(2), - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N38 + ADR0 => Inst_txserie1_FIFO1_wr_en, + ADR1 => Inst_txserie1_flagreg(2), + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N38 ); - Inst_rxserie1_FIFO1_fifo0_BU41 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU41 : X_LUT4 generic map( INIT => X"2222" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_wr_en, - ADR1 => Inst_rxserie1_flagreg(2), - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N3 + ADR0 => Inst_txserie1_FIFO1_wr_en, + ADR1 => Inst_txserie1_flagreg(2), + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N3 ); - Inst_rxserie1_FIFO1_fifo0_BU35 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU35 : X_SFF generic map( INIT => '1' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N1, + CE => Inst_txserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N333, - O => Inst_rxserie1_FIFO1_fifo0_rd_ack, - SSET => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N333, + O => Inst_txserie1_FIFO1_fifo0_rd_ack, + SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); - Inst_rxserie1_FIFO1_fifo0_BU34 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU34 : X_LUT4 generic map( INIT => X"bbbb" ) port map ( - ADR0 => Inst_rxserie1_flagreg(3), - ADR1 => Inst_rxserie1_FIFO1_state_read_FFd2, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N333 + ADR0 => Inst_txserie1_flagreg(3), + ADR1 => Inst_txserie1_FIFO1_rd_en, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N333 ); - Inst_rxserie1_FIFO1_fifo0_BU27 : X_SFF + Inst_txserie1_FIFO1_fifo0_BU27 : X_SFF generic map( INIT => '1' ) port map ( - CE => Inst_rxserie1_FIFO1_fifo0_N1, + CE => Inst_txserie1_FIFO1_fifo0_N1, CLK => clk_speed_BUFGP, - I => Inst_rxserie1_FIFO1_fifo0_N284, - O => Inst_rxserie1_FIFO1_fifo0_rd_err, - SSET => rst_IBUF, + I => Inst_txserie1_FIFO1_fifo0_N284, + O => Inst_txserie1_FIFO1_fifo0_rd_err, + SSET => Inst_txserie1_fifopurge, SET => GSR, RST => GND, SRST => GND ); - Inst_rxserie1_FIFO1_fifo0_BU26 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU26 : X_LUT4 generic map( INIT => X"7777" ) port map ( - ADR0 => Inst_rxserie1_flagreg(3), - ADR1 => Inst_rxserie1_FIFO1_state_read_FFd2, - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N284 + ADR0 => Inst_txserie1_flagreg(3), + ADR1 => Inst_txserie1_FIFO1_rd_en, + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N284 ); - Inst_rxserie1_FIFO1_fifo0_BU19 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU19 : X_LUT4 generic map( INIT => X"2222" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_state_read_FFd2, - ADR1 => Inst_rxserie1_flagreg(3), - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N37 + ADR0 => Inst_txserie1_FIFO1_rd_en, + ADR1 => Inst_txserie1_flagreg(3), + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N37 ); - Inst_rxserie1_FIFO1_fifo0_BU13 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU13 : X_LUT4 generic map( INIT => X"2222" ) port map ( - ADR0 => Inst_rxserie1_FIFO1_state_read_FFd2, - ADR1 => Inst_rxserie1_flagreg(3), - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => Inst_rxserie1_FIFO1_fifo0_N2 + ADR0 => Inst_txserie1_FIFO1_rd_en, + ADR1 => Inst_txserie1_flagreg(3), + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => Inst_txserie1_FIFO1_fifo0_N2 ); - Inst_rxserie1_FIFO1_fifo0_BU7 : X_LUT4 + Inst_txserie1_FIFO1_fifo0_BU7 : X_LUT4 generic map( INIT => X"eeee" ) port map ( - ADR0 => Inst_rxserie1_flagreg(2), - ADR1 => Inst_rxserie1_flagreg(2), - ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, - ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, - O => NLW_Inst_rxserie1_FIFO1_fifo0_BU7_O_UNCONNECTED + ADR0 => Inst_txserie1_flagreg(2), + ADR1 => Inst_txserie1_flagreg(2), + ADR2 => Inst_txserie1_FIFO1_fifo0_N0, + ADR3 => Inst_txserie1_FIFO1_fifo0_N0, + O => NLW_Inst_txserie1_FIFO1_fifo0_BU7_O_UNCONNECTED ); - Inst_rxserie1_FIFO1_fifo0_GND : X_ZERO + Inst_txserie1_FIFO1_fifo0_GND : X_ZERO port map ( - O => Inst_rxserie1_FIFO1_fifo0_N0 + O => Inst_txserie1_FIFO1_fifo0_N0 ); - Inst_rxserie1_FIFO1_fifo0_VCC : X_ONE + Inst_txserie1_FIFO1_fifo0_VCC : X_ONE port map ( - O => Inst_rxserie1_FIFO1_fifo0_N1 + O => Inst_txserie1_FIFO1_fifo0_N1 ); - bus_data_5_IOBUF_OBUFT : X_TRI + bus_data_4_IOBUF_OBUFT : X_TRI port map ( - CTL => bus_data_5_IOBUF_OBUFT_GTS_AND, - I => bus_data_5_IOBUF, - O => bus_data(5) + CTL => bus_data_4_IOBUF_OBUFT_GTS_AND, + I => bus_data_4_IOBUF, + O => bus_data(4) ); - bus_data_5_IOBUF_IBUF : X_BUF + bus_data_4_IOBUF_IBUF : X_BUF port map ( - I => bus_data(5), - O => N10997 + I => bus_data(4), + O => N15393 + ); + bus_data_3_IOBUF_OBUFT : X_TRI + port map ( + CTL => bus_data_3_IOBUF_OBUFT_GTS_AND, + I => bus_data_3_IOBUF, + O => bus_data(3) + ); + bus_data_3_IOBUF_IBUF : X_BUF + port map ( + I => bus_data(3), + O => N15391 ); bus_data_0_IOBUF_OBUFT : X_TRI port map ( @@ -4258,7 +7508,7 @@ begin bus_data_0_IOBUF_IBUF : X_BUF port map ( I => bus_data(0), - O => N10987 + O => N15385 ); bus_data_7_IOBUF_OBUFT : X_TRI port map ( @@ -4269,7 +7519,7 @@ begin bus_data_7_IOBUF_IBUF : X_BUF port map ( I => bus_data(7), - O => N11001 + O => N15399 ); bus_data_1_IOBUF_OBUFT : X_TRI port map ( @@ -4280,51 +7530,7 @@ begin bus_data_1_IOBUF_IBUF : X_BUF port map ( I => bus_data(1), - O => N10989 - ); - bus_data_6_IOBUF_OBUFT : X_TRI - port map ( - CTL => bus_data_6_IOBUF_OBUFT_GTS_AND, - I => bus_data_6_IOBUF, - O => bus_data(6) - ); - bus_data_6_IOBUF_IBUF : X_BUF - port map ( - I => bus_data(6), - O => N10999 - ); - bus_data_2_IOBUF_OBUFT : X_TRI - port map ( - CTL => bus_data_2_IOBUF_OBUFT_GTS_AND, - I => bus_data_2_IOBUF, - O => bus_data(2) - ); - bus_data_2_IOBUF_IBUF : X_BUF - port map ( - I => bus_data(2), - O => N10991 - ); - bus_data_4_IOBUF_OBUFT : X_TRI - port map ( - CTL => bus_data_4_IOBUF_OBUFT_GTS_AND, - I => bus_data_4_IOBUF, - O => bus_data(4) - ); - bus_data_4_IOBUF_IBUF : X_BUF - port map ( - I => bus_data(4), - O => N10995 - ); - bus_data_3_IOBUF_OBUFT : X_TRI - port map ( - CTL => bus_data_3_IOBUF_OBUFT_GTS_AND, - I => bus_data_3_IOBUF, - O => bus_data(3) - ); - bus_data_3_IOBUF_IBUF : X_BUF - port map ( - I => bus_data(3), - O => N10993 + O => N15387 ); Inst_decodisa_dadrL_BU2826 : X_LUT4 generic map( @@ -12552,7 +15758,7 @@ begin ADR1 => Inst_decodisa_dadrL_N1005, ADR2 => Inst_decodisa_dadrL_N1006, ADR3 => Inst_decodisa_dadrL_N0, - O => Inst_decodisa_dadrL_O_6_Q + O => cs(6) ); Inst_decodisa_dadrL_BU84 : X_LUT4 generic map( @@ -12585,7 +15791,7 @@ begin ADR1 => Inst_decodisa_dadrL_N934, ADR2 => Inst_decodisa_dadrL_N935, ADR3 => Inst_decodisa_dadrL_N0, - O => Inst_decodisa_dadrL_O_5_Q + O => cs(5) ); Inst_decodisa_dadrL_BU73 : X_LUT4 generic map( @@ -12618,7 +15824,7 @@ begin ADR1 => Inst_decodisa_dadrL_N863, ADR2 => Inst_decodisa_dadrL_N864, ADR3 => Inst_decodisa_dadrL_N0, - O => Inst_decodisa_dadrL_O_4_Q + O => cs(4) ); Inst_decodisa_dadrL_BU62 : X_LUT4 generic map( @@ -12717,7 +15923,7 @@ begin ADR1 => Inst_decodisa_dadrL_N650, ADR2 => Inst_decodisa_dadrL_N651, ADR3 => Inst_decodisa_dadrL_N0, - O => Inst_decodisa_dadrL_O_1_Q + O => cs(1) ); Inst_decodisa_dadrL_BU29 : X_LUT4 generic map( @@ -12782,433 +15988,803 @@ begin port map ( O => NLW_Inst_decodisa_dadrL_VCC_O_UNCONNECTED ); + clk_ref_BUFGP_BUFG : X_CKBUF + port map ( + I => clk_ref_BUFGP_IBUFG, + O => clk_ref_BUFGP + ); + clk_ref_BUFGP_IBUFG_115 : X_CKBUF + port map ( + I => clk_ref, + O => clk_ref_BUFGP_IBUFG + ); clk_speed_BUFGP_BUFG : X_CKBUF port map ( - I => clk_speed_BUFGP_IBUFG, - O => clk_speed_BUFGP + I => clk_speed_BUFGP_IBUFG, + O => clk_speed_BUFGP + ); + clk_speed_BUFGP_IBUFG_116 : X_CKBUF + port map ( + I => clk_speed, + O => clk_speed_BUFGP_IBUFG + ); + rst_BUFGP_BUFG : X_CKBUF + port map ( + I => rst_BUFGP_IBUFG, + O => rst_BUFGP + ); + rst_BUFGP_IBUFG_117 : X_CKBUF + port map ( + I => rst, + O => rst_BUFGP_IBUFG + ); + Inst_txserie1_RFLAG_REG_2_GSR_OR_118 : X_OR2 + port map ( + I0 => Inst_txserie1_RFLAG_REG_2_n0000, + I1 => GSR, + O => Inst_txserie1_RFLAG_REG_2_GSR_OR + ); + Inst_txserie1_RFLAG_REG_1_GSR_OR_119 : X_OR2 + port map ( + I0 => Inst_txserie1_RFLAG_REG_1_n0000, + I1 => GSR, + O => Inst_txserie1_RFLAG_REG_1_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_0_GSR_OR_120 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_0_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_0_GSR_OR + ); + Inst_rxserie1_RCONF_REG_0_GSR_OR_121 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_rxserie1_RCONF_REG_0_GSR_OR + ); + Inst_rxserie1_FIFO1_wr_en_GSR_OR_122 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_rxserie1_FIFO1_wr_en_GSR_OR + ); + Inst_rxserie1_FIFO1_rd_en_GSR_OR_123 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_rxserie1_FIFO1_rd_en_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_6_GSR_OR_124 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_6_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_6_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_5_GSR_OR_125 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_5_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_5_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_4_GSR_OR_126 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_4_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_4_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_3_GSR_OR_127 : X_OR2 + port map ( + I0 => irqrxRX_OBUF, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_3_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_2_GSR_OR_128 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_2_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_2_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_1_GSR_OR_129 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_1_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_1_GSR_OR + ); + Inst_txserie1_RFLAG_REG_3_GSR_OR_130 : X_OR2 + port map ( + I0 => Inst_txserie1_RFLAG_REG_3_n0000, + I1 => GSR, + O => Inst_txserie1_RFLAG_REG_3_GSR_OR + ); + Inst_txserie1_RCONF_REG_2_GSR_OR_131 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_RCONF_REG_2_GSR_OR + ); + Inst_txserie1_RCONF_REG_7_GSR_OR_132 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_RCONF_REG_7_GSR_OR ); - clk_speed_BUFGP_IBUFG_69 : X_CKBUF + Inst_txserie1_RCONF_REG_3_GSR_OR_133 : X_OR2 port map ( - I => clk_speed, - O => clk_speed_BUFGP_IBUFG + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_RCONF_REG_3_GSR_OR ); - Inst_rxserie1_RCONF_REG_7_GSR_OR_70 : X_OR2 + Inst_txserie1_RCONF_REG_5_GSR_OR_134 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, - O => Inst_rxserie1_RCONF_REG_7_GSR_OR + O => Inst_txserie1_RCONF_REG_5_GSR_OR ); - Inst_rxserie1_RCONF_REG_0_GSR_OR_71 : X_OR2 + Inst_txserie1_RCONF_REG_4_GSR_OR_135 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, - O => Inst_rxserie1_RCONF_REG_0_GSR_OR + O => Inst_txserie1_RCONF_REG_4_GSR_OR ); - Inst_rxserie1_RFLAG_REG_0_GSR_OR_72 : X_OR2 + Inst_rxserie1_RCONF_REG_7_GSR_OR_136 : X_OR2 port map ( - I0 => Inst_rxserie1_RFLAG_REG_0_n0000, + I0 => rst_BUFGP, I1 => GSR, - O => Inst_rxserie1_RFLAG_REG_0_GSR_OR + O => Inst_rxserie1_RCONF_REG_7_GSR_OR ); - Inst_rxserie1_FIFO1_wr_en_GSR_OR_73 : X_OR2 + Inst_txserie1_RCONF_REG_6_GSR_OR_137 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, - O => Inst_rxserie1_FIFO1_wr_en_GSR_OR + O => Inst_txserie1_RCONF_REG_6_GSR_OR ); - Inst_rxserie1_RCONF_REG_6_GSR_OR_74 : X_OR2 + Inst_rxserie1_RCONF_REG_6_GSR_OR_138 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_6_GSR_OR ); - Inst_rxserie1_RCONF_REG_5_GSR_OR_75 : X_OR2 + Inst_rxserie1_RCONF_REG_5_GSR_OR_139 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_5_GSR_OR ); - Inst_rxserie1_RCONF_REG_4_GSR_OR_76 : X_OR2 + Inst_rxserie1_RCONF_REG_4_GSR_OR_140 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_4_GSR_OR ); - Inst_rxserie1_RCONF_REG_3_GSR_OR_77 : X_OR2 + Inst_rxserie1_RCONF_REG_3_GSR_OR_141 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_3_GSR_OR ); - Inst_rxserie1_RFLAG_REG_6_GSR_OR_78 : X_OR2 + Inst_rxserie1_RCONF_REG_2_GSR_OR_142 : X_OR2 port map ( - I0 => Inst_rxserie1_RFLAG_REG_6_n0000, + I0 => rst_BUFGP, I1 => GSR, - O => Inst_rxserie1_RFLAG_REG_6_GSR_OR + O => Inst_rxserie1_RCONF_REG_2_GSR_OR ); - Inst_rxserie1_RCONF_REG_1_GSR_OR_79 : X_OR2 + Inst_rxserie1_RCONF_REG_1_GSR_OR_143 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RCONF_REG_1_GSR_OR ); - Inst_rxserie1_RFLAG_REG_5_GSR_OR_80 : X_OR2 + Inst_txserie1_RCONF_REG_1_GSR_OR_144 : X_OR2 port map ( - I0 => Inst_rxserie1_RFLAG_REG_5_n0000, + I0 => rst_BUFGP, I1 => GSR, - O => Inst_rxserie1_RFLAG_REG_5_GSR_OR + O => Inst_txserie1_RCONF_REG_1_GSR_OR ); - Inst_rxserie1_RCONF_REG_2_GSR_OR_81 : X_OR2 + Inst_txserie1_RFLAG_REG_0_GSR_OR_145 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => Inst_txserie1_RFLAG_REG_0_n0000, I1 => GSR, - O => Inst_rxserie1_RCONF_REG_2_GSR_OR + O => Inst_txserie1_RFLAG_REG_0_GSR_OR ); - Inst_rxserie1_RFLAG_REG_4_GSR_OR_82 : X_OR2 + Inst_txserie1_RCONF_REG_0_GSR_OR_146 : X_OR2 port map ( - I0 => Inst_rxserie1_RFLAG_REG_4_n0000, + I0 => rst_BUFGP, I1 => GSR, - O => Inst_rxserie1_RFLAG_REG_4_GSR_OR + O => Inst_txserie1_RCONF_REG_0_GSR_OR ); - Inst_rxserie1_RFLAG_REG_3_GSR_OR_83 : X_OR2 + Inst_txserie1_TX1_CNT_1_GSR_OR_147 : X_OR2 port map ( - I0 => Inst_rxserie1_RFLAG_REG_3_n0000, + I0 => rst_BUFGP, I1 => GSR, - O => Inst_rxserie1_RFLAG_REG_3_GSR_OR + O => Inst_txserie1_TX1_CNT_1_GSR_OR ); - Inst_rxserie1_RFLAG_REG_2_GSR_OR_84 : X_OR2 + Inst_txserie1_FIFO1_wr_en_GSR_OR_148 : X_OR2 port map ( - I0 => Inst_rxserie1_RFLAG_REG_2_n0000, + I0 => Inst_txserie1_fifopurge, I1 => GSR, - O => Inst_rxserie1_RFLAG_REG_2_GSR_OR + O => Inst_txserie1_FIFO1_wr_en_GSR_OR ); - Inst_rxserie1_RFLAG_REG_1_GSR_OR_85 : X_OR2 + Inst_txserie1_FIFO1_rd_en_GSR_OR_149 : X_OR2 port map ( - I0 => Inst_rxserie1_RFLAG_REG_1_n0000, + I0 => Inst_txserie1_fifopurge, I1 => GSR, - O => Inst_rxserie1_RFLAG_REG_1_GSR_OR + O => Inst_txserie1_FIFO1_rd_en_GSR_OR ); - Inst_rxserie1_RC1_RHR_6_GSR_OR_86 : X_OR2 + Inst_rxserie1_RC1_RHR_6_GSR_OR_150 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_6_GSR_OR ); - Inst_rxserie1_RC1_RHR_3_GSR_OR_87 : X_OR2 + Inst_rxserie1_RC1_RHR_3_GSR_OR_151 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_3_GSR_OR ); - Inst_rxserie1_RC1_RHR_5_GSR_OR_88 : X_OR2 + Inst_rxserie1_RC1_RHR_5_GSR_OR_152 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_5_GSR_OR ); - Inst_rxserie1_RC1_RHR_4_GSR_OR_89 : X_OR2 + Inst_rxserie1_RC1_RHR_4_GSR_OR_153 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_4_GSR_OR ); - Inst_rxserie1_RC1_RHR_0_GSR_OR_90 : X_OR2 + Inst_rxserie1_RC1_RHR_0_GSR_OR_154 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_0_GSR_OR ); - Inst_rxserie1_RC1_RHR_2_GSR_OR_91 : X_OR2 + Inst_rxserie1_RC1_RHR_2_GSR_OR_155 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_2_GSR_OR ); - Inst_rxserie1_RC1_RHR_1_GSR_OR_92 : X_OR2 + Inst_rxserie1_RC1_RHR_1_GSR_OR_156 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_1_GSR_OR ); - Inst_rxserie1_RC1_READ2_GSR_OR_93 : X_OR2 + Inst_rxserie1_RC1_READ2_GSR_OR_157 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_READ2_GSR_OR ); - Inst_rxserie1_RC1_IDLE1_GSR_OR_94 : X_OR2 + Inst_rxserie1_RC1_IDLE1_GSR_OR_158 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_IDLE1_GSR_OR ); - Inst_rxserie1_RC1_READ1_GSR_OR_95 : X_OR2 + Inst_rxserie1_RC1_READ1_GSR_OR_159 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_READ1_GSR_OR ); - Inst_rxserie1_RC1_IDLE_GSR_OR_96 : X_OR2 + Inst_rxserie1_RC1_IDLE_GSR_OR_160 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_IDLE_GSR_OR ); - Inst_rxserie1_RC1_HUNT_GSR_OR_97 : X_OR2 + Inst_rxserie1_RC1_HUNT_GSR_OR_161 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_HUNT_GSR_OR ); - Inst_rxserie1_RC1_RXCNT_1_GSR_OR_98 : X_OR2 + Inst_rxserie1_RC1_RXCNT_1_GSR_OR_162 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXCNT_1_GSR_OR ); - Inst_rxserie1_RC1_RX1_GSR_OR_99 : X_OR2 + Inst_rxserie1_RC1_RX1_GSR_OR_163 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RX1_GSR_OR ); - Inst_rxserie1_RC1_RXCLK_GSR_OR_100 : X_OR2 + Inst_rxserie1_RC1_RXCLK_GSR_OR_164 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXCLK_GSR_OR ); - Inst_rxserie1_RC1_RXPARITY_GSR_OR_101 : X_OR2 + Inst_rxserie1_RC1_RXPARITY_GSR_OR_165 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXPARITY_GSR_OR ); - Inst_rxserie1_RC1_PARITYGEN_GSR_OR_102 : X_OR2 + Inst_rxserie1_RC1_PARITYGEN_GSR_OR_166 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_PARITYGEN_GSR_OR ); - Inst_rxserie1_RC1_RXSTOP_GSR_OR_103 : X_OR2 + Inst_rxserie1_RC1_RXSTOP_GSR_OR_167 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXSTOP_GSR_OR ); - Inst_rxserie1_RC1_RSR_7_GSR_OR_104 : X_OR2 + Inst_rxserie1_RC1_RSR_7_GSR_OR_168 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_7_GSR_OR ); - Inst_rxserie1_RC1_RSR_6_GSR_OR_105 : X_OR2 + Inst_rxserie1_RC1_RSR_6_GSR_OR_169 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_6_GSR_OR ); - Inst_rxserie1_RC1_RSR_5_GSR_OR_106 : X_OR2 + Inst_rxserie1_RC1_RSR_5_GSR_OR_170 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_5_GSR_OR ); - Inst_rxserie1_RC1_RSR_4_GSR_OR_107 : X_OR2 + Inst_rxserie1_RC1_RSR_4_GSR_OR_171 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_4_GSR_OR ); - Inst_rxserie1_RC1_RSR_3_GSR_OR_108 : X_OR2 + Inst_rxserie1_RC1_RSR_3_GSR_OR_172 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_3_GSR_OR ); - Inst_rxserie1_RC1_RSR_2_GSR_OR_109 : X_OR2 + Inst_rxserie1_RC1_RSR_2_GSR_OR_173 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_2_GSR_OR ); - Inst_rxserie1_RC1_RSR_1_GSR_OR_110 : X_OR2 + Inst_rxserie1_RC1_RSR_1_GSR_OR_174 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_1_GSR_OR ); - Inst_rxserie1_RC1_RSR_0_GSR_OR_111 : X_OR2 + Inst_rxserie1_RC1_RSR_0_GSR_OR_175 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RSR_0_GSR_OR ); - Inst_rxserie1_RC1_RHR_7_GSR_OR_112 : X_OR2 + Inst_rxserie1_RC1_RHR_7_GSR_OR_176 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RHR_7_GSR_OR ); - Inst_rxserie1_RC1_RXDATARDY_GSR_OR_113 : X_OR2 + Inst_rxserie1_RC1_RXDATARDY_GSR_OR_177 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXDATARDY_GSR_OR ); - Inst_rxserie1_RC1_OVERRUN_GSR_OR_114 : X_OR2 + Inst_rxserie1_RC1_OVERRUN_GSR_OR_178 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_OVERRUN_GSR_OR ); - Inst_rxserie1_RC1_PARITY_ERR_GSR_OR_115 : X_OR2 + Inst_rxserie1_RC1_PARITY_ERR_GSR_OR_179 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_PARITY_ERR_GSR_OR ); - Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR_116 : X_OR2 + Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR_180 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR ); - Inst_rxserie1_RC1_RXCNT_3_GSR_OR_117 : X_OR2 + Inst_rxserie1_RC1_RXCNT_3_GSR_OR_181 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXCNT_3_GSR_OR ); - Inst_rxserie1_RC1_RXCNT_2_GSR_OR_118 : X_OR2 + Inst_rxserie1_RC1_RXCNT_2_GSR_OR_182 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXCNT_2_GSR_OR ); - Inst_rxserie1_RC1_RXCNT_0_GSR_OR_119 : X_OR2 + Inst_rxserie1_RC1_RXCNT_0_GSR_OR_183 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_RC1_RXCNT_0_GSR_OR ); - Inst_rxserie1_CLOCK1_ckout_GSR_OR_120 : X_OR2 + Inst_txserie1_CLOCK1_ckout_GSR_OR_184 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_CLOCK1_ckout_GSR_OR + ); + Inst_txserie1_CLOCK1_compteur_9_GSR_OR_185 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_CLOCK1_compteur_9_GSR_OR + ); + Inst_txserie1_CLOCK1_compteur_8_GSR_OR_186 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_CLOCK1_compteur_8_GSR_OR + ); + Inst_txserie1_CLOCK1_compteur_0_GSR_OR_187 : X_OR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_0_0_n0000, + I1 => GSR, + O => Inst_txserie1_CLOCK1_compteur_0_GSR_OR + ); + Inst_txserie1_CLOCK1_compteur_1_GSR_OR_188 : X_OR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_0_1_n0000, + I1 => GSR, + O => Inst_txserie1_CLOCK1_compteur_1_GSR_OR + ); + Inst_txserie1_CLOCK1_compteur_2_GSR_OR_189 : X_OR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_0_2_n0000, + I1 => GSR, + O => Inst_txserie1_CLOCK1_compteur_2_GSR_OR + ); + Inst_txserie1_CLOCK1_compteur_3_GSR_OR_190 : X_OR2 + port map ( + I0 => Inst_txserie1_CLOCK1_compteur_0_3_n0000, + I1 => GSR, + O => Inst_txserie1_CLOCK1_compteur_3_GSR_OR + ); + Inst_txserie1_CLOCK1_compteur_4_GSR_OR_191 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_CLOCK1_compteur_4_GSR_OR + ); + Inst_txserie1_CLOCK1_compteur_5_GSR_OR_192 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_CLOCK1_compteur_5_GSR_OR + ); + Inst_txserie1_CLOCK1_compteur_6_GSR_OR_193 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_CLOCK1_compteur_6_GSR_OR + ); + Inst_txserie1_CLOCK1_compteur_7_GSR_OR_194 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_CLOCK1_compteur_7_GSR_OR + ); + Inst_rxserie1_CLOCK1_ckout_GSR_OR_195 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_ckout_GSR_OR ); - Inst_rxserie1_CLOCK1_compteur_9_GSR_OR_121 : X_OR2 + Inst_rxserie1_CLOCK1_compteur_9_GSR_OR_196 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_9_GSR_OR ); - Inst_rxserie1_CLOCK1_compteur_8_GSR_OR_122 : X_OR2 + Inst_rxserie1_CLOCK1_compteur_8_GSR_OR_197 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_8_GSR_OR ); - Inst_rxserie1_CLOCK1_compteur_0_GSR_OR_123 : X_OR2 + Inst_rxserie1_CLOCK1_compteur_0_GSR_OR_198 : X_OR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_0_0_n0000, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_0_GSR_OR ); - Inst_rxserie1_CLOCK1_compteur_1_GSR_OR_124 : X_OR2 + Inst_rxserie1_CLOCK1_compteur_1_GSR_OR_199 : X_OR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_0_1_n0000, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_1_GSR_OR ); - Inst_rxserie1_CLOCK1_compteur_2_GSR_OR_125 : X_OR2 + Inst_rxserie1_CLOCK1_compteur_2_GSR_OR_200 : X_OR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_0_2_n0000, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_2_GSR_OR ); - Inst_rxserie1_CLOCK1_compteur_3_GSR_OR_126 : X_OR2 + Inst_rxserie1_CLOCK1_compteur_3_GSR_OR_201 : X_OR2 port map ( I0 => Inst_rxserie1_CLOCK1_compteur_0_3_n0000, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_3_GSR_OR ); - Inst_rxserie1_CLOCK1_compteur_4_GSR_OR_127 : X_OR2 + Inst_rxserie1_CLOCK1_compteur_4_GSR_OR_202 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_4_GSR_OR ); - Inst_rxserie1_CLOCK1_compteur_5_GSR_OR_128 : X_OR2 + Inst_rxserie1_CLOCK1_compteur_5_GSR_OR_203 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_5_GSR_OR ); - Inst_rxserie1_CLOCK1_compteur_6_GSR_OR_129 : X_OR2 + Inst_rxserie1_CLOCK1_compteur_6_GSR_OR_204 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_6_GSR_OR ); - Inst_rxserie1_CLOCK1_compteur_7_GSR_OR_130 : X_OR2 + Inst_rxserie1_CLOCK1_compteur_7_GSR_OR_205 : X_OR2 port map ( - I0 => rst_IBUF, + I0 => rst_BUFGP, I1 => GSR, O => Inst_rxserie1_CLOCK1_compteur_7_GSR_OR ); - bus_data_0_IOBUF_OBUFT_GTS_AND_131 : X_AND2 + Inst_txserie1_TX1_THR_6_GSR_OR_206 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_THR_6_GSR_OR + ); + Inst_txserie1_TX1_THR_5_GSR_OR_207 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_THR_5_GSR_OR + ); + Inst_txserie1_TX1_THR_3_GSR_OR_208 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_THR_3_GSR_OR + ); + Inst_txserie1_TX1_TSR_0_GSR_OR_209 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TSR_0_GSR_OR + ); + Inst_txserie1_TX1_TSR_1_GSR_OR_210 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TSR_1_GSR_OR + ); + Inst_txserie1_TX1_THR_4_GSR_OR_211 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_THR_4_GSR_OR + ); + Inst_txserie1_TX1_TXDONE1_GSR_OR_212 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TXDONE1_GSR_OR + ); + Inst_txserie1_TX1_WRITE1_GSR_OR_213 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_WRITE1_GSR_OR + ); + Inst_txserie1_TX1_WRITE2_GSR_OR_214 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_WRITE2_GSR_OR + ); + Inst_txserie1_TX1_TXDATARDY_GSR_OR_215 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TXDATARDY_GSR_OR + ); + Inst_txserie1_TX1_THR_7_GSR_OR_216 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_THR_7_GSR_OR + ); + Inst_txserie1_TX1_TXCLK_GSR_OR_217 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TXCLK_GSR_OR + ); + Inst_txserie1_TX1_TAG2_GSR_OR_218 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TAG2_GSR_OR + ); + Inst_txserie1_TX1_TAG1_GSR_OR_219 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TAG1_GSR_OR + ); + Inst_txserie1_TX1_TXPARITY_GSR_OR_220 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TXPARITY_GSR_OR + ); + Inst_txserie1_TX1_TX_GSR_OR_221 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TX_GSR_OR + ); + Inst_txserie1_TX1_TSR_7_GSR_OR_222 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TSR_7_GSR_OR + ); + Inst_txserie1_TX1_TSR_6_GSR_OR_223 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TSR_6_GSR_OR + ); + Inst_txserie1_TX1_TSR_5_GSR_OR_224 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TSR_5_GSR_OR + ); + Inst_txserie1_TX1_TSR_4_GSR_OR_225 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TSR_4_GSR_OR + ); + Inst_txserie1_TX1_TSR_3_GSR_OR_226 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TSR_3_GSR_OR + ); + Inst_txserie1_TX1_TSR_2_GSR_OR_227 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_TSR_2_GSR_OR + ); + Inst_txserie1_TX1_THR_0_GSR_OR_228 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_THR_0_GSR_OR + ); + Inst_txserie1_TX1_THR_1_GSR_OR_229 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_THR_1_GSR_OR + ); + Inst_txserie1_TX1_THR_2_GSR_OR_230 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_THR_2_GSR_OR + ); + Inst_txserie1_TX1_CNT_2_GSR_OR_231 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_CNT_2_GSR_OR + ); + Inst_txserie1_TX1_CNT_0_GSR_OR_232 : X_OR2 + port map ( + I0 => rst_BUFGP, + I1 => GSR, + O => Inst_txserie1_TX1_CNT_0_GSR_OR + ); + bus_data_0_IOBUF_OBUFT_GTS_AND_233 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_0_IOBUF_OBUFT_GTS_AND ); - bus_data_1_IOBUF_OBUFT_GTS_AND_132 : X_AND2 + bus_data_1_IOBUF_OBUFT_GTS_AND_234 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_1_IOBUF_OBUFT_GTS_AND ); - bus_data_2_IOBUF_OBUFT_GTS_AND_133 : X_AND2 + bus_data_2_IOBUF_OBUFT_GTS_AND_235 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_2_IOBUF_OBUFT_GTS_AND ); - bus_data_3_IOBUF_OBUFT_GTS_AND_134 : X_AND2 + bus_data_3_IOBUF_OBUFT_GTS_AND_236 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_3_IOBUF_OBUFT_GTS_AND ); - bus_data_4_IOBUF_OBUFT_GTS_AND_135 : X_AND2 + bus_data_4_IOBUF_OBUFT_GTS_AND_237 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_4_IOBUF_OBUFT_GTS_AND ); - bus_data_5_IOBUF_OBUFT_GTS_AND_136 : X_AND2 + bus_data_5_IOBUF_OBUFT_GTS_AND_238 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_5_IOBUF_OBUFT_GTS_AND ); - bus_data_6_IOBUF_OBUFT_GTS_AND_137 : X_AND2 + bus_data_6_IOBUF_OBUFT_GTS_AND_239 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_6_IOBUF_OBUFT_GTS_AND ); - bus_data_7_IOBUF_OBUFT_GTS_AND_138 : X_AND2 + bus_data_7_IOBUF_OBUFT_GTS_AND_240 : X_AND2 port map ( I0 => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0, I1 => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1, O => bus_data_7_IOBUF_OBUFT_GTS_AND ); - NlwBlock_fpga_VCC : X_ONE + txout1_OBUF_GTS_TRI_241 : X_TRI port map ( - O => VCC + I => txout1_OBUF_GTS_TRI, + CTL => NlwInverterSignal_txout1_OBUF_GTS_TRI_CTL, + O => txout1 + ); + irqtx_OBUF_GTS_TRI_242 : X_TRI + port map ( + I => irqtx_OBUF_GTS_TRI, + CTL => NlwInverterSignal_irqtx_OBUF_GTS_TRI_CTL, + O => irqtx + ); + irqrxFIFO_OBUF_GTS_TRI_243 : X_TRI + port map ( + I => irqrxFIFO_OBUF_GTS_TRI, + CTL => NlwInverterSignal_irqrxFIFO_OBUF_GTS_TRI_CTL, + O => irqrxFIFO + ); + irqrxRX_OBUF_GTS_TRI_244 : X_TRI + port map ( + I => irqrxRX_OBUF_GTS_TRI, + CTL => NlwInverterSignal_irqrxRX_OBUF_GTS_TRI_CTL, + O => irqrxRX + ); + irqrxERR_OBUF_GTS_TRI_245 : X_TRI + port map ( + I => irqrxERR_OBUF_GTS_TRI, + CTL => NlwInverterSignal_irqrxERR_OBUF_GTS_TRI_CTL, + O => irqrxERR ); NlwBlock_fpga_GND : X_ZERO port map ( @@ -13216,42 +16792,46 @@ begin ); NlwInverterBlock_Inst_rxserie1_I7_0_T : X_INV port map ( - I => Inst_rxserie1_I7_N1369, + I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_0_T ); + NlwBlock_fpga_VCC : X_ONE + port map ( + O => VCC + ); NlwInverterBlock_Inst_rxserie1_I7_7_T : X_INV port map ( - I => Inst_rxserie1_I7_N1369, + I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_7_T ); NlwInverterBlock_Inst_rxserie1_I7_6_T : X_INV port map ( - I => Inst_rxserie1_I7_N1369, + I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_6_T ); NlwInverterBlock_Inst_rxserie1_I7_5_T : X_INV port map ( - I => Inst_rxserie1_I7_N1369, + I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_5_T ); NlwInverterBlock_Inst_rxserie1_I7_4_T : X_INV port map ( - I => Inst_rxserie1_I7_N1369, + I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_4_T ); NlwInverterBlock_Inst_rxserie1_I7_3_T : X_INV port map ( - I => Inst_rxserie1_I7_N1369, + I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_3_T ); NlwInverterBlock_Inst_rxserie1_I7_2_T : X_INV port map ( - I => Inst_rxserie1_I7_N1369, + I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_2_T ); NlwInverterBlock_Inst_rxserie1_I7_1_T : X_INV port map ( - I => Inst_rxserie1_I7_N1369, + I => Inst_rxserie1_I7_N1528, O => NlwInverterSignal_Inst_rxserie1_I7_1_T ); NlwInverterBlock_Inst_rxserie1_FIFO1_wr_en_C : X_INV @@ -13259,104 +16839,259 @@ begin I => clk_speed_BUFGP, O => NlwInverterSignal_Inst_rxserie1_FIFO1_wr_en_C ); - NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd1_C : X_INV + NlwInverterBlock_Inst_rxserie1_FIFO1_rd_en_C : X_INV port map ( I => clk_speed_BUFGP, - O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C + O => NlwInverterSignal_Inst_rxserie1_FIFO1_rd_en_C ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_1_T : X_INV port map ( - I => Inst_rxserie1_RFLAG_I1_N1369, + I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_1_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_2_T : X_INV port map ( - I => Inst_rxserie1_RFLAG_I1_N1369, + I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_2_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_0_T : X_INV port map ( - I => Inst_rxserie1_RFLAG_I1_N1369, + I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_0_T ); + NlwInverterBlock_Inst_txserie1_RCONF_I1_1_T : X_INV + port map ( + I => Inst_txserie1_RCONF_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RCONF_I1_1_T + ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_7_T : X_INV port map ( - I => Inst_rxserie1_RFLAG_I1_N1369, + I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_7_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_6_T : X_INV port map ( - I => Inst_rxserie1_RFLAG_I1_N1369, + I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_6_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_5_T : X_INV port map ( - I => Inst_rxserie1_RFLAG_I1_N1369, + I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_5_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_4_T : X_INV port map ( - I => Inst_rxserie1_RFLAG_I1_N1369, + I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_4_T ); NlwInverterBlock_Inst_rxserie1_RFLAG_I1_3_T : X_INV port map ( - I => Inst_rxserie1_RFLAG_I1_N1369, + I => Inst_rxserie1_RFLAG_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_3_T ); + NlwInverterBlock_Inst_txserie1_RCONF_I1_2_T : X_INV + port map ( + I => Inst_txserie1_RCONF_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RCONF_I1_2_T + ); + NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd1_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C + ); + NlwInverterBlock_Inst_txserie1_RCONF_I1_0_T : X_INV + port map ( + I => Inst_txserie1_RCONF_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RCONF_I1_0_T + ); + NlwInverterBlock_Inst_txserie1_RCONF_I1_7_T : X_INV + port map ( + I => Inst_txserie1_RCONF_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RCONF_I1_7_T + ); + NlwInverterBlock_Inst_txserie1_RCONF_I1_6_T : X_INV + port map ( + I => Inst_txserie1_RCONF_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RCONF_I1_6_T + ); + NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd2_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C + ); + NlwInverterBlock_Inst_txserie1_FIFO1_state_write_FFd2_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd2_C + ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_1_T : X_INV port map ( - I => Inst_rxserie1_RCONF_I1_N1369, + I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_1_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_2_T : X_INV port map ( - I => Inst_rxserie1_RCONF_I1_N1369, + I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_2_T ); + NlwInverterBlock_Inst_txserie1_RCONF_I1_5_T : X_INV + port map ( + I => Inst_txserie1_RCONF_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RCONF_I1_5_T + ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_0_T : X_INV port map ( - I => Inst_rxserie1_RCONF_I1_N1369, + I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_0_T ); + NlwInverterBlock_Inst_txserie1_RCONF_I1_4_T : X_INV + port map ( + I => Inst_txserie1_RCONF_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RCONF_I1_4_T + ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_7_T : X_INV port map ( - I => Inst_rxserie1_RCONF_I1_N1369, + I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_7_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_6_T : X_INV port map ( - I => Inst_rxserie1_RCONF_I1_N1369, + I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_6_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_5_T : X_INV port map ( - I => Inst_rxserie1_RCONF_I1_N1369, + I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_5_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_4_T : X_INV port map ( - I => Inst_rxserie1_RCONF_I1_N1369, + I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_4_T ); NlwInverterBlock_Inst_rxserie1_RCONF_I1_3_T : X_INV port map ( - I => Inst_rxserie1_RCONF_I1_N1369, + I => Inst_rxserie1_RCONF_I1_N1528, O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_3_T ); - NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd3_C : X_INV + NlwInverterBlock_Inst_txserie1_RCONF_I1_3_T : X_INV + port map ( + I => Inst_txserie1_RCONF_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RCONF_I1_3_T + ); + NlwInverterBlock_Inst_rxserie1_FIFO1_state_read_FFd3_C : X_INV port map ( I => clk_speed_BUFGP, - O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C + O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd3_C ); - NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd2_C : X_INV + NlwInverterBlock_Inst_rxserie1_FIFO1_state_read_FFd2_C : X_INV port map ( I => clk_speed_BUFGP, - O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C + O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd2_C + ); + NlwInverterBlock_Inst_rxserie1_FIFO1_state_read_FFd1_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd1_C + ); + NlwInverterBlock_Inst_txserie1_FIFO1_state_write_FFd1_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd1_C + ); + NlwInverterBlock_Inst_txserie1_txload_G : X_INV + port map ( + I => rst_BUFGP, + O => NlwInverterSignal_Inst_txserie1_txload_G + ); + NlwInverterBlock_Inst_rxserie1_FIFO1_state_read_FFd4_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_read_FFd4_C + ); + NlwInverterBlock_Inst_txserie1_FIFO1_wr_en_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_txserie1_FIFO1_wr_en_C + ); + NlwInverterBlock_Inst_txserie1_FIFO1_dready_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_txserie1_FIFO1_dready_C + ); + NlwInverterBlock_Inst_txserie1_FIFO1_state_write_FFd3_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_txserie1_FIFO1_state_write_FFd3_C + ); + NlwInverterBlock_Inst_txserie1_FIFO1_rd_en_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_txserie1_FIFO1_rd_en_C + ); + NlwInverterBlock_Inst_txserie1_RFLAG_I1_1_T : X_INV + port map ( + I => Inst_txserie1_RFLAG_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_1_T + ); + NlwInverterBlock_Inst_txserie1_RFLAG_I1_2_T : X_INV + port map ( + I => Inst_txserie1_RFLAG_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_2_T + ); + NlwInverterBlock_Inst_txserie1_FIFO1_state_read_FFd3_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd3_C + ); + NlwInverterBlock_Inst_txserie1_RFLAG_I1_0_T : X_INV + port map ( + I => Inst_txserie1_RFLAG_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_0_T + ); + NlwInverterBlock_Inst_txserie1_RFLAG_I1_7_T : X_INV + port map ( + I => Inst_txserie1_RFLAG_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_7_T + ); + NlwInverterBlock_Inst_txserie1_RFLAG_I1_6_T : X_INV + port map ( + I => Inst_txserie1_RFLAG_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_6_T + ); + NlwInverterBlock_Inst_txserie1_RFLAG_I1_5_T : X_INV + port map ( + I => Inst_txserie1_RFLAG_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_5_T + ); + NlwInverterBlock_Inst_txserie1_RFLAG_I1_4_T : X_INV + port map ( + I => Inst_txserie1_RFLAG_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_4_T + ); + NlwInverterBlock_Inst_txserie1_RFLAG_I1_3_T : X_INV + port map ( + I => Inst_txserie1_RFLAG_I1_N1528, + O => NlwInverterSignal_Inst_txserie1_RFLAG_I1_3_T + ); + NlwInverterBlock_Inst_txserie1_FIFO1_state_read_FFd1_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd1_C + ); + NlwInverterBlock_Inst_txserie1_FIFO1_state_read_FFd4_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_txserie1_FIFO1_state_read_FFd4_C + ); + NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd3_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C ); NlwInverterBlock_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( - I => N4805, + I => N6828, O => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1 : X_INV @@ -13366,7 +17101,7 @@ begin ); NlwInverterBlock_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( - I => N4805, + I => N6828, O => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_1_IOBUF_OBUFT_GTS_AND_IN1 : X_INV @@ -13376,7 +17111,7 @@ begin ); NlwInverterBlock_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( - I => N4805, + I => N6828, O => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_2_IOBUF_OBUFT_GTS_AND_IN1 : X_INV @@ -13386,7 +17121,7 @@ begin ); NlwInverterBlock_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( - I => N4805, + I => N6828, O => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_3_IOBUF_OBUFT_GTS_AND_IN1 : X_INV @@ -13396,7 +17131,7 @@ begin ); NlwInverterBlock_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( - I => N4805, + I => N6828, O => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_4_IOBUF_OBUFT_GTS_AND_IN1 : X_INV @@ -13406,7 +17141,7 @@ begin ); NlwInverterBlock_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( - I => N4805, + I => N6828, O => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_5_IOBUF_OBUFT_GTS_AND_IN1 : X_INV @@ -13416,7 +17151,7 @@ begin ); NlwInverterBlock_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( - I => N4805, + I => N6828, O => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1 : X_INV @@ -13426,7 +17161,7 @@ begin ); NlwInverterBlock_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0 : X_INV port map ( - I => N4805, + I => N6828, O => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0 ); NlwInverterBlock_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1 : X_INV @@ -13434,6 +17169,31 @@ begin I => GTS, O => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1 ); + NlwInverterBlock_txout1_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_txout1_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_irqtx_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_irqtx_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_irqrxFIFO_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_irqrxFIFO_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_irqrxRX_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_irqrxRX_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_irqrxERR_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_irqrxERR_OBUF_GTS_TRI_CTL + ); NlwBlockROC : X_ROC generic map (ROC_WIDTH => 100 ns) port map (O => GSR); diff --git a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd index 25fadff..0014d05 100644 --- a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd +++ b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd @@ -73,7 +73,7 @@ begin combi:process(state) begin - clk <= '0'; + clk <= '1'; rw <= '0'; bus_data <= (others => 'Z'); csData <= '0'; @@ -87,14 +87,14 @@ begin when 2 => bus_data<="01110111"; csConfig<='1'; rw<='0'; - clk<='1'; + clk<='0'; when 4 => bus_data<="00010110"; csData<='1'; rw<='0'; when 5 => bus_data<="00010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; when 70 => bus_data<="00010110"; csData<='1'; @@ -102,14 +102,14 @@ begin when 71 => bus_data<="00010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; when 12 => csFlag<='1'; rw<='1'; when 13 => csFlag<='1'; rw<='1'; - clk<='1'; + clk<='0'; when 20 => bus_data<="01010101"; @@ -118,7 +118,7 @@ begin when 21 => bus_data<="01010101"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; when 1004 => bus_data<="00010110"; csData<='1'; @@ -126,7 +126,7 @@ begin when 1005 => bus_data<="00010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1007 => bus_data<="01010110"; csData<='1'; @@ -134,7 +134,7 @@ begin when 1008 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1010 => bus_data<="01010110"; csData<='1'; @@ -142,7 +142,7 @@ begin when 1011 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1013 => bus_data<="01010110"; csData<='1'; @@ -150,7 +150,7 @@ begin when 1014 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1016 => bus_data<="01010110"; csData<='1'; @@ -158,7 +158,7 @@ begin when 1017 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1019 => bus_data<="01010110"; csData<='1'; @@ -166,7 +166,7 @@ begin when 1020 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1022 => bus_data<="01010110"; csData<='1'; @@ -174,7 +174,7 @@ begin when 1023 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1025 => bus_data<="01010110"; csData<='1'; @@ -182,7 +182,7 @@ begin when 1026 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1028 => bus_data<="01010110"; csData<='1'; @@ -190,7 +190,7 @@ begin when 1029 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1031 => bus_data<="01010110"; csData<='1'; @@ -198,7 +198,7 @@ begin when 1032 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1034 => bus_data<="01010110"; csData<='1'; @@ -206,7 +206,7 @@ begin when 1035 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1037 => bus_data<="01010110"; csData<='1'; @@ -214,7 +214,7 @@ begin when 1038 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1040 => bus_data<="01010110"; csData<='1'; @@ -222,7 +222,7 @@ begin when 1041 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1043 => bus_data<="01010110"; csData<='1'; @@ -230,7 +230,7 @@ begin when 1044 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1046 => bus_data<="01010110"; csData<='1'; @@ -238,7 +238,7 @@ begin when 1047 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1049 => bus_data<="01010110"; csData<='1'; @@ -246,7 +246,7 @@ begin when 1050 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1052 => bus_data<="01010110"; csData<='1'; @@ -254,7 +254,7 @@ begin when 1053 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1055 => bus_data<="01010110"; csData<='1'; @@ -262,7 +262,7 @@ begin when 1056 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1058 => bus_data<="01010110"; csData<='1'; @@ -270,7 +270,7 @@ begin when 1059 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1061 => bus_data<="01010110"; csData<='1'; @@ -278,7 +278,7 @@ begin when 1062 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; -- when 1064 => bus_data<="01010110"; csData<='1'; @@ -286,7 +286,7 @@ begin when 1065 => bus_data<="01010110"; csData<='1'; rw<='0'; - clk<='1'; + clk<='0'; when others => null; diff --git a/2004/n/fpga/src/portserie/portserie/txserie.vhd b/2004/n/fpga/src/portserie/portserie/txserie.vhd index 2b94529..ece9754 100644 --- a/2004/n/fpga/src/portserie/portserie/txserie.vhd +++ b/2004/n/fpga/src/portserie/portserie/txserie.vhd @@ -169,6 +169,7 @@ RCONF : regIO port map( load=>dummy(0), ck=>bus_clk, rst=>rst); +-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) -- Flag : (x ! x ! x ! x ! Empty ! Full ! FLI1 ! FLI0 ) RFLAG : regIO port map( @@ -196,12 +197,17 @@ flagreg(3)<=fifoEmpty; -- irq minirq<=fifoFull and confreg(2); --fifo full AND Int/En + -- controle des flux -fifockin <= (csData and bus_clk and not rw and not rst); +fifockin <= (csData and not bus_clk and not rw and not rst); fifockout <= (txready and not fifoEmpty); -process(fifodready,txready) + +process(fifodready,txready,rst) begin +if(rst='1') then + state_txload<= 0; +else txload <= '0'; case state_txload is when 0 => if(txready='1') then @@ -232,6 +238,7 @@ begin end if; when others => state_txload <= 0; end case; +end if; end process; diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd index e0ec325..46d2a31 100644 --- a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd +++ b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd @@ -169,7 +169,7 @@ RCONF : regIO port map( load=>dummy(0), ck=>bus_clk, rst=>rst); - +-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0) -- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 ) RFLAG : regIO port map( cs=>csFlag, -- cgit v1.2.3