From 6b0130e85b84140dbbcd476f61e63e37160fe4d1 Mon Sep 17 00:00:00 2001 From: galmes Date: Sat, 28 Feb 2004 22:01:21 +0000 Subject: Registres tous mis dans le même répertoire. --- 2004/n/fpga/src/registre/bch_reg_8.vhd | 54 ++++++++++++++++++++++++++ 2004/n/fpga/src/registre/bch_reg_rw.vhd | 68 +++++++++++++++++++++++++++++++++ 2004/n/fpga/src/registre/reg_8.vhd | 33 ++++++++++++++++ 2004/n/fpga/src/registre/reg_rw.vhd | 53 +++++++++++++++++++++++++ 4 files changed, 208 insertions(+) create mode 100644 2004/n/fpga/src/registre/bch_reg_8.vhd create mode 100644 2004/n/fpga/src/registre/bch_reg_rw.vhd create mode 100644 2004/n/fpga/src/registre/reg_8.vhd create mode 100644 2004/n/fpga/src/registre/reg_rw.vhd (limited to '2004/n/fpga') diff --git a/2004/n/fpga/src/registre/bch_reg_8.vhd b/2004/n/fpga/src/registre/bch_reg_8.vhd new file mode 100644 index 0000000..4538de2 --- /dev/null +++ b/2004/n/fpga/src/registre/bch_reg_8.vhd @@ -0,0 +1,54 @@ +-- bch_reg_8.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- test bench du registre 8 bits + +library ieee; +use ieee.std_logic_1164.all; +--use ieee.std_logic_arith.all; + +use work.nono_const.all; + +entity bch_reg_8 is +end bch_reg_8; + +architecture sim_1 of bch_reg_8 is + component reg_8 + port( + rst : in std_logic; + clk : in std_logic; + en : in std_logic; -- enable + input : in std_logic_vector (7 downto 0); + output : out std_logic_vector (7 downto 0) + ); + end component; + signal rst : std_logic; + signal clk : std_logic := '0'; + signal en : std_logic := '0'; + signal input : std_logic_vector (7 downto 0); + signal output : std_logic_vector (7 downto 0); + + begin + U0 : reg_8 port map (rst => rst, clk => clk, en => en, + input => input, output => output); + + rst <= '1', '0' after (CK_PERIOD/5); + clk <= not clk after CK_PERIOD/2; + en <= '0', + '1' after (CK_PERIOD*1), + '0' after (CK_PERIOD*3), + '1' after (CK_PERIOD*5), + '0' after (CK_PERIOD*7); + input <= x"00", + x"05" after (CK_PERIOD/2), + x"01" after (CK_PERIOD*3); + +end sim_1; + +--configuration + +configuration cf_bch_reg_8 of bch_reg_8 is + for sim_1 + for U0 : reg_8 use entity work.reg_8(RTL); end for; + end for; +end cf_bch_reg_8; diff --git a/2004/n/fpga/src/registre/bch_reg_rw.vhd b/2004/n/fpga/src/registre/bch_reg_rw.vhd new file mode 100644 index 0000000..07b7cc2 --- /dev/null +++ b/2004/n/fpga/src/registre/bch_reg_rw.vhd @@ -0,0 +1,68 @@ +-- bch_reg_rw.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Test de reg_rw. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity bch_reg_rw is +end bch_reg_rw; + +architecture sim1 of bch_reg_rw is + + component reg_rw + port ( + clk : in std_logic; + rst : in std_logic; + rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE) + enable : in std_logic; + data : inout T_DATA; + data_out : out T_DATA + ); + end component; + + -- définiton des signaux + signal clk : std_logic := '0'; + signal rst : std_logic; + signal rw : std_logic; -- read / write + signal enable : std_logic; + signal data : T_DATA; + signal data_out : T_DATA; + +begin + U1 : reg_rw port map ( + clk => clk, + rst => rst, + rw => rw, + enable => enable, + data => data, + data_out => data_out + ); + + clk <= not clk after CK_PERIOD/2; + rst <= '1', '0' after CK_PERIOD; + enable <= '0', + '1' after 2*CK_PERIOD, + '0' after 3*CK_PERIOD, + '1' after 5*CK_PERIOD, + '0' after 6*CK_PERIOD; + rw <= '1', '0' after 3*CK_PERIOD; + data <= x"01", + x"02" after 3*CK_PERIOD, + "ZZZZZZZZ" after 5*CK_PERIOD; + --x"03" after 5*CK_PERIOD; +end sim1; + +configuration cf1_bch_reg_rw of bch_reg_rw is + for sim1 + for all : reg_rw use entity work.reg_rw(RTL); end for; + end for; +end cf1_bch_reg_rw; + diff --git a/2004/n/fpga/src/registre/reg_8.vhd b/2004/n/fpga/src/registre/reg_8.vhd new file mode 100644 index 0000000..f32f7d9 --- /dev/null +++ b/2004/n/fpga/src/registre/reg_8.vhd @@ -0,0 +1,33 @@ +-- reg_8.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Registre 8 bits. + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +entity reg_8 is + port ( + rst : in std_logic; + clk : in std_logic; + en : in std_logic; -- enable + input : in std_logic_vector (7 downto 0); + output : out std_logic_vector (7 downto 0) + ); +end reg_8; + +architecture RTL of reg_8 is +begin + process (rst, clk) + begin + if (rst ='1') then + output <= x"00"; + elsif (clk'event and clk = '1') then + if (en='1') then + output <= input; + end if; + end if; + end process; +end RTL; diff --git a/2004/n/fpga/src/registre/reg_rw.vhd b/2004/n/fpga/src/registre/reg_rw.vhd new file mode 100644 index 0000000..1c81139 --- /dev/null +++ b/2004/n/fpga/src/registre/reg_rw.vhd @@ -0,0 +1,53 @@ +-- reg_rw.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Registre dont la valeur est accessible en lecture. + +-- Principe : +-- Si (write et enable) alors sauvegarde entrée et copie entrée sur sortie. +-- Si (read et enable) alors copie dernière valeur sauvegardée sur entrée. +-- Si (pas enable) alors copie dernière valeur sauvegardée sur sortie. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity reg_rw is + port ( + clk : in std_logic; + rst : in std_logic; + rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE) + enable : in std_logic; + data : inout T_DATA; + data_out : out T_DATA -- data courant + ); +end entity; + +architecture RTL of reg_rw is + -- signal interne + signal REG : T_DATA; +begin + -- partie séquentielle. + process (rst, clk) + begin + -- reset + if (rst = '1') then + REG <= (others => '0'); + -- écriture des données. + elsif (clk'event and clk = '1') then + if (enable = '1' and rw = ISA_WRITE) then + REG <= data; + end if; + end if; + end process; + + -- partie combinatoire. + data <= REG when (enable = '1' and rw = ISA_READ) else (others => 'Z'); + data_out <= REG; + +end RTL; -- cgit v1.2.3