From 87b82909048734b06777a486cece1320ed6b6a0d Mon Sep 17 00:00:00 2001 From: galmes Date: Thu, 26 Feb 2004 16:53:40 +0000 Subject: Ajout d'un test bench pour les gpio. Il n'est pas achevé, mais compile et permet de tester les parties : - décodage, - gestion de la direction - lecture et écriture dans les registre. - ... Il ne reste que la gestion des interruptions à traiter :) --- 2004/n/fpga/src/gpio/bch_gpio.vhd | 153 ++++++++++++++++++++++++++++++++ 2004/n/fpga/src/gpio/gpio.vhd | 14 +-- 2004/n/fpga/src/gpio/gpio_it_detect.vhd | 4 +- 3 files changed, 162 insertions(+), 9 deletions(-) create mode 100644 2004/n/fpga/src/gpio/bch_gpio.vhd (limited to '2004/n/fpga/src') diff --git a/2004/n/fpga/src/gpio/bch_gpio.vhd b/2004/n/fpga/src/gpio/bch_gpio.vhd new file mode 100644 index 0000000..d785248 --- /dev/null +++ b/2004/n/fpga/src/gpio/bch_gpio.vhd @@ -0,0 +1,153 @@ +-- bch_gpio.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Banc de test. + +-- RQ : Observer 300ns + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity bch_gpio is +end bch_gpio; + +architecture sim1 of bch_gpio is + + component gpio + generic ( + A_REG_DATA_WRITE : T_ADDRESS; + A_REG_DIRECTION : T_ADDRESS; + A_REG_INTERRUPT_MASK : T_ADDRESS; + A_DATA_READ_OUTPUT : T_ADDRESS + ); + port( + rst : in std_logic; + clk_i : in std_logic; -- clock du bus isa + clk_m : in std_logic; -- master clock + rw : in std_logic; -- read (0) / write (1) TODO ?? + interrupt : out std_logic; + bus_address : in T_ADDRESS; + bus_data : inout T_DATA; + io_output : inout T_DATA + ); + end component; + + -- définiton des signaux + signal rst : std_logic; + signal clk_i : std_logic := '0'; + signal clk_m : std_logic := '0'; + signal rw : std_logic := '0'; + signal interrupt : std_logic; + signal bus_address : T_ADDRESS; + signal bus_data : T_DATA; + signal io_output : T_DATA; + +begin + -- ----------------------------------------------------- + -- mapping du gpio. A reprendre pour le mapping final !! + -- ----------------------------------------------------- + U1 : gpio + generic map ( + -- Définition des addresses. + A_REG_DATA_WRITE => A_IO1_REG_DATA, + A_REG_DIRECTION => A_IO1_REG_DIRECTION, + A_REG_INTERRUPT_MASK => A_IO1_REG_INTERRUPT_MASK, + A_DATA_READ_OUTPUT => A_IO1_READ_OUTPUT + ) + port map ( + rst => rst, + clk_i => clk_i, + clk_m => clk_m, + rw => rw, + interrupt => interrupt, + bus_address => bus_address, + bus_data => bus_data, + io_output => io_output + ); + + -- --------------------------------- + -- Process de test. + -- --------------------------------- + process + + -- ---------------------------------- + -- déclaration de procédures de test. + -- ---------------------------------- + -- Lire dans un registre ou la sortie ! + procedure do_read (address : in T_ADDRESS) is + begin + rw <= ISA_READ; + bus_address <= address; + bus_data <= "ZZZZZZZZ"; --est en sortie. + end do_read; + + -- Ecrire dans un registre ! + procedure do_write (address : in T_ADDRESS; data : in T_DATA) is + begin + rw <= ISA_WRITE; + bus_address <= address; + bus_data <= data; + end do_write; + + -- Tester que le décodeur fonctionne correctement. + --procedure test_decod (bidon1 : in std_logic) is + --begin + --end test_decod; + + -- ------------------------- + -- Début du process de test. + -- ------------------------- + begin + -- Ecriture dans les trois registres. + wait for (3*CK_PERIOD); + do_write (A_IO1_REG_DIRECTION, x"07"); + wait for (3*CK_PERIOD); + do_write (A_IO1_REG_DATA, x"01"); + wait for (3*CK_PERIOD); + do_write (A_IO1_REG_INTERRUPT_MASK, x"04"); + + -- Lecture dans les trois registres. + wait for (3*CK_PERIOD); + do_read (A_IO1_REG_INTERRUPT_MASK); + wait for (3*CK_PERIOD); + do_read (A_IO1_REG_DIRECTION); + wait for (3*CK_PERIOD); + do_read (A_IO1_REG_DATA); + + -- Lecture de la donnée sur io_output. + wait for (3*CK_PERIOD); + do_read (A_IO1_READ_OUTPUT); + + -- test du signal d'interruption + wait for (3*CK_PERIOD); + do_write (A_IO1_REG_DATA, x"02"); + wait for (3*CK_PERIOD); + do_write (A_IO1_REG_DATA, x"01"); + + + end process; + + rst <= '1','0' after (CK_PERIOD/5); + clk_m <= not clk_m after (CK_PERIOD/2); + + --bus_address <= A_IO1_REG_INTERRUPT_MASK, + -- A_IO1_READ_OUTPUT after 3*CK_PERIOD, + -- A_IO1_REG_DIRECTION after 5*CK_PERIOD, + -- A_IO1_REG_DATA after 7*CK_PERIOD; + + +end sim1; + +-- Configuration +configuration cf1_bch_gpio of bch_gpio is + for sim1 + for all : gpio use entity work.gpio(RTL); end for; + end for; +end cf1_bch_gpio; + diff --git a/2004/n/fpga/src/gpio/gpio.vhd b/2004/n/fpga/src/gpio/gpio.vhd index 90704f3..3329997 100644 --- a/2004/n/fpga/src/gpio/gpio.vhd +++ b/2004/n/fpga/src/gpio/gpio.vhd @@ -13,9 +13,9 @@ use work.nono_const.all; entity gpio is generic ( A_REG_DATA_WRITE : T_ADDRESS; - A_REG_DATA_READ : T_ADDRESS; A_REG_DIRECTION : T_ADDRESS; - A_REG_INTERRUPT_MASK : T_ADDRESS + A_REG_INTERRUPT_MASK : T_ADDRESS; + A_DATA_READ_OUTPUT : T_ADDRESS ); port( rst : in std_logic; @@ -148,11 +148,11 @@ port map ( Reg_it_mask : reg_rw port map ( clk_m, -rst, -rw, -en_reg_data, -bus_data, -bus_it_mask + rst, + rw, + en_reg_it_mask, + bus_data, + bus_it_mask ); -- diff --git a/2004/n/fpga/src/gpio/gpio_it_detect.vhd b/2004/n/fpga/src/gpio/gpio_it_detect.vhd index 1f1d69b..3511c63 100644 --- a/2004/n/fpga/src/gpio/gpio_it_detect.vhd +++ b/2004/n/fpga/src/gpio/gpio_it_detect.vhd @@ -6,8 +6,8 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_arith.all; +--use ieee.std_logic_unsigned.all; use work.isa_const.all; use work.nono_const.all; -- cgit v1.2.3