From 0213d3145f743a12e13b5b7602f0614e444a36a7 Mon Sep 17 00:00:00 2001 From: galmes Date: Thu, 18 Mar 2004 09:50:49 +0000 Subject: Les fichiers sont synthétysables, bien qu'il me reste des doutes pour savoir si tout fonctionne vraiment sans problèmes. --- 2004/n/fpga/src/registre/bch_reg_rw.vhd | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to '2004/n/fpga/src/registre/bch_reg_rw.vhd') diff --git a/2004/n/fpga/src/registre/bch_reg_rw.vhd b/2004/n/fpga/src/registre/bch_reg_rw.vhd index 07b7cc2..f42b090 100644 --- a/2004/n/fpga/src/registre/bch_reg_rw.vhd +++ b/2004/n/fpga/src/registre/bch_reg_rw.vhd @@ -36,6 +36,8 @@ architecture sim1 of bch_reg_rw is signal data : T_DATA; signal data_out : T_DATA; + constant CK_PERIOD : time := 10 ns; + begin U1 : reg_rw port map ( clk => clk, @@ -53,7 +55,7 @@ begin '0' after 3*CK_PERIOD, '1' after 5*CK_PERIOD, '0' after 6*CK_PERIOD; - rw <= '1', '0' after 3*CK_PERIOD; + rw <= ISA_WRITE, ISA_READ after 3*CK_PERIOD; data <= x"01", x"02" after 3*CK_PERIOD, "ZZZZZZZZ" after 5*CK_PERIOD; -- cgit v1.2.3