From e9078d509d9634b853958576ac7de4960b1e1f10 Mon Sep 17 00:00:00 2001 From: galmes Date: Thu, 18 Mar 2004 13:00:06 +0000 Subject: Ajout des fichiers de bench sous ISE --- 2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.tbw | 47 +++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.tbw (limited to '2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.tbw') diff --git a/2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.tbw b/2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.tbw new file mode 100644 index 0000000..c4ec12e --- /dev/null +++ b/2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.tbw @@ -0,0 +1,47 @@ +info x 37 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL +col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  +radix x 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  +entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reg_rw +term mark 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  +vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library work; +use work.isa_const.all; +use work.nono_const.all; + +var add 1 0 0 226 23 0 257 100 50 50 10 10 0 0 0 0 clkInstd_logicFALLING_EDGEclk +var add 2 0 0 98 24 0 257 100 50 50 10 10 0 0 0 0 rstInstd_logicFALLING_EDGEclk +var add 3 0 0 98 25 0 257 100 50 50 10 10 0 0 0 0 rwInstd_logicFALLING_EDGEclk +var add 4 0 0 98 26 0 257 100 50 50 10 10 0 0 0 0 enableInstd_logicFALLING_EDGEclk +var add 6 7 0 100 28 0 257 100 50 50 10 10 0 0 0 0 data_outOutstd_logic_vectorFALLING_EDGEclk +var add 5 7 0 100 27 0 257 100 50 50 10 10 0 0 0 0 dataInOutstd_logic_vectorFALLING_EDGEclk +vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  +npos xxx 120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  +cell fill 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +cell fill 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cell fill 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cell fill 3 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +cell fill 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cell fill 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +cell fill 4 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cell fill 4 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +cell fill 4 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cell fill 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001 +cell fill 6 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000010 +cell fill 6 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZZZZZZZZ +time info 50 50 10 10 50 50 1 0 0 0 0 0 0 0 0 0 nsclk +font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman +src mod 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\registre\reg_rw.vhd +utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  +cellenab on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  +grid on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  +com add 1 1 16 499 11 -16 -95 0 0 0 0 0 0 0 0 0 Waveform created by +HDL Bencher 6.1i +Source = f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\registre\reg_rw.vhd +Sat Mar 13 17:10:47 2004 +opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  +NumClocks x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  +clock_1 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk +Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.66666666666667 -- cgit v1.2.3