From b2e2ac2333ac00f53cc3b173b6433e7f5b59a36f Mon Sep 17 00:00:00 2001 From: prot Date: Sun, 14 Mar 2004 23:32:28 +0000 Subject: Port série de Bob Villedieu --- 2004/n/fpga/src/portserie/uart/uart.vhd | 86 +++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 2004/n/fpga/src/portserie/uart/uart.vhd (limited to '2004/n/fpga/src/portserie/uart/uart.vhd') diff --git a/2004/n/fpga/src/portserie/uart/uart.vhd b/2004/n/fpga/src/portserie/uart/uart.vhd new file mode 100644 index 0000000..89ff76d --- /dev/null +++ b/2004/n/fpga/src/portserie/uart/uart.vhd @@ -0,0 +1,86 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +entity UART is + port ( + MCLKX16 : in std_logic; + READ : in std_logic; + WRITE : in std_logic; + RESET : in std_logic; + + DATA : inout std_logic_vector(7 downto 0); + + -- receiver input signal, error, and status flags + + RX : in std_logic; + RXRDY : out std_logic; + PARITY_ERR : out std_logic; + FRAMING_ERR : out std_logic; + OVERRUN : out std_logic; + + -- transmitter output signal and status flag + + TX : out std_logic; + TXRDY : out std_logic + ); +end UART; + +architecture TOP OF UART is + +signal RXDATA : std_logic_vector(7 downto 0); + +component TXMIT + port ( + MCLKX16 : in std_logic; + WRITE : in std_logic; + RESET : in std_logic; + DATA : in std_logic_vector(7 downto 0); + TX : out std_logic; + TXRDY : out std_logic + ); +end component; + +component RXCVER + port ( + MCLKX16 : in std_logic; + READ : in std_logic; + RX : in std_logic; + RESET : in std_logic; + + RXRDY : out std_logic; + PARITY_ERR : out std_logic; + FRAMING_ERR : out std_logic; + OVERRUN : out std_logic; + DATA : out std_logic_vector(7 downto 0) + ); +end component; + +begin + + TRANSMITTER : TXMIT port map + ( + MCLKX16 => MCLKX16, + WRITE => WRITE, + RESET => RESET, + DATA => DATA, + TX => TX, + TXRDY => TXRDY + ); + + + RECEIVER : RXCVER port map + ( + MCLKX16 => MCLKX16, + READ => READ, + RX => RX, + RESET => RESET, + RXRDY => RXRDY, + PARITY_ERR => PARITY_ERR, + FRAMING_ERR => FRAMING_ERR, + OVERRUN => OVERRUN, + DATA => RXDATA + ); + + DATA <= RXDATA when (READ = '0') else "ZZZZZZZZ"; + +end TOP; -- cgit v1.2.3