From 0a1f5ed5b441501c01dbf94f80828952f091c433 Mon Sep 17 00:00:00 2001 From: prot Date: Mon, 23 Feb 2004 14:28:44 +0000 Subject: Ajout des fichiers vhdl des vacances --- 2004/n/fpga/src/portserie/modele.vhd | 603 +++++++++++++++++++++++++++++++++++ 1 file changed, 603 insertions(+) create mode 100644 2004/n/fpga/src/portserie/modele.vhd (limited to '2004/n/fpga/src/portserie/modele.vhd') diff --git a/2004/n/fpga/src/portserie/modele.vhd b/2004/n/fpga/src/portserie/modele.vhd new file mode 100644 index 0000000..3186341 --- /dev/null +++ b/2004/n/fpga/src/portserie/modele.vhd @@ -0,0 +1,603 @@ +-- txserie.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre Prot + +-- ------------------------------------------- +-- Port série TX pour le fpga robot +-- ------------------------------------------- +-- +-- * Prend 3 adresses mémoire : +-- 0 - Txdata +-- 1 - Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0) +-- 2 - Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) +-- * Mettre le bit On/Off à 1 pour activer la transmission +-- * Chaque écriture dans txdata charge la donnée dans la fifo +-- * Dès que le registre à décalage est vide, il enlève le dernier élément de +-- la fifo et le transmet +-- * Deux bits de stop +-- * Quand la fifo est pleine, met le flag Full/Int à 1 et génère une +-- interruption. Il faut alors mettre à 0 le bit IntEn, qui sera remis à 1 à +-- la prochaine écriture dans la fifo +-- * On peut lire l'état de la pile dans le registre de flags +-- * On peut vider la pile en mettant Purge à 1 +-- * Baudrate disponible : +-- BdR1/0 ! Baudrate +-- 00 ! 9600 +-- 01 ! 19200 +-- 10 ! 57600 +-- 11 ! 115200 + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.nono_const.all; + +entity txserie is + generic ( + -- adresses des différents registres du module. + A_DATA : T_ADDRESS ; + A_CONFIG : T_ADDRESS ; + A_FLAG : T_ADDRESS + -- si autre choses à déclarer... + ); + port ( + rst : in std_logic; + clk : in std_logic; + + -- XXX : savoir si read = 0 ou 1 !! + rw : in std_logic; -- read (0) / write (1) + + bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0); + bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0) + ); +end entity; + + +entity txserie is +generic(adr : integer); +constant adr_w : integer :=10; +port( + adrbus: in std_logic_vector((adr_w - 1) downto 0); + databus: inout std_logic_vector(7 downto 0); + rw: in std_logic; + busck: in std_logic; + rst: in std_logic; + masterck: in std_logic; + txout: out std_logic; + intout: out std_logic; + ); +end txserie; + +architecture rtl of txserie is + +component registre + generic(adr : integer); + port( + adrbus: in std_logic_vector((adr_w - 1) downto 0); + databus: inout std_logic_vector(7 downto 0); + input: in std_logic_vector(7 downto 0); + output: out std_logic_vector(7 downto 0); + rw: in std_logic; + load: in std_logic; + ck: in std_logic; + rst: in std_logic + ); +end component; + +component fifo + port( + data_in: in std_logic_vector(7 downto 0); + data_out: in std_logic_vector(7 downto 0); + ck_in: in std_logic; + ck_out: in std_logic; + f0: out std_logic; + f1: out std_logic; + f2: out std_logic; + f3: out std_logic; + purge: in std_logic + ); +end component; + +component transmitter + port( + data_in: in std_logic_vector(7 downto 0); + ck: in std_logic; + flag: out std_logic; + txout: out std_logic + ); +end component; + +component clockgene + port( + ck_in: in std_logic; + ck_out: in std_logic; + param: in std_logic_vector(1 downto 0) + ); +end component; + +component decoder + generic(adr : integer); + port( + adrbus: in std_logic_vector((adr_w - 1) downto 0); + cs: out std_logic + ); +end component; + + +signal fifoEmpty: std_logic; +signal fifoFull: std_logic; +signal fifoLI1: std_logic; +signal fifoLI0: std_logic; +signal BdR1: std_logic; +signal BdR0: std_logic; +signal purge: std_logic; +signal geneck: std_logic; +signal txck: std_logic; +signal busck: std_logic; +signal adrbus: std_logic_vector((adr_w - 1) downto 0); +signal databus: std_logic_vector(7 downto 0); +signal rw: std_logic; +signal rst: std_logic; +signal txdata: std_logic; +signal txempty: std_logic; +signal csFifo: std_logic; +signal fifockin: std_logic; +signal fifockout: std_logic; + +FIFO1: fifo + port map( + data_in=>databus, + data_out=>txdata, + ck_in=>fifockin, + ck_out=>fifockout + f0=>fifoEmpty, + f1=>fifoLI0, + f2=>fifoLI1, + f3=>fifoFull, + purge=>confreg(3) + ); + +fifockin<=csFifo and not rw and busck; +fifockout<=txempty; -- à vérifier !!! Cette ligne est valable pour + -- txempty=1 quand le tx est vide + +TX1 : transmitter + port map( + data_in=>txdata, + ck=>txck, + flag=>txempty, + txout=>txout, + ); + +CLOCK1 : clockgene + port map( + ck_in=>geneck, + ck_out=>txck, + param=>confreg(1 downto 0) + ); +geneck<=confreg(4) and masterck; -- On/Off et masterck + + +-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) +RCONF : registre + generic map(adr=>adr+1) + port map( + adrbus=>adrbus, + databus=>databus, + input=>(others => '0'), + output=>confreg, + rw=>rw, + load=>'0', + ck=>busck, + rst=>'0' + ); + +-- Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0) +RFLAG : registre + generic map(adr=>adr+2) + port map( + adrbus=>adrbus, + databus=>databus, + input=>flagreg, + output=>open, + rw=>rw, + load=>'1', + ck=>busck, + rst=>'0' + ); + +flagreg(7 downto 3)<=(others => '0'); +flagreg(3)<=txempty; +flagreg(2)<=fifoFull; +flagreg(1)<=fifoLI1; +flagreg(0)<=fifoLI0; + +-- la sortie intout est active si la pile est pleine ET si le bit de conf est +-- activé +intout<=fifoFull and confreg(2); -- IntEn et fifoFull + +DECOD : decoder + generic map(adr=>adr) + port map( + adrbus=>adrbus, + cs=>csFifo + ); +end rtl; + + + +library ieee; +library ieee.std_logic_1164.all; + +entity txserie is +generic(adr : integer); +constant adr_w : integer :=10; +port( + adrbus: in std_logic_vector((adr_w - 1) downto 0); + databus: inout std_logic_vector(7 downto 0); + rw: in std_logic; + busck: in std_logic; + rst: in std_logic; + masterck: in std_logic; + txout: out std_logic; + intout: out std_logic; + ); +end txserie; + +architecture rtl of txserie is + +component registre + generic(adr : integer); + port( + adrbus: in std_logic_vector((adr_w - 1) downto 0); + databus: inout std_logic_vector(7 downto 0); + input: in std_logic_vector(7 downto 0); + output: out std_logic_vector(7 downto 0); + rw: in std_logic; + load: in std_logic; + ck: in std_logic; + rst: in std_logic + ); +end component; + +component fifo + port( + data_in: in std_logic_vector(7 downto 0); + data_out: in std_logic_vector(7 downto 0); + ck_in: in std_logic; + ck_out: in std_logic; + f0: out std_logic; + f1: out std_logic; + f2: out std_logic; + f3: out std_logic; + purge: in std_logic + ); +end component; + +component transmitter + port( + data_in: in std_logic_vector(7 downto 0); + ck: in std_logic; + flag: out std_logic; + txout: out std_logic + ); +end component; + +component clockgene + port( + ck_in: in std_logic; + ck_out: in std_logic; + param: in std_logic_vector(1 downto 0) + ); +end component; + +component decoder + generic(adr : integer); + port( + adrbus: in std_logic_vector((adr_w - 1) downto 0); + cs: out std_logic + ); +end component; + + +signal fifoEmpty: std_logic; +signal fifoFull: std_logic; +signal fifoLI1: std_logic; +signal fifoLI0: std_logic; +signal BdR1: std_logic; +signal BdR0: std_logic; +signal purge: std_logic; +signal geneck: std_logic; +signal txck: std_logic; +signal busck: std_logic; +signal adrbus: std_logic_vector((adr_w - 1) downto 0); +signal databus: std_logic_vector(7 downto 0); +signal rw: std_logic; +signal rst: std_logic; +signal txdata: std_logic; +signal txempty: std_logic; +signal csFifo: std_logic; +signal fifockin: std_logic; +signal fifockout: std_logic; + +FIFO1: fifo + port map( + data_in=>databus, + data_out=>txdata, + ck_in=>fifockin, + ck_out=>fifockout + f0=>fifoEmpty, + f1=>fifoLI0, + f2=>fifoLI1, + f3=>fifoFull, + purge=>confreg(3) + ); + +fifockin<=csFifo and not rw and busck; +fifockout<=txempty; -- à vérifier !!! Cette ligne est valable pour + -- txempty=1 quand le tx est vide + +TX1 : transmitter + port map( + data_in=>txdata, + ck=>txck, + flag=>txempty, + txout=>txout, + ); + +CLOCK1 : clockgene + port map( + ck_in=>geneck, + ck_out=>txck, + param=>confreg(1 downto 0) + ); +geneck<=confreg(4) and masterck; -- On/Off et masterck + + +-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) +RCONF : registre + generic map(adr=>adr+1) + port map( + adrbus=>adrbus, + databus=>databus, + input=>(others => '0'), + output=>confreg, + rw=>rw, + load=>'0', + ck=>busck, + rst=>'0' + ); + +-- Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0) +RFLAG : registre + generic map(adr=>adr+2) + port map( + adrbus=>adrbus, + databus=>databus, + input=>flagreg, + output=>open, + rw=>rw, + load=>'1', + ck=>busck, + rst=>'0' + ); + +flagreg(7 downto 3)<=(others => '0'); +flagreg(3)<=txempty; +flagreg(2)<=fifoFull; +flagreg(1)<=fifoLI1; +flagreg(0)<=fifoLI0; + +-- la sortie intout est active si la pile est pleine ET si le bit de conf est +-- activé +intout<=fifoFull and confreg(2); -- IntEn et fifoFull + +DECOD : decoder + generic map(adr=>adr) + port map( + adrbus=>adrbus, + cs=>csFifo + ); +end rtl; + +library ieee; +library ieee.std_logic_1164.all; + +entity txserie is +generic(adr : integer); +constant adr_w : integer :=10; +port( + adrbus: in std_logic_vector((adr_w - 1) downto 0); + databus: inout std_logic_vector(7 downto 0); + rw: in std_logic; + busck: in std_logic; + rst: in std_logic; + masterck: in std_logic; + txout: out std_logic; + intout: out std_logic; + ); +end txserie; + +architecture rtl of txserie is + +component registre + generic(adr : integer); + port( + adrbus: in std_logic_vector((adr_w - 1) downto 0); + databus: inout std_logic_vector(7 downto 0); + input: in std_logic_vector(7 downto 0); + output: out std_logic_vector(7 downto 0); + rw: in std_logic; + load: in std_logic; + ck: in std_logic; + rst: in std_logic + ); +end component; + +component fifo + port( + data_in: in std_logic_vector(7 downto 0); + data_out: in std_logic_vector(7 downto 0); + ck_in: in std_logic; + ck_out: in std_logic; + f0: out std_logic; + f1: out std_logic; + f2: out std_logic; + f3: out std_logic; + purge: in std_logic + ); +end component; + +component transmitter + port( + data_in: in std_logic_vector(7 downto 0); + ck: in std_logic; + flag: out std_logic; + txout: out std_logic + ); +end component; + +component clockgene + port( + ck_in: in std_logic; + ck_out: in std_logic; + param: in std_logic_vector(1 downto 0) + ); +end component; + +component decoder + generic(adr : integer); + port( + adrbus: in std_logic_vector((adr_w - 1) downto 0); + cs: out std_logic + ); +end component; + + +signal fifoEmpty: std_logic; +signal fifoFull: std_logic; +signal fifoLI1: std_logic; +signal fifoLI0: std_logic; +signal BdR1: std_logic; +signal BdR0: std_logic; +signal purge: std_logic; +signal geneck: std_logic; +signal txck: std_logic; +signal busck: std_logic; +signal adrbus: std_logic_vector((adr_w - 1) downto 0); +signal databus: std_logic_vector(7 downto 0); +signal rw: std_logic; +signal rst: std_logic; +signal txdata: std_logic; +signal txempty: std_logic; +signal csFifo: std_logic; +signal fifockin: std_logic; +signal fifockout: std_logic; + +FIFO1: fifo + port map( + data_in=>databus, + data_out=>txdata, + ck_in=>fifockin, + ck_out=>fifockout + f0=>fifoEmpty, + f1=>fifoLI0, + f2=>fifoLI1, + f3=>fifoFull, + purge=>confreg(3) + ); + +fifockin<=csFifo and not rw and busck; +fifockout<=txempty; -- à vérifier !!! Cette ligne est valable pour + -- txempty=1 quand le tx est vide + +TX1 : transmitter + port map( + data_in=>txdata, + ck=>txck, + flag=>txempty, + txout=>txout, + ); + +CLOCK1 : clockgene + port map( + ck_in=>geneck, + ck_out=>txck, + param=>confreg(1 downto 0) + ); +geneck<=confreg(4) and masterck; -- On/Off et masterck + + +-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0) +RCONF : registre + generic map(adr=>adr+1) + port map( + adrbus=>adrbus, + databus=>databus, + input=>(others => '0'), + output=>confreg, + rw=>rw, + load=>'0', + ck=>busck, + rst=>'0' + ); + +-- Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0) +RFLAG : registre + generic map(adr=>adr+2) + port map( + adrbus=>adrbus, + databus=>databus, + input=>flagreg, + output=>open, + rw=>rw, + load=>'1', + ck=>busck, + rst=>'0' + ); + +flagreg(7 downto 3)<=(others => '0'); +flagreg(3)<=txempty; +flagreg(2)<=fifoFull; +flagreg(1)<=fifoLI1; +flagreg(0)<=fifoLI0; + +-- la sortie intout est active si la pile est pleine ET si le bit de conf est +-- activé +intout<=fifoFull and confreg(2); -- IntEn et fifoFull + +DECOD : decoder + generic map(adr=>adr) + port map( + adrbus=>adrbus, + cs=>csFifo + ); +end rtl; + + + + + +architecture test_modele of modele is +begin + process (rst, clk) + begin + if (rst = '1') then + bus_data <= x"00"; + elsif (clk'event and clk = '1') then + if (bus_address = A_REG1) then + bus_data <= x"01"; + else + if (bus_address = A_REG2) then + bus_data <= x"02"; + elsif (bus_address = A_REG3) then + bus_data <= x"03"; + end if; + end if; + end if; + end process; +end test_modele; -- cgit v1.2.3