From aa5af70bfadebbf3f4809d232f3cf692541cac36 Mon Sep 17 00:00:00 2001 From: galmes Date: Mon, 1 Mar 2004 14:40:02 +0000 Subject: Modification des modeles. Nouvelle version de la gestion de l'addressage (avec 1 chip select par registre). --- 2004/n/fpga/src/modele/modele.vhd | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) (limited to '2004/n/fpga/src/modele/modele.vhd') diff --git a/2004/n/fpga/src/modele/modele.vhd b/2004/n/fpga/src/modele/modele.vhd index c4e9f38..0e11e62 100644 --- a/2004/n/fpga/src/modele/modele.vhd +++ b/2004/n/fpga/src/modele/modele.vhd @@ -11,19 +11,15 @@ use ieee.std_logic_unsigned.all; use work.nono_const.all; entity modele is - generic ( - -- adresses des différents registres du module. - A_REG1 : T_ADDRESS; - A_REG2 : T_ADDRESS; - A_REG3 : T_ADDRESS - -- si autre choses à déclarer... - ); port ( rst : in std_logic; clk : in std_logic; rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA; - bus_address : in T_ADDRESS + -- chaque registre se voit administrer un chip select. + cs_reg0 : in std_logic; -- chip select + cs_reg1 : in std_logic; + cs_reg2 : in std_logic ); end entity; @@ -34,12 +30,12 @@ begin if (rst = '1') then bus_data <= x"00"; elsif (clk'event and clk = '1') then - if (bus_address = A_REG1) then + if (cs_reg0 = '1') then bus_data <= x"01"; else - if (bus_address = A_REG2) then + if (cs_reg1 = '1') then bus_data <= x"02"; - elsif (bus_address = A_REG3) then + elsif (cs_reg2 = '1') then bus_data <= x"03"; end if; end if; -- cgit v1.2.3