From 4ccfe616f851d0ea39d6fe5ac0d18a37e66af74b Mon Sep 17 00:00:00 2001 From: galmes Date: Mon, 23 Feb 2004 16:19:44 +0000 Subject: Améliorations de modele --- 2004/n/fpga/src/modele/bch_modele.vhd | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) (limited to '2004/n/fpga/src/modele/bch_modele.vhd') diff --git a/2004/n/fpga/src/modele/bch_modele.vhd b/2004/n/fpga/src/modele/bch_modele.vhd index 18bc9a7..eb062c5 100644 --- a/2004/n/fpga/src/modele/bch_modele.vhd +++ b/2004/n/fpga/src/modele/bch_modele.vhd @@ -19,17 +19,17 @@ architecture sim1 of bch_modele is component modele generic ( -- adresses des différents registres du module. - A_REG1 : T_ADDRESS := A_REG_IO_DIRECTION; - A_REG2 : T_ADDRESS := A_REG_IO_DATA; - A_REG3 : T_ADDRESS := A_REG_IO_INTERRUPT_MASK + A_REG1 : T_ADDRESS; + A_REG2 : T_ADDRESS; + A_REG3 : T_ADDRESS -- si autre choses à déclarer... ); port ( rst : in std_logic; clk : in std_logic; rw : in std_logic; -- read / write - bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0); - bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0) + bus_data : inout T_DATA; + bus_address : in T_ADDRESS ); end component; @@ -37,16 +37,23 @@ architecture sim1 of bch_modele is signal rst : std_logic; signal clk : std_logic := '0'; signal rw : std_logic; -- read / write - signal bus_data : unsigned ((NB_BIT_DATA - 1) downto 0); - signal bus_address : unsigned ((NB_BIT_ADDRESS - 1) downto 0); + signal bus_data : T_DATA; + signal bus_address : T_ADDRESS; begin - U1 : modele port map ( - rst => rst, - clk => clk, - rw => rw, - bus_data => bus_data, - bus_address => bus_address + U1 : modele + generic map ( + -- Définition des addresses. + A_REG1 => A_REG_IO_DIRECTION, + A_REG2 => A_REG_IO_DATA, + A_REG3 => A_REG_IO_INTERRUPT_MASK + ) + port map ( + rst => rst, + clk => clk, + rw => rw, + bus_data => bus_data, + bus_address => bus_address ); rst <= '1', '0' after CK_PERIOD; -- cgit v1.2.3