From 7ac4ade1a941c90d23891c5332f9f9b869107977 Mon Sep 17 00:00:00 2001 From: galmes Date: Sat, 28 Feb 2004 22:04:03 +0000 Subject: Suppression des registres ds le rep gpio et déplacé ds le rep registre. --- 2004/n/fpga/src/gpio/bch_reg_rw.vhd | 68 ------------------------------------- 2004/n/fpga/src/gpio/reg_rw.vhd | 53 ----------------------------- 2 files changed, 121 deletions(-) delete mode 100644 2004/n/fpga/src/gpio/bch_reg_rw.vhd delete mode 100644 2004/n/fpga/src/gpio/reg_rw.vhd (limited to '2004/n/fpga/src/gpio') diff --git a/2004/n/fpga/src/gpio/bch_reg_rw.vhd b/2004/n/fpga/src/gpio/bch_reg_rw.vhd deleted file mode 100644 index 07b7cc2..0000000 --- a/2004/n/fpga/src/gpio/bch_reg_rw.vhd +++ /dev/null @@ -1,68 +0,0 @@ --- bch_reg_rw.vhd --- Eurobot 2004 : APB Team --- Auteur : Pierre-André Galmes --- Test de reg_rw. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -use work.isa_const.all; -use work.nono_const.all; - - -entity bch_reg_rw is -end bch_reg_rw; - -architecture sim1 of bch_reg_rw is - - component reg_rw - port ( - clk : in std_logic; - rst : in std_logic; - rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE) - enable : in std_logic; - data : inout T_DATA; - data_out : out T_DATA - ); - end component; - - -- définiton des signaux - signal clk : std_logic := '0'; - signal rst : std_logic; - signal rw : std_logic; -- read / write - signal enable : std_logic; - signal data : T_DATA; - signal data_out : T_DATA; - -begin - U1 : reg_rw port map ( - clk => clk, - rst => rst, - rw => rw, - enable => enable, - data => data, - data_out => data_out - ); - - clk <= not clk after CK_PERIOD/2; - rst <= '1', '0' after CK_PERIOD; - enable <= '0', - '1' after 2*CK_PERIOD, - '0' after 3*CK_PERIOD, - '1' after 5*CK_PERIOD, - '0' after 6*CK_PERIOD; - rw <= '1', '0' after 3*CK_PERIOD; - data <= x"01", - x"02" after 3*CK_PERIOD, - "ZZZZZZZZ" after 5*CK_PERIOD; - --x"03" after 5*CK_PERIOD; -end sim1; - -configuration cf1_bch_reg_rw of bch_reg_rw is - for sim1 - for all : reg_rw use entity work.reg_rw(RTL); end for; - end for; -end cf1_bch_reg_rw; - diff --git a/2004/n/fpga/src/gpio/reg_rw.vhd b/2004/n/fpga/src/gpio/reg_rw.vhd deleted file mode 100644 index 1c81139..0000000 --- a/2004/n/fpga/src/gpio/reg_rw.vhd +++ /dev/null @@ -1,53 +0,0 @@ --- reg_rw.vhd --- Eurobot 2004 : APB Team --- Auteur : Pierre-André Galmes --- Registre dont la valeur est accessible en lecture. - --- Principe : --- Si (write et enable) alors sauvegarde entrée et copie entrée sur sortie. --- Si (read et enable) alors copie dernière valeur sauvegardée sur entrée. --- Si (pas enable) alors copie dernière valeur sauvegardée sur sortie. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -use work.isa_const.all; -use work.nono_const.all; - - -entity reg_rw is - port ( - clk : in std_logic; - rst : in std_logic; - rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE) - enable : in std_logic; - data : inout T_DATA; - data_out : out T_DATA -- data courant - ); -end entity; - -architecture RTL of reg_rw is - -- signal interne - signal REG : T_DATA; -begin - -- partie séquentielle. - process (rst, clk) - begin - -- reset - if (rst = '1') then - REG <= (others => '0'); - -- écriture des données. - elsif (clk'event and clk = '1') then - if (enable = '1' and rw = ISA_WRITE) then - REG <= data; - end if; - end if; - end process; - - -- partie combinatoire. - data <= REG when (enable = '1' and rw = ISA_READ) else (others => 'Z'); - data_out <= REG; - -end RTL; -- cgit v1.2.3