From 3a46e687fadd28f93b3a67063e535615770a966d Mon Sep 17 00:00:00 2001 From: galmes Date: Tue, 24 Feb 2004 21:30:40 +0000 Subject: Ajout de plein de fichier pour faire les gpio --- 2004/n/fpga/src/gpio/bch_gpio_direction.vhd | 52 ++++++++++++++++++++++ 2004/n/fpga/src/gpio/bch_gpio_it_detect.vhd | 61 ++++++++++++++++++++++++++ 2004/n/fpga/src/gpio/bch_reg_io.vhd | 68 ----------------------------- 2004/n/fpga/src/gpio/bch_reg_ioz.vhd | 67 ---------------------------- 2004/n/fpga/src/gpio/bch_reg_rw.vhd | 22 ++++++---- 2004/n/fpga/src/gpio/bch_tristate.vhd | 56 ++++++++++++++++++++++++ 2004/n/fpga/src/gpio/gpio_direction.vhd | 40 +++++++++++++++++ 2004/n/fpga/src/gpio/gpio_it_detect.vhd | 55 +++++++++++++++++++++++ 2004/n/fpga/src/gpio/reg_io.vhd | 56 ------------------------ 2004/n/fpga/src/gpio/reg_ioz.vhd | 54 ----------------------- 2004/n/fpga/src/gpio/reg_rw.vhd | 35 ++++++++------- 2004/n/fpga/src/gpio/tristate.vhd | 31 +++++++++++++ 12 files changed, 325 insertions(+), 272 deletions(-) create mode 100644 2004/n/fpga/src/gpio/bch_gpio_direction.vhd create mode 100644 2004/n/fpga/src/gpio/bch_gpio_it_detect.vhd delete mode 100644 2004/n/fpga/src/gpio/bch_reg_io.vhd delete mode 100644 2004/n/fpga/src/gpio/bch_reg_ioz.vhd create mode 100644 2004/n/fpga/src/gpio/bch_tristate.vhd create mode 100644 2004/n/fpga/src/gpio/gpio_direction.vhd create mode 100644 2004/n/fpga/src/gpio/gpio_it_detect.vhd delete mode 100644 2004/n/fpga/src/gpio/reg_io.vhd delete mode 100644 2004/n/fpga/src/gpio/reg_ioz.vhd create mode 100644 2004/n/fpga/src/gpio/tristate.vhd (limited to '2004/n/fpga/src/gpio') diff --git a/2004/n/fpga/src/gpio/bch_gpio_direction.vhd b/2004/n/fpga/src/gpio/bch_gpio_direction.vhd new file mode 100644 index 0000000..1b6f792 --- /dev/null +++ b/2004/n/fpga/src/gpio/bch_gpio_direction.vhd @@ -0,0 +1,52 @@ +-- bch_gpio_direction.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Test de gpio_direction. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity bch_gpio_direction is +end bch_gpio_direction; + +architecture sim1 of bch_gpio_direction is + + component gpio_direction + port ( + direction_mask : in T_DATA; + data_in : in T_DATA; + data_out : out T_DATA + ); + end component; + + -- définiton des signaux + signal direction_mask : T_DATA; + signal data_in : T_DATA; + signal data_out : T_DATA; + +begin + U1 : gpio_direction port map ( + direction_mask => direction_mask, + data_in => data_in, + data_out => data_out + ); + + direction_mask <= x"04"; + data_in <= x"01", + x"02" after 3*CK_PERIOD, + x"07" after 5*CK_PERIOD; + --x"03" after 5*CK_PERIOD; +end sim1; + +configuration cf1_bch_gpio_direction of bch_gpio_direction is + for sim1 + for all : gpio_direction use entity work.gpio_direction(RTL); end for; + end for; +end cf1_bch_gpio_direction; + diff --git a/2004/n/fpga/src/gpio/bch_gpio_it_detect.vhd b/2004/n/fpga/src/gpio/bch_gpio_it_detect.vhd new file mode 100644 index 0000000..2e7162c --- /dev/null +++ b/2004/n/fpga/src/gpio/bch_gpio_it_detect.vhd @@ -0,0 +1,61 @@ +-- bch_gpio_it_detect.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Test de gpio_it_detect. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity bch_gpio_it_detect is +end bch_gpio_it_detect; + +architecture sim1 of bch_gpio_it_detect is + + component gpio_it_detect + port ( + clk : in std_logic; + rst : in std_logic; + data_in : in T_DATA; + it_mask : in T_DATA; + it_detected : out std_logic + ); + end component; + + -- définiton des signaux + signal clk : std_logic := '0'; + signal rst : std_logic; + signal data_in : T_DATA; + signal it_mask : T_DATA; + signal it_detected : std_logic; + +begin + U1 : gpio_it_detect port map ( + clk => clk, + rst => rst, + data_in => data_in, + it_mask => it_mask, + it_detected => it_detected + ); + + clk <= not clk after CK_PERIOD/2; + rst <= '1', '0' after CK_PERIOD; + data_in <= x"02", + x"08" after 3*CK_PERIOD, + x"01" after 5*CK_PERIOD; + --x"03" after 5*CK_PERIOD; + it_mask <= x"02", + x"01" after 3*CK_PERIOD; +end sim1; + +configuration cf1_bch_gpio_it_detect of bch_gpio_it_detect is + for sim1 + for all : gpio_it_detect use entity work.gpio_it_detect(BEHAV); end for; + end for; +end cf1_bch_gpio_it_detect; + diff --git a/2004/n/fpga/src/gpio/bch_reg_io.vhd b/2004/n/fpga/src/gpio/bch_reg_io.vhd deleted file mode 100644 index a404427..0000000 --- a/2004/n/fpga/src/gpio/bch_reg_io.vhd +++ /dev/null @@ -1,68 +0,0 @@ --- bch_reg_io.vhd --- Eurobot 2004 : APB Team --- Auteur : Pierre-André Galmes --- Test de reg_io. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -use work.isa_const.all; -use work.nono_const.all; - - -entity bch_reg_io is -end bch_reg_io; - -architecture sim1 of bch_reg_io is - - component reg_io - port ( - rst : in std_logic; - rw : in std_logic; - enable : in std_logic; - data_f_in : inout T_DATA; -- forward in = entrée dans le sens direct. - data_out : out T_DATA; - data_b_in : in T_DATA -- backward in = entrée pour la lecture - ); - end component; - - -- définiton des signaux - signal rst : std_logic; - signal rw : std_logic; -- read / write - signal enable : std_logic; - signal data_f_in : T_DATA; - signal data_out : T_DATA; - signal data_b_in : T_DATA; - -begin - U1 : reg_io port map ( - rst => rst, - rw => rw, - enable => enable, - data_f_in => data_f_in, - data_out => data_out, - data_b_in => data_b_in - ); - - rst <= '1', '0' after CK_PERIOD; - enable <= '0', - '1' after 2*CK_PERIOD, - '0' after 3*CK_PERIOD, - '1' after 5*CK_PERIOD, - '0' after 6*CK_PERIOD; - rw <= '1', '0' after 3*CK_PERIOD; - data_f_in <= x"01", - x"02" after 3*CK_PERIOD, - "ZZZZZZZZ" after 5*CK_PERIOD; - --x"03" after 5*CK_PERIOD; - data_b_in <= x"07"; -end sim1; - -configuration cf1_bch_reg_io of bch_reg_io is - for sim1 - for all : reg_io use entity work.reg_io(BEHAV); end for; - end for; -end cf1_bch_reg_io; - diff --git a/2004/n/fpga/src/gpio/bch_reg_ioz.vhd b/2004/n/fpga/src/gpio/bch_reg_ioz.vhd deleted file mode 100644 index 280bb63..0000000 --- a/2004/n/fpga/src/gpio/bch_reg_ioz.vhd +++ /dev/null @@ -1,67 +0,0 @@ --- bch_reg_ioz.vhd --- Eurobot 2004 : APB Team --- Auteur : Pierre-André Galmes --- Test de reg_rw. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -use work.isa_const.all; -use work.nono_const.all; - - -entity bch_reg_ioz is -end bch_reg_ioz; - -architecture sim1 of bch_reg_ioz is - - component reg_ioz - port ( - rst : in std_logic; - rw : in std_logic; - enable : in std_logic; - data_in : inout T_DATA; - data_out : inout T_DATA - ); - end component; - - -- définiton des signaux - signal rst : std_logic; - signal rw : std_logic; -- read / write - signal enable : std_logic; - signal data_in : T_DATA; - signal data_out : T_DATA; - -begin - U1 : reg_ioz port map ( - rst => rst, - rw => rw, - enable => enable, - data_in => data_in, - data_out => data_out - ); - - rst <= '1', '0' after CK_PERIOD; - enable <= '0', - '1' after 2*CK_PERIOD, - '0' after 3*CK_PERIOD, - '1' after 5*CK_PERIOD, - '0' after 6*CK_PERIOD; - rw <= '1', '0' after 3*CK_PERIOD; - data_in <= x"01", - x"02" after 3*CK_PERIOD, - "ZZZZZZZZ" after 5*CK_PERIOD; - --x"03" after 5*CK_PERIOD; - data_out <= "ZZZZZZZZ", - x"07" after 5*CK_PERIOD, - "ZZZZZZZZ" after 6*CK_PERIOD; -end sim1; - -configuration cf1_bch_reg_ioz of bch_reg_ioz is - for sim1 - for all : reg_ioz use entity work.reg_ioz(BEHAV); end for; - end for; -end cf1_bch_reg_ioz; - diff --git a/2004/n/fpga/src/gpio/bch_reg_rw.vhd b/2004/n/fpga/src/gpio/bch_reg_rw.vhd index 7d4a41a..07b7cc2 100644 --- a/2004/n/fpga/src/gpio/bch_reg_rw.vhd +++ b/2004/n/fpga/src/gpio/bch_reg_rw.vhd @@ -19,30 +19,34 @@ architecture sim1 of bch_reg_rw is component reg_rw port ( - rst : in std_logic; - rw : in std_logic; - enable : in std_logic; - data_in : inout T_DATA; - data_out : out T_DATA + clk : in std_logic; + rst : in std_logic; + rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE) + enable : in std_logic; + data : inout T_DATA; + data_out : out T_DATA ); end component; -- définiton des signaux + signal clk : std_logic := '0'; signal rst : std_logic; signal rw : std_logic; -- read / write signal enable : std_logic; - signal data_in : T_DATA; + signal data : T_DATA; signal data_out : T_DATA; begin U1 : reg_rw port map ( + clk => clk, rst => rst, rw => rw, enable => enable, - data_in => data_in, + data => data, data_out => data_out ); + clk <= not clk after CK_PERIOD/2; rst <= '1', '0' after CK_PERIOD; enable <= '0', '1' after 2*CK_PERIOD, @@ -50,7 +54,7 @@ begin '1' after 5*CK_PERIOD, '0' after 6*CK_PERIOD; rw <= '1', '0' after 3*CK_PERIOD; - data_in <= x"01", + data <= x"01", x"02" after 3*CK_PERIOD, "ZZZZZZZZ" after 5*CK_PERIOD; --x"03" after 5*CK_PERIOD; @@ -58,7 +62,7 @@ end sim1; configuration cf1_bch_reg_rw of bch_reg_rw is for sim1 - for all : reg_rw use entity work.reg_rw(BEHAV); end for; + for all : reg_rw use entity work.reg_rw(RTL); end for; end for; end cf1_bch_reg_rw; diff --git a/2004/n/fpga/src/gpio/bch_tristate.vhd b/2004/n/fpga/src/gpio/bch_tristate.vhd new file mode 100644 index 0000000..a31c03e --- /dev/null +++ b/2004/n/fpga/src/gpio/bch_tristate.vhd @@ -0,0 +1,56 @@ +-- bch_tristate.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Test de tristate. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity bch_tristate is +end bch_tristate; + +architecture sim1 of bch_tristate is + + component tristate + port ( + enable : in std_logic; + data_in : in T_DATA; + data_out : out T_DATA + ); + end component; + + -- définiton des signaux + signal enable : std_logic; + signal data_in : T_DATA; + signal data_out : T_DATA; + +begin + U1 : tristate port map ( + enable => enable, + data_in => data_in, + data_out => data_out + ); + + enable <= '0', + '1' after 2*CK_PERIOD, + '0' after 3*CK_PERIOD, + '1' after 5*CK_PERIOD, + '0' after 6*CK_PERIOD; + data_in <= x"01", + x"02" after 3*CK_PERIOD, + x"06" after 5*CK_PERIOD; + --x"03" after 5*CK_PERIOD; +end sim1; + +configuration cf1_bch_tristate of bch_tristate is + for sim1 + for all : tristate use entity work.tristate(RTL); end for; + end for; +end cf1_bch_tristate; + diff --git a/2004/n/fpga/src/gpio/gpio_direction.vhd b/2004/n/fpga/src/gpio/gpio_direction.vhd new file mode 100644 index 0000000..1daf3e2 --- /dev/null +++ b/2004/n/fpga/src/gpio/gpio_direction.vhd @@ -0,0 +1,40 @@ +-- gpio_direction.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Registre dont la valeur est accessible en lecture. + +-- Principe : +-- Bloc trois états (three-state) qui met les sorties en hautes impédance si +-- elle ne sont pas "enabled". + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity gpio_direction is + port ( + direction_mask : in T_DATA; + data_in : in T_DATA; + data_out : out T_DATA + ); +end entity; + +architecture RTL of gpio_direction is + -- constantes + constant DIR_OUT : std_logic := '1'; -- valeur de masque pour sortie +begin + -- partie combinatoire. + data_out(7) <= data_in(7) when (direction_mask(7) = DIR_OUT) else 'Z'; + data_out(6) <= data_in(6) when (direction_mask(6) = DIR_OUT) else 'Z'; + data_out(5) <= data_in(5) when (direction_mask(5) = DIR_OUT) else 'Z'; + data_out(4) <= data_in(4) when (direction_mask(4) = DIR_OUT) else 'Z'; + data_out(3) <= data_in(3) when (direction_mask(3) = DIR_OUT) else 'Z'; + data_out(2) <= data_in(2) when (direction_mask(2) = DIR_OUT) else 'Z'; + data_out(1) <= data_in(1) when (direction_mask(1) = DIR_OUT) else 'Z'; + data_out(0) <= data_in(0) when (direction_mask(0) = DIR_OUT) else 'Z'; +end RTL; diff --git a/2004/n/fpga/src/gpio/gpio_it_detect.vhd b/2004/n/fpga/src/gpio/gpio_it_detect.vhd new file mode 100644 index 0000000..1f1d69b --- /dev/null +++ b/2004/n/fpga/src/gpio/gpio_it_detect.vhd @@ -0,0 +1,55 @@ +-- gpio_it_detect.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- detecteur d'interruption avec masque. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity gpio_it_detect is + port ( + clk : in std_logic; + rst : in std_logic; + data_in : in T_DATA; + it_mask : in T_DATA; + it_detected : out std_logic + ); +end entity; + +architecture RTL of gpio_it_detect is + -- Constantes + constant IT_ENABLE : std_logic := '1'; + -- Signal interne + signal state_p : T_DATA; -- etat passe + +begin + -- process séquentiel + process (rst, clk) + begin + if (rst = '1') then + state_p <= (others => '0'); + it_detected <= '0'; + elsif (clk'event and clk = '1') then + -- TODO : Ajouter la synchronisation ??????? Pas besoin, non ????? + + if (data_in /= state_p) then + -- bit ayant droit de générer une interruption ? + if (((data_in xor state_p) and it_mask) /= x"00") then + -- on émet le signal d'interruption. + it_detected <= '1'; + end if; + else + it_detected <= '0'; + state_p <= data_in; + end if; + end if; + end process; + +end RTL; diff --git a/2004/n/fpga/src/gpio/reg_io.vhd b/2004/n/fpga/src/gpio/reg_io.vhd deleted file mode 100644 index 43416e4..0000000 --- a/2004/n/fpga/src/gpio/reg_io.vhd +++ /dev/null @@ -1,56 +0,0 @@ --- reg_io.vhd --- Eurobot 2004 : APB Team --- Auteur : Pierre-André Galmes --- Registre dont on peut lire les valeurs sur data_out. --- RQ : Ce type de registre a un inconvénient : la haute impédance ! - --- TODO : Principe : --- Si (write et enable) alors sauvegarde l'entrée data_f_in et copie --- entrée data_f_in sur sortie. --- Si (read et enable) alors copie entrée data_b_in sur entrée data_f_in. --- Si (pas enable) alors copie dernière valeur sauvegardée sur sortie. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -use work.isa_const.all; -use work.nono_const.all; - - -entity reg_io is - port ( - rst : in std_logic; - rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE) - enable : in std_logic; - data_f_in : inout T_DATA; -- forward in = entrée dans le sens direct. - data_out : out T_DATA; - data_b_in : in T_DATA -- backward in = entrée pour la lecture - ); -end entity; - -architecture BEHAV of reg_io is - -- signal interne - signal REG : T_DATA; -begin - -- process - process (rst, rw, enable, data_f_in, data_b_in) - begin - if (rst = '1') then - REG <= x"00"; - else - if (enable = '1') then - if (rw = ISA_WRITE) then - REG <= data_f_in; - elsif (rw = ISA_READ) then - data_f_in <= data_b_in; - end if; - else - data_f_in <= "ZZZZZZZZ"; - end if; - end if; - end process; - - data_out <= REG; -end BEHAV; diff --git a/2004/n/fpga/src/gpio/reg_ioz.vhd b/2004/n/fpga/src/gpio/reg_ioz.vhd deleted file mode 100644 index 22f1730..0000000 --- a/2004/n/fpga/src/gpio/reg_ioz.vhd +++ /dev/null @@ -1,54 +0,0 @@ --- reg_ioz.vhd --- Eurobot 2004 : APB Team --- Auteur : Pierre-André Galmes --- Registre dont on peut lire les valeurs sur data_out. --- RQ : Ce type de registre a un inconvénient : la haute impédance ! - --- Principe : --- Si (write et enable) alors sauvegarde entrée et copie entrée sur sortie. --- Si (read et enable) alors copie sortie sur entrée. --- Si (pas enable) alors copie dernière valeur sauvegardée sur sortie. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -use work.isa_const.all; -use work.nono_const.all; - - -entity reg_ioz is - port ( - rst : in std_logic; - rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE) - enable : in std_logic; - data_in : inout T_DATA; - data_out : inout T_DATA - ); -end entity; - -architecture BEHAV of reg_ioz is - -- signal interne - signal REG : T_DATA; -begin - -- process - process (rst, rw, enable, data_in) - begin - if (rst = '1') then - REG <= x"00"; - else - if (enable = '1') then - if (rw = ISA_WRITE) then - REG <= data_in; - elsif (rw = ISA_READ) then - data_in <= data_out; - end if; - else - data_in <= "ZZZZZZZZ"; - end if; - end if; - end process; - - data_out <= "ZZZZZZZZ" when (rw = ISA_READ and enable = '1') else REG; -end BEHAV; diff --git a/2004/n/fpga/src/gpio/reg_rw.vhd b/2004/n/fpga/src/gpio/reg_rw.vhd index b93121f..1c81139 100644 --- a/2004/n/fpga/src/gpio/reg_rw.vhd +++ b/2004/n/fpga/src/gpio/reg_rw.vhd @@ -19,36 +19,35 @@ use work.nono_const.all; entity reg_rw is port ( + clk : in std_logic; rst : in std_logic; rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE) enable : in std_logic; - data_in : inout T_DATA; - data_out : out T_DATA + data : inout T_DATA; + data_out : out T_DATA -- data courant ); end entity; -architecture BEHAV of reg_rw is +architecture RTL of reg_rw is -- signal interne signal REG : T_DATA; begin - -- process d'écriture. - process (rst, rw, enable, data_in) + -- partie séquentielle. + process (rst, clk) begin + -- reset if (rst = '1') then - REG <= x"00"; - else - if (enable = '1') then - if (rw = ISA_WRITE) then - REG <= data_in; - elsif (rw = ISA_READ) then - data_in <= REG; - end if; - else - data_in <= "ZZZZZZZZ"; + REG <= (others => '0'); + -- écriture des données. + elsif (clk'event and clk = '1') then + if (enable = '1' and rw = ISA_WRITE) then + REG <= data; end if; end if; end process; - - -- + + -- partie combinatoire. + data <= REG when (enable = '1' and rw = ISA_READ) else (others => 'Z'); data_out <= REG; -end BEHAV; + +end RTL; diff --git a/2004/n/fpga/src/gpio/tristate.vhd b/2004/n/fpga/src/gpio/tristate.vhd new file mode 100644 index 0000000..07e440e --- /dev/null +++ b/2004/n/fpga/src/gpio/tristate.vhd @@ -0,0 +1,31 @@ +-- tristate.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Registre dont la valeur est accessible en lecture. + +-- Principe : +-- Bloc trois états (three-state) qui met les sorties en hautes impédance si +-- elle ne sont pas "enabled". + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity tristate is + port ( + enable : in std_logic; + data_in : in T_DATA; + data_out : out T_DATA + ); +end entity; + +architecture RTL of tristate is +begin + -- partie combinatoire. + data_out <= data_in when (enable = '1') else (others => 'Z'); +end RTL; -- cgit v1.2.3