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-rw-r--r--2004/n/fpga/src/pwm/pwm_generator.vhd4
-rw-r--r--2004/n/fpga/src/pwm/pwm_nono.vhd4
2 files changed, 4 insertions, 4 deletions
diff --git a/2004/n/fpga/src/pwm/pwm_generator.vhd b/2004/n/fpga/src/pwm/pwm_generator.vhd
index f14c1e3..7b8f012 100644
--- a/2004/n/fpga/src/pwm/pwm_generator.vhd
+++ b/2004/n/fpga/src/pwm/pwm_generator.vhd
@@ -16,7 +16,7 @@ use work.pwm_const.all;
entity pwm_generator is
port (
rst : in std_logic;
- clk : in std_logic;
+ clk : in std_logic; -- clk 200ns
pwm_in : in T_DOUBLE_OCTET;
pwm_out : out std_logic
);
@@ -40,7 +40,7 @@ begin
pwm_out <= '1';
else
pwm_out <= '0';
- if (compt = PWM_NB_CYCLE_20MS) then
+ if (compt = PWM_NB_CYCLE_PERIODE) then
compt <= x"0000";
reg <= pwm_in;
end if;
diff --git a/2004/n/fpga/src/pwm/pwm_nono.vhd b/2004/n/fpga/src/pwm/pwm_nono.vhd
index 992588c..f136072 100644
--- a/2004/n/fpga/src/pwm/pwm_nono.vhd
+++ b/2004/n/fpga/src/pwm/pwm_nono.vhd
@@ -39,7 +39,7 @@ port (
end component;
-- Générateur d'horloge à 1us.
-component clk1us is
+component clk200ns is
port(
RST : in std_logic;
CLK : in std_logic; --40MHz
@@ -87,7 +87,7 @@ port map(
);
--
-Clock_div : clk1us
+Clock_div : clk200ns
port map(
rst,
clk,