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-rw-r--r--2004/n/fpga/src/decodisa/bch_decodisa.vhd10
-rw-r--r--2004/n/fpga/src/fpga/fpga-test.vhd31
-rw-r--r--2004/n/fpga/src/fpga/fpga.npl3
3 files changed, 22 insertions, 22 deletions
diff --git a/2004/n/fpga/src/decodisa/bch_decodisa.vhd b/2004/n/fpga/src/decodisa/bch_decodisa.vhd
index 5457481..91a6bc9 100644
--- a/2004/n/fpga/src/decodisa/bch_decodisa.vhd
+++ b/2004/n/fpga/src/decodisa/bch_decodisa.vhd
@@ -32,6 +32,8 @@ ARCHITECTURE behavior OF decodisa_bch IS
SIGNAL adr_bus : std_logic_vector(23 downto 0):=(others => '0');
SIGNAL AEN : std_logic:='0';
+ SIGNAL IORosc : std_logic:='0';
+ SIGNAL IOWosc : std_logic:='0';
SIGNAL IOR : std_logic:='0';
SIGNAL IOW : std_logic:='0';
SIGNAL cs : std_logic_vector(255 downto 0);
@@ -51,9 +53,11 @@ BEGIN
);
adr_bus <= conv_std_logic_vector(unsigned(adr_bus) + 1 , 24) after 120 ns;
-aen<= not aen after 1500 ns;
-ior<= not ior after 70 ns;
-iow<= not iow after 50 ns;
+aen<= not aen after 13000 ns;
+iorosc<= not iorosc after 7000 ns;
+iowosc<= not iowosc after 5000 ns;
+ior<=not(iorosc and not aen);
+iow<=not(iowosc and not aen);
END;
diff --git a/2004/n/fpga/src/fpga/fpga-test.vhd b/2004/n/fpga/src/fpga/fpga-test.vhd
index 4459bef..b7ff084 100644
--- a/2004/n/fpga/src/fpga/fpga-test.vhd
+++ b/2004/n/fpga/src/fpga/fpga-test.vhd
@@ -44,16 +44,16 @@ ARCHITECTURE behavior OF bch_fpga IS
SIGNAL rst : std_logic:='0';
SIGNAL clk_speed : std_logic:='0';
SIGNAL clk_ref : std_logic:='0';
- SIGNAL AEN : std_logic;
- SIGNAL IOR : std_logic;
- SIGNAL IOW : std_logic;
+ SIGNAL AEN : std_logic:='1';
+ SIGNAL IOR : std_logic:='1';
+ SIGNAL IOW : std_logic:='1';
SIGNAL bus_adr : std_logic_vector(23 downto 0);
SIGNAL bus_data : std_logic_vector(7 downto 0);
- SIGNAL irq : std_logic;
- SIGNAL irqrxFIFO,irqrxRX,irqrxERR,irqtx : std_logic;
+ SIGNAL irq : std_logic:='0';
+ SIGNAL irqrxFIFO,irqrxRX,irqrxERR,irqtx : std_logic:='0';
SIGNAL rxin1 : std_logic:='0';
- SIGNAL txout1 : std_logic;
+ SIGNAL txout1 : std_logic:='0';
signal data : integer;
signal data_received : std_logic_vector(7 downto 0);
@@ -106,7 +106,7 @@ check:process
bus_adr<=adr;
WAIT FOR 20 ns;
IOR<='0';
- WAIT FOR 60 ns;
+ WAIT FOR 150 ns;
data_received <= bus_data;
IOR<='1';
WAIT FOR 20 ns;
@@ -126,7 +126,7 @@ check:process
bus_data <= conv_std_logic_vector(data,8);
WAIT FOR 20 ns;
IOW<='0';
- WAIT FOR 60 ns;
+ WAIT FOR 100 ns;
IOW<='1';
WAIT FOR 20 ns;
bus_data <= "ZZZZZZZZ";
@@ -161,30 +161,29 @@ check:process
data<=255;
write_bus(258);
read_bus(258);
- wait for 100 ns;
+ wait for 500 ns;
-- configuration du TX
data<=119;
write_bus(261);
read_bus(261);
- wait for 5 us;
+ wait for 1 us;
-- transmission par le TX
data<=177;
write_bus(260);
- read_bus(260);
-
wait for 100 ns;
+-- transmission par le TX
+ data<=52;
+ write_bus(260);
+ wait for 100 ns;
-- transmission par le TX
data<=22;
write_bus(260);
- read_bus(260);
-
-
- wait for 100 ns;
wait for 100 ns;
+ wait for 400 ns;
end process;
END behavior;
diff --git a/2004/n/fpga/src/fpga/fpga.npl b/2004/n/fpga/src/fpga/fpga.npl
index 6bc4e79..6fb7a07 100644
--- a/2004/n/fpga/src/fpga/fpga.npl
+++ b/2004/n/fpga/src/fpga/fpga.npl
@@ -38,9 +38,6 @@ STIMULUS ..\portserie\portserie\bch_txserie.vhd
SOURCE ..\portserie\portserie\txserie.vhd
SOURCE ..\portserie\uart\txmit.vhd
[STATUS-ALL]
-decodisa.ngcFile=WARNINGS,1080659193
-fpga.ngcFile=WARNINGS,1082194051
-fpga.ngdFile=WARNINGS,1082194062
txmit.ngdFile=WARNINGS,1082195280
txserie.ngcFile=WARNINGS,1082194924
txserie.ngdFile=WARNINGS,1082194930