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-rw-r--r--2004/n/fpga/src/registre/registre.vhd3
1 files changed, 2 insertions, 1 deletions
diff --git a/2004/n/fpga/src/registre/registre.vhd b/2004/n/fpga/src/registre/registre.vhd
index 94be6c2..e0445fb 100644
--- a/2004/n/fpga/src/registre/registre.vhd
+++ b/2004/n/fpga/src/registre/registre.vhd
@@ -45,7 +45,7 @@ end entity;
architecture rtl of regIO is
-signal REG : T_DATA :=(others => '1');
+signal REG : T_DATA :=(others => '0');
begin
p_w:process(ck,load,input,rst)
@@ -104,3 +104,4 @@ end rtl;
+