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Diffstat (limited to '2004/n/fpga/src/registre/registre.vhd')
-rw-r--r--2004/n/fpga/src/registre/registre.vhd15
1 files changed, 8 insertions, 7 deletions
diff --git a/2004/n/fpga/src/registre/registre.vhd b/2004/n/fpga/src/registre/registre.vhd
index 23a0079..94be6c2 100644
--- a/2004/n/fpga/src/registre/registre.vhd
+++ b/2004/n/fpga/src/registre/registre.vhd
@@ -30,12 +30,12 @@ use ieee.std_logic_unsigned.all;
use work.nono_const.all;
entity regIO is
- generic(adr : unsigned);
+ generic(adr : T_ADDRESS);
port(
- bus_data: inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
- input: in unsigned(7 downto 0);
- output: out unsigned(7 downto 0);
+ bus_data: inout T_DATA;
+ bus_address: in T_ADDRESS;
+ input: in T_DATA;
+ output: out T_DATA;
rw: in std_logic;
load: in std_logic;
ck: in std_logic;
@@ -45,7 +45,7 @@ end entity;
architecture rtl of regIO is
-signal REG : unsigned((NB_BIT_DATA - 1) downto 0):=(others => '1');
+signal REG : T_DATA :=(others => '1');
begin
p_w:process(ck,load,input,rst)
@@ -67,7 +67,7 @@ begin
end if;
-- chargement : prioritaire sur l'écriture via le bus
- if(load='1') then
+ if(load='1' and not(ck='1' and rw='1')) then
REG<=input;
end if;
@@ -103,3 +103,4 @@ end rtl;
+