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Diffstat (limited to '2004/n/fpga/src/pwm/tb_fsmpwm3.vhd')
-rw-r--r--2004/n/fpga/src/pwm/tb_fsmpwm3.vhd66
1 files changed, 0 insertions, 66 deletions
diff --git a/2004/n/fpga/src/pwm/tb_fsmpwm3.vhd b/2004/n/fpga/src/pwm/tb_fsmpwm3.vhd
deleted file mode 100644
index aec67ed..0000000
--- a/2004/n/fpga/src/pwm/tb_fsmpwm3.vhd
+++ /dev/null
@@ -1,66 +0,0 @@
---simulation pendant 41 ms
-
-library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.std_logic_arith.all;
- use IEEE.std_logic_unsigned.all;
-library work;
-library synopsys;
-use synopsys.bv_arithmetic.all;
---ENTITY
-entity tb_fsmpwm3 is
-end tb_fsmpwm3;
---ARCHITECTURE
-architecture sim1 of tb_fsmpwm3 is
- component fsmpwm3
- port(RST :in std_logic;
- CLK :in std_logic;
- CLK1USFSM :in std_logic;
- tcfsm :in integer;
-
- enloadfsm:out std_logic
- );
- end component;
--- declaration des signaux
-signal RST:std_logic;
-signal CLK:std_logic:='0';
-signal CLK1USFSM:std_logic:='0';
-signal tcfsm:integer:=0;
-
-signal enloadfsm: std_logic:='0';
-
---CONSTANT
-constant CLK1US_PERIOD :time:= 992 ns;
-constant tcmax :integer:= 20161; --pour le clk1us
-constant CLK_PERIOD :time := 32 ns ;
---MAP
- begin
- U1fsmpwm3 : fsmpwm3 port map (
- RST=>RST,CLK=>CLK,CLK1USFSM=>CLK1USFSM,tcfsm=>tcfsm,enloadfsm=>enloadfsm
- );
-
- rst<='1','0'after (CLK1US_PERIOD/3);
- clk<= not clk after (CLK_PERIOD/2);
- clk1usfsm<= not clk1usfsm after (CLK1US_PERIOD/2);
--- STIMULI
-
- process
- begin
- tcfsm<=tcmax;wait for (CLK1US_PERIOD);
- tcfsm<=10;wait for ((tcmax*(CLK1US_PERIOD))-(CLK1US_PERIOD));
- tcfsm<=0;wait for ((CLK1US_PERIOD));
- tcfsm<=tcmax;wait for (CLK1US_PERIOD);
- tcfsm<=10;wait for ((tcmax*(CLK1US_PERIOD))-(CLK1US_PERIOD));
- tcfsm<=0;wait for ((CLK1US_PERIOD));
-
- end process;
-end sim1;
-
---CONFIGURATION
-configuration cfg_tb_fsmpwm3 of tb_fsmpwm3 is
- for sim1
- --for U1fsmpwm3 : fsmpwm3 use entity work.fsmpwm3(BEHAV);
- for all: fsmpwm3 use entity work.fsmpwm3(BEHAV);
-end for;
-end for;
-end cfg_tb_fsmpwm3;