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-rw-r--r--2004/n/fpga/src/pwm/clk1us.vhd43
1 files changed, 24 insertions, 19 deletions
diff --git a/2004/n/fpga/src/pwm/clk1us.vhd b/2004/n/fpga/src/pwm/clk1us.vhd
index 082e4ec..3614b5a 100644
--- a/2004/n/fpga/src/pwm/clk1us.vhd
+++ b/2004/n/fpga/src/pwm/clk1us.vhd
@@ -4,44 +4,49 @@
--Auteur : Fidèle GAFAN
--Module générateur d'horloge 1us-périodique(0,992us en réalité)
--
---REMARQUE(S):changer inc si CLK#32MHz
+--REMARQUE(S):changer compt si CLK#32MHz
--Les calculs ont été faits avec CLK=32MHz
--donc 31*(1/CLK)=1us
---d'où inc=31
+--d'où compt=31
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
+
+use work.nono_const.all;
+use work.pwm_const.all;
+
--ENTITY
entity clk1us is
port (
RST : in std_logic;
- CLK : in std_logic; --32MHz
+ CLK : in std_logic; --40MHz
CLK1USOUT : out std_logic
);
end entity;
+
--ARCHITECTURE
-architecture clk1usbehav of clk1us is
-signal inc : integer range 0 to 31;-- nombres de cycles de clk necessaires
- --pour 1us decremente
+architecture RTL of clk1us is
+ -- nombres de cycles de clk necessaires pour 1us incrémente.
+ signal compt: T_OCTET;
begin
- process(RST,CLK)
- begin
+ process(RST,CLK)
+ begin
if (RST = '1') then
- CLK1USOUT<='0';
- inc<=31; --31,25 normalement
+ CLK1USOUT <= '0';
+ compt <= x"00";
elsif (CLK'event and CLK = '1') then
- inc<=((inc)-1);
- if (inc=30) then
- CLK1USOUT<='1';
+ compt <= compt + x"01";
+ if (compt = x"00") then -- 30
+ CLK1USOUT <= '1';
else
- CLK1USOUT<='0';
- if (inc=0) then
- inc<=30;
- end if;
+ CLK1USOUT <= '0';
+ if (compt = (PWM_NB_CYCLE_1US - x"01")) then
+ compt <= x"00"; -- 30
+ end if;
end if;
end if;
- end process;
-end clk1usbehav;
+ end process;
+end RTL;