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diff --git a/2004/n/fpga/src/pwm/clk1us.vhd b/2004/n/fpga/src/pwm/clk1us.vhd
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--- clk1us.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Fidèle GAFAN et Pierre-André Galmes
--- Module générateur d'horloge 1us-périodique.
---
--- REMARQUE(S): pour les constantes, se reporter à pwm_const.vhd
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-use work.nono_const.all;
-use work.pwm_const.all;
-
---ENTITY
-entity clk1us is
- port (
- RST : in std_logic;
- CLK : in std_logic; --40MHz
- CLK1USOUT : out std_logic
- );
-end entity;
-
---ARCHITECTURE
-architecture RTL of clk1us is
- -- nombres de cycles de clk necessaires pour 1us incrémente.
- signal compt: T_OCTET;
-begin
- process(RST,CLK)
- begin
- if (RST = '1') then
- CLK1USOUT <= '0';
- compt <= x"00";
- elsif (CLK'event and CLK = '1') then
- compt <= compt + x"01";
- if (compt = x"00") then -- 30
- CLK1USOUT <= '1';
- else
- CLK1USOUT <= '0';
- if (compt = (PWM_NB_CYCLE_1US - x"01")) then
- compt <= x"00"; -- 30
- end if;
- end if;
- end if;
- end process;
-end RTL;