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Diffstat (limited to '2004/n/fpga/src/portserie/txserie.vhd')
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd58
1 files changed, 32 insertions, 26 deletions
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
index df1ec41..cad7dda 100644
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -49,19 +49,19 @@ entity txserie is
busclk : in std_logic;
rw : in std_logic; -- read (0) / write (1)
bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0)
- masterck: in std_logic;
+ bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
+ masterck: in std_logic;
txout: out std_logic;
- minIRQ: out std_logic;
+ minIRQ: out std_logic
);
end txserie;
architecture rtl of txserie is
component registre
- generic(adr : integer);
+ generic(adr : T_ADDRESS);
port(
- bus_address: in unsigned((NB_BIT_ADRESS - 1) downto 0);
+ bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
bus_data: inout unsigned(7 downto 0);
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
@@ -74,8 +74,8 @@ end component;
component fifo
port(
- data_in: in std_logic_vector(7 downto 0);
- data_out: in std_logic_vector(7 downto 0);
+ data_in: in unsigned(7 downto 0);
+ data_out: in unsigned(7 downto 0);
ck_in: in std_logic;
ck_out: in std_logic;
f0: out std_logic;
@@ -88,7 +88,7 @@ end component;
component transmitter
port(
- data_in: in std_logic_vector(7 downto 0);
+ data_in: in unsigned(7 downto 0);
ck: in std_logic;
flag: out std_logic;
txout: out std_logic
@@ -104,9 +104,9 @@ component clockgene
end component;
component decoder
- generic(adr : integer);
+ generic(adr : unsigned);
port(
- bus_address: in std_logic_vector((NB_BIT_ADRESS - 1) downto 0);
+ bus_address: in unsigned((NB_BIT_ADDRESS - 1) downto 0);
cs: out std_logic
);
end component;
@@ -122,27 +122,31 @@ signal purge: std_logic;
signal geneck: std_logic;
signal txck: std_logic;
signal busck: std_logic;
-signal bus_address: std_logic_vector((NB_BIT_ADRESS - 1) downto 0);
-signal bus_data: std_logic_vector(7 downto 0);
-signal rw: std_logic;
-signal rst: std_logic;
-signal txdata: std_logic;
+--signal bus_address: std_logic_vector((NB_BIT_ADDRESS - 1) downto 0);
+--signal bus_data: std_logic_vector(7 downto 0);
+--signal rw: std_logic;
+--signal rst: std_logic;
+signal confreg: std_logic_vector(7 downto 0);
+signal flagreg: std_logic_vector(7 downto 0);
+signal datareg: std_logic_vector(7 downto 0);
+signal inter_data: unsigned(7 downto 0);
signal txempty: std_logic;
signal csFifo: std_logic;
signal fifockin: std_logic;
signal fifockout: std_logic;
+begin
FIFO1: fifo
port map(
data_in=>bus_data,
- data_out=>txdata,
+ data_out=>inter_data,
ck_in=>fifockin,
- ck_out=>fifockout
+ ck_out=>fifockout,
f0=>fifoEmpty,
f1=>fifoLI0,
f2=>fifoLI1,
f3=>fifoFull,
- purge=>confreg(3)
+ purge=>'1' --confreg(3 downto 3)
);
fifockin<=csFifo and not rw and busck;
@@ -151,24 +155,25 @@ fifockout<=txempty; -- à vérifier !!! Cette ligne est valable pour
TX1 : transmitter
port map(
- data_in=>txdata,
+ data_in=>inter_data,
ck=>txck,
flag=>txempty,
- txout=>txout,
+ txout=>txout
);
CLOCK1 : clockgene
port map(
ck_in=>geneck,
ck_out=>txck,
- param=>confreg(1 downto 0)
+ param=>"11" --confreg(1 downto 0)
);
-geneck<=confreg(4) and masterck; -- On/Off et masterck
+
+geneck<='1'; --confreg(4) and masterck; -- On/Off et masterck
-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
RCONF : registre
- generic map(adr=>adr+1)
+ generic map(adr=>A_DATA)
port map(
bus_address=>bus_address,
bus_data=>bus_data,
@@ -182,7 +187,7 @@ RCONF : registre
-- Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0)
RFLAG : registre
- generic map(adr=>adr+2)
+ generic map(adr=>A_FLAG)
port map(
bus_address=>bus_address,
bus_data=>bus_data,
@@ -202,10 +207,10 @@ flagreg(0)<=fifoLI0;
-- la sortie intout est active si la pile est pleine ET si le bit de conf est
-- activé
-intout<=fifoFull and confreg(2); -- IntEn et fifoFull
+minIRQ<=fifoFull and confreg(2); -- IntEn et fifoFull
DECOD : decoder
- generic map(adr=>adr)
+ generic map(adr=>A_DATA)
port map(
bus_address=>bus_address,
cs=>csFifo
@@ -213,3 +218,4 @@ DECOD : decoder
end rtl;
+