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+-- txserie.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+
+-- -------------------------------------------
+-- Port série TX pour le fpga robot
+-- -------------------------------------------
+--
+-- * Prend 3 adresses mémoire :
+-- 0 - Txdata
+-- 1 - Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0)
+-- 2 - Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
+-- * Mettre le bit On/Off à 1 pour activer la transmission
+-- * Chaque écriture dans txdata charge la donnée dans la fifo
+-- * Dès que le registre à décalage est vide, il enlève le dernier élément de
+-- la fifo et le transmet
+-- * Deux bits de stop
+-- * Quand la fifo est pleine, met le flag Full/Int à 1 et génère une
+-- interruption. Il faut alors mettre à 0 le bit IntEn, qui sera remis à 1 à
+-- la prochaine écriture dans la fifo
+-- * On peut lire l'état de la pile dans le registre de flags
+-- * On peut vider la pile en mettant Purge à 1
+-- * Baudrate disponible :
+-- BdR1/0 ! Baudrate
+-- 00 ! 9600
+-- 01 ! 19200
+-- 10 ! 57600
+-- 11 ! 115200
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+entity txserie is
+ generic (
+ -- adresses des différents registres du module.
+ A_DATA : T_ADDRESS ;
+ A_CONFIG : T_ADDRESS ;
+ A_FLAG : T_ADDRESS
+ -- si autre choses à déclarer...
+ );
+ port (
+ rst : in std_logic;
+ busclk : in std_logic;
+ rw : in std_logic; -- read (0) / write (1)
+ bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
+ bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0)
+ masterck: in std_logic;
+ txout: out std_logic;
+ minIRQ: out std_logic;
+ );
+end txserie;
+
+architecture rtl of txserie is
+
+component registre
+ generic(adr : integer);
+ port(
+ bus_address: in unsigned((NB_BIT_ADRESS - 1) downto 0);
+ bus_data: inout unsigned(7 downto 0);
+ input: in std_logic_vector(7 downto 0);
+ output: out std_logic_vector(7 downto 0);
+ rw: in std_logic;
+ load: in std_logic;
+ ck: in std_logic;
+ rst: in std_logic
+ );
+end component;
+
+component fifo
+ port(
+ data_in: in std_logic_vector(7 downto 0);
+ data_out: in std_logic_vector(7 downto 0);
+ ck_in: in std_logic;
+ ck_out: in std_logic;
+ f0: out std_logic;
+ f1: out std_logic;
+ f2: out std_logic;
+ f3: out std_logic;
+ purge: in std_logic
+ );
+end component;
+
+component transmitter
+ port(
+ data_in: in std_logic_vector(7 downto 0);
+ ck: in std_logic;
+ flag: out std_logic;
+ txout: out std_logic
+ );
+end component;
+
+component clockgene
+ port(
+ ck_in: in std_logic;
+ ck_out: in std_logic;
+ param: in std_logic_vector(1 downto 0)
+ );
+end component;
+
+component decoder
+ generic(adr : integer);
+ port(
+ bus_address: in std_logic_vector((NB_BIT_ADRESS - 1) downto 0);
+ cs: out std_logic
+ );
+end component;
+
+
+signal fifoEmpty: std_logic;
+signal fifoFull: std_logic;
+signal fifoLI1: std_logic;
+signal fifoLI0: std_logic;
+signal BdR1: std_logic;
+signal BdR0: std_logic;
+signal purge: std_logic;
+signal geneck: std_logic;
+signal txck: std_logic;
+signal busck: std_logic;
+signal bus_address: std_logic_vector((NB_BIT_ADRESS - 1) downto 0);
+signal bus_data: std_logic_vector(7 downto 0);
+signal rw: std_logic;
+signal rst: std_logic;
+signal txdata: std_logic;
+signal txempty: std_logic;
+signal csFifo: std_logic;
+signal fifockin: std_logic;
+signal fifockout: std_logic;
+
+FIFO1: fifo
+ port map(
+ data_in=>bus_data,
+ data_out=>txdata,
+ ck_in=>fifockin,
+ ck_out=>fifockout
+ f0=>fifoEmpty,
+ f1=>fifoLI0,
+ f2=>fifoLI1,
+ f3=>fifoFull,
+ purge=>confreg(3)
+ );
+
+fifockin<=csFifo and not rw and busck;
+fifockout<=txempty; -- à vérifier !!! Cette ligne est valable pour
+ -- txempty=1 quand le tx est vide
+
+TX1 : transmitter
+ port map(
+ data_in=>txdata,
+ ck=>txck,
+ flag=>txempty,
+ txout=>txout,
+ );
+
+CLOCK1 : clockgene
+ port map(
+ ck_in=>geneck,
+ ck_out=>txck,
+ param=>confreg(1 downto 0)
+ );
+geneck<=confreg(4) and masterck; -- On/Off et masterck
+
+
+-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
+RCONF : registre
+ generic map(adr=>adr+1)
+ port map(
+ bus_address=>bus_address,
+ bus_data=>bus_data,
+ input=>(others => '0'),
+ output=>confreg,
+ rw=>rw,
+ load=>'0',
+ ck=>busck,
+ rst=>'0'
+ );
+
+-- Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0)
+RFLAG : registre
+ generic map(adr=>adr+2)
+ port map(
+ bus_address=>bus_address,
+ bus_data=>bus_data,
+ input=>flagreg,
+ output=>open,
+ rw=>rw,
+ load=>'1',
+ ck=>busck,
+ rst=>'0'
+ );
+
+flagreg(7 downto 3)<=(others => '0');
+flagreg(3)<=txempty;
+flagreg(2)<=fifoFull;
+flagreg(1)<=fifoLI1;
+flagreg(0)<=fifoLI0;
+
+-- la sortie intout est active si la pile est pleine ET si le bit de conf est
+-- activé
+intout<=fifoFull and confreg(2); -- IntEn et fifoFull
+
+DECOD : decoder
+ generic map(adr=>adr)
+ port map(
+ bus_address=>bus_address,
+ cs=>csFifo
+ );
+end rtl;
+
+