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Diffstat (limited to '2004/n/fpga/src/portserie/txserie.vhd')
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd41
1 files changed, 17 insertions, 24 deletions
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
index 5995f9c..997a60d 100644
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -46,10 +46,11 @@ entity txserie is
);
port (
rst : in std_logic;
- busclk : in std_logic;
+ clk : in std_logic;
rw : in std_logic; -- read (0) / write (1)
- bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
+ bus_data : inout T_DATA;
+ bus_address : in T_ADDRESS
+
masterck: in std_logic;
txout: out std_logic;
minIRQ: out std_logic
@@ -61,10 +62,10 @@ architecture rtl of txserie is
component registre
generic(adr : T_ADDRESS);
port(
- bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
- bus_data: inout unsigned(7 downto 0);
- input: in std_logic_vector(7 downto 0);
- output: out std_logic_vector(7 downto 0);
+ bus_address: in T_ADDRESS;
+ bus_data: inout T_DATA;
+ input: in T_DATA;
+ output: out T_DATA;
rw: in std_logic;
load: in std_logic;
ck: in std_logic;
@@ -75,8 +76,8 @@ end component;
component fifo is
port(
- data_in: in unsigned(7 downto 0);
- data_out: out unsigned(7 downto 0);
+ data_in: in T_DATA;
+ data_out: out T_DATA;
ck: in std_logic;
ck_in: in std_logic;
ck_out: in std_logic;
@@ -88,7 +89,7 @@ end component;
component transmitter
port(
- data_in: in unsigned(7 downto 0);
+ data_in: in T_DATA;
ck: in std_logic;
flag: out std_logic;
txout: out std_logic
@@ -106,7 +107,7 @@ end component;
component decoder
generic(adr : unsigned);
port(
- bus_address: in unsigned((NB_BIT_ADDRESS - 1) downto 0);
+ bus_address: in T_DATA;
cs: out std_logic
);
end component;
@@ -122,15 +123,11 @@ signal purge: std_logic;
signal geneck: std_logic;
signal txck: std_logic;
signal busck: std_logic;
---signal bus_address: std_logic_vector((NB_BIT_ADDRESS - 1) downto 0);
---signal bus_data: std_logic_vector(7 downto 0);
---signal rw: std_logic;
---signal rst: std_logic;
-signal confreg: unsigned(7 downto 0);
-signal flagreg: unsigned(7 downto 0);
+signal confreg: T_DATA;
+signal flagreg: T_DATA;
signal interflag: std_logic_vector(5 downto 0);
-signal datareg: unsigned(7 downto 0);
-signal inter_data: unsigned(7 downto 0);
+signal datareg: T_DATA;
+signal inter_data: T_DATA;
signal txempty: std_logic;
signal csFifo: std_logic;
signal fifockin: std_logic;
@@ -148,7 +145,7 @@ FIFO1: fifo
purge=>confreg(3)
);
-flagreg(5 downto 0)<=conv_unsigned(CONV_INTEGER(interflag),8);
+flagreg(5 downto 0)<=interflag;
fifockin<=csFifo and not rw and busck;
fifockout<=txempty; -- ŕ vérifier !!! Cette ligne est valable pour
@@ -219,7 +216,3 @@ DECOD : decoder
end rtl;
-
-
-
-