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Diffstat (limited to '2004/n/fpga/src/portserie/rxserie/sfifo.xco')
-rw-r--r--2004/n/fpga/src/portserie/rxserie/sfifo.xco9
1 files changed, 4 insertions, 5 deletions
diff --git a/2004/n/fpga/src/portserie/rxserie/sfifo.xco b/2004/n/fpga/src/portserie/rxserie/sfifo.xco
index afcd6a7..61a5042 100644
--- a/2004/n/fpga/src/portserie/rxserie/sfifo.xco
+++ b/2004/n/fpga/src/portserie/rxserie/sfifo.xco
@@ -25,18 +25,17 @@ SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
CSET data_width = 8
-CSET read_error_sense = active_high
+CSET read_error_sense = Active_Low
CSET read_error_flag = true
CSET write_acknowledge_flag = true
CSET write_error_flag = true
CSET data_count = true
CSET memory_type = Distributed_Memory
-CSET read_acknowledge_sense = active_high
+CSET read_acknowledge_sense = Active_Low
CSET component_name = sfifo
CSET fifo_depth = 16
CSET read_acknowledge_flag = true
CSET data_count_width = 2
-CSET write_error_sense = active_high
-CSET write_acknowledge_sense = active_high
+CSET write_error_sense = Active_Low
+CSET write_acknowledge_sense = Active_Low
GENERATE
-