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Diffstat (limited to '2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd')
-rw-r--r--2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd24
1 files changed, 14 insertions, 10 deletions
diff --git a/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
index ec71a5c..b575b9d 100644
--- a/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
+++ b/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
@@ -20,14 +20,15 @@ use work.isa_const.all;
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA;
clk: in std_logic;
+ clk_ref: in std_logic;
rxin: in std_logic;
irqFIFO: out std_logic;
irqRX: out std_logic;
+ irqERR: out std_logic;
csData : in std_logic;
csConfig : in std_logic;
csFlag : in std_logic);
END COMPONENT;
-
signal rst: std_logic;
@@ -36,9 +37,11 @@ signal rw: std_logic;
signal bus_data: T_DATA;
signal data_received: T_DATA;
signal clk: std_logic:='0';
+signal clk_ref: std_logic:='0';
signal rxin: std_logic:='1';
signal irqFIFO: std_logic;
signal irqRX: std_logic;
+signal irqERR: std_logic;
signal csData: std_logic;
signal csConfig: std_logic;
signal csFlag: std_logic;
@@ -47,34 +50,35 @@ signal csFlag: std_logic;
BEGIN
- Inst_rxserie: rxserie PORT MAP(
+ uut: rxserie PORT MAP(
rst => rst,
bus_clk => bus_clk,
rw => rw,
bus_data => bus_data,
clk => clk,
+ clk_ref => clk_ref,
rxin => rxin,
irqFIFO => irqFIFO,
irqRX => irqRX,
+ irqERR => irqERR,
csData => csData,
csConfig => csConfig,
csFlag => csFlag
);
--- baudrate/(16*2) used to generate half clock cycle;
+-- master clock
clk <= (Not clk) after (CK_PERIOD/2);
-- Reset Uart
rst <= '1','0' after (10*CK_PERIOD);
--- feeding back output from transmitter to the input of receiver
-rxin <= not rxin after 12 us;
+-- baudrate/(16*2) used to generate half clock cycle;
+clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz
+-- feeding back output from transmitter to the input of receiver
+rxin <= not rxin after 15751 ns;
--- csData => csData,
--- csConfig => csConfig,
--- csFlag => csFlag
check:process
@@ -124,12 +128,12 @@ begin
csData<='1';
read_bus;
- WAIT FOR 10 us;
+ WAIT FOR 100 us;
csFlag<='1';
read_bus;
- WAIT FOR 10 us;
+ WAIT FOR 100 us;
end process;
END;