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Diffstat (limited to '2004/n/fpga/src/portserie/portserie')
-rw-r--r--2004/n/fpga/src/portserie/portserie/bch_txserie.vhd12
-rw-r--r--2004/n/fpga/src/portserie/portserie/portserie.npl2
-rw-r--r--2004/n/fpga/src/portserie/portserie/sfifo.xco5
-rw-r--r--2004/n/fpga/src/portserie/portserie/txserie.vhd21
4 files changed, 27 insertions, 13 deletions
diff --git a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
index 3400854..25fadff 100644
--- a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
+++ b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
@@ -22,6 +22,7 @@ component txserie
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA:=(others => 'Z');
clk: in std_logic;
+ clk_ref: in std_logic;
txout: out std_logic;
minIRQ: out std_logic;
csData : in std_logic;
@@ -35,6 +36,7 @@ end component;
signal simclk:std_logic:='0';
signal rst : std_logic;
signal clk : std_logic;
+signal clk_ref : std_logic:='0';
signal rw : std_logic;
signal bus_data : T_DATA:=(others => 'Z');
signal masterck: std_logic:='0';
@@ -44,18 +46,19 @@ signal csData : std_logic;
signal csConfig : std_logic;
signal csFlag : std_logic;
-signal state:integer:=-3;
+signal state:integer:=-30;
begin
- U1 : txserie
+ UUT : txserie
port map(
rst => rst,
bus_clk => clk,
rw =>rw,
bus_data => bus_data,
clk => masterck,
+ clk_ref => clk_ref,
txout => txout,
minIRQ => minirq,
csData => csData,
@@ -66,6 +69,7 @@ begin
rst<='1','0' after 5 ns;
simclk<= not simclk after 10 ns;
masterck<= not masterck after 3 ns;
+ clk_ref <= not clk_ref after 10 ns;
combi:process(state)
begin
@@ -77,10 +81,10 @@ begin
csFlag <= '0';
case state is
- when 1 => bus_data<="00010110";
+ when 1 => bus_data<="01110111";
csConfig<='1';
rw<='0';
- when 2 => bus_data<="00010110";
+ when 2 => bus_data<="01110111";
csConfig<='1';
rw<='0';
clk<='1';
diff --git a/2004/n/fpga/src/portserie/portserie/portserie.npl b/2004/n/fpga/src/portserie/portserie/portserie.npl
index 1743fbf..b293bd4 100644
--- a/2004/n/fpga/src/portserie/portserie/portserie.npl
+++ b/2004/n/fpga/src/portserie/portserie/portserie.npl
@@ -30,7 +30,9 @@ SOURCE ..\fifo\sfifo.xco
STIMULUS bch_txmit.vhd
STIMULUS ..\fifo\bch_fifodriver.vhd
SOURCE ..\clockgene\clockgene.vhd
+STIMULUS bch_clockgene.vhd
[Normal]
+p_CompxlibOutputDir=xstvhd, spartan2, Design.t_compLibraries, 1079779592, D:\xilinx\vhdl\src
p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1078871494, ModelSim SE
[STRATEGY-LIST]
Normal=True
diff --git a/2004/n/fpga/src/portserie/portserie/sfifo.xco b/2004/n/fpga/src/portserie/portserie/sfifo.xco
index a2badbd..cc7276e 100644
--- a/2004/n/fpga/src/portserie/portserie/sfifo.xco
+++ b/2004/n/fpga/src/portserie/portserie/sfifo.xco
@@ -18,11 +18,12 @@
# Number of HU_SETs used: 0
#
SET BusFormat = BusFormatAngleBracketNotRipped
+SET SimulationOutputProducts = VHDL
SET XilinxFamily = Spartan2
-SET OutputOption = OutputProducts
+SET OutputOption = DesignFlow
+SET DesignFlow = VHDL
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
-SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
CSET data_width = 8
CSET read_error_sense = Active_Low
diff --git a/2004/n/fpga/src/portserie/portserie/txserie.vhd b/2004/n/fpga/src/portserie/portserie/txserie.vhd
index b1ceb53..2b94529 100644
--- a/2004/n/fpga/src/portserie/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/portserie/txserie.vhd
@@ -46,6 +46,7 @@ entity txserie is
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA:=(others => 'Z');
clk: in std_logic;
+ clk_ref: in std_logic;
txout: out std_logic;
minIRQ: out std_logic;
csData : in std_logic;
@@ -115,16 +116,15 @@ signal txck: std_logic;
signal geneck:std_logic;
signal txload: std_logic:='0';
-signal loadingtx: std_logic:='0';
signal confreg: T_DATA:="00000000";
signal flagreg: T_DATA:="00000000";
signal inter_data: T_DATA;
-signal inter_fifo_bus: T_DATA;
+--signal inter_fifo_bus: T_DATA;
signal txready: std_logic:='1';
signal fifodready :std_logic;
-signal state:integer:=1;
-signal state_next:integer:=1;
+--signal state:integer:=1;
+--signal state_next:integer:=1;
signal state_txload:integer:=0;
signal dummy : T_DATA :=(others =>'0');
@@ -135,7 +135,7 @@ signal un: std_logic :='1';
begin
CLOCK1 : clockgene port map(
rst => rst,
- ckin=>geneck,
+ ckin=>clk_ref,--geneck,
ckout=>txck,
param=>confreg(1 downto 0));
@@ -185,7 +185,7 @@ RFLAG : regIO port map(
-- signaux
-- config
-geneck <= (confreg(4) and clk); -- On/Off et masterck
+geneck <= (clk_ref);-- and confreg(4); -- On/Off et masterck
fifopurge <= '1' when (rst='1') else confreg(3); -- reset or purge
-- flags
@@ -208,22 +208,29 @@ begin
state_txload <= 3;
elsif(fifodready='1') then
state_txload <= 1;
+ else
+ state_txload <= 0;
end if;
when 1 => if(txready='1') then
state_txload <= 2;
txload <= '1';
+ else
+ state_txload <= 1;
end if;
when 2 => if(txready='0') then
state_txload <= 0;
else
txload <= '1';
+ state_txload <= 2;
end if;
when 3 => if(fifodready='1') then
state_txload <= 2;
txload <= '1';
+ else
+ state_txload <= 3;
end if;
- when others => null;
+ when others => state_txload <= 0;
end case;
end process;