summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/portserie/modele.vhd
diff options
context:
space:
mode:
Diffstat (limited to '2004/n/fpga/src/portserie/modele.vhd')
-rw-r--r--2004/n/fpga/src/portserie/modele.vhd40
1 files changed, 2 insertions, 38 deletions
diff --git a/2004/n/fpga/src/portserie/modele.vhd b/2004/n/fpga/src/portserie/modele.vhd
index 6a01686..a9f700b 100644
--- a/2004/n/fpga/src/portserie/modele.vhd
+++ b/2004/n/fpga/src/portserie/modele.vhd
@@ -1,15 +1,3 @@
--- modele.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Fichier modèle pour la déclaration de module.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
entity modele is
generic (
-- adresses des différents registres du module.
@@ -21,31 +9,7 @@ entity modele is
port (
rst : in std_logic;
clk : in std_logic;
- -- XXX : savoir si read = 0 ou 1 !!
rw : in std_logic; -- read (0) / write (1)
- bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0)
- masterck : in std_logic;
-
- );
-end entity;
+ bus_data : inout T_DATA;
+ bus_address : in T_ADDRESS
-architecture test_modele of modele is
-begin
- process (rst, clk)
- begin
- if (rst = '1') then
- bus_data <= x"00";
- elsif (clk'event and clk = '1') then
- if (bus_address = A_REG1) then
- bus_data <= x"01";
- else
- if (bus_address = A_REG2) then
- bus_data <= x"02";
- elsif (bus_address = A_REG3) then
- bus_data <= x"03";
- end if;
- end if;
- end if;
- end process;
-end test_modele;