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Diffstat (limited to '2004/n/fpga/src/portserie/fifodriver.vhd')
-rw-r--r--2004/n/fpga/src/portserie/fifodriver.vhd83
1 files changed, 47 insertions, 36 deletions
diff --git a/2004/n/fpga/src/portserie/fifodriver.vhd b/2004/n/fpga/src/portserie/fifodriver.vhd
index 15ab56c..9084d51 100644
--- a/2004/n/fpga/src/portserie/fifodriver.vhd
+++ b/2004/n/fpga/src/portserie/fifodriver.vhd
@@ -21,55 +21,64 @@ entity fifodriver is
constant PRESCAL :integer:= 1;
end fifodriver;
+-- arch
architecture rtl of fifodriver is
-signal subck: integer :=0;
-signal state_actual,state_next : integer;
+signal clock:std_logic;
+signal writeflag,readflag :std_logic;
+signal subck : integer :=0;
begin
--- la partie COMBI
- COMBI:process(state_actual,readreq,writereq)
- begin
- fifowrite <= '0';
- fiforead <= '0';
- fifock <= '0';
- state_next <= 1;
-
- case state_actual is
- when 1 => if (readreq='1') then
- state_next <= 2;
- elsif(writereq='1') then
- state_next <= 4;
- end if;
-
- when 2 => state_next <= 3;
- fiforead<='1';
+ fifock<=clock;
- when 3 => state_next <= 1;
- fiforead<='1';
- fifock<='1';
+-- process(writereq)
+-- begin
+-- if (writereq'event and writereq='1') then
+-- writeflag<='1';
+-- end if;
+-- end process;
+--
+-- process(readreq)
+-- begin
+-- if (readreq'event and readreq='1') then
+-- readflag<='1';
+-- end if;
+-- end process;
- when 4 => state_next <= 5;
- fifowrite<='1';
+ process(clock,writereq,readreq)
+ begin
+ if (writereq'event and writereq='1') then
+ writeflag<='1';
+ end if;
- when 5 => state_next <= 1;
- fifowrite<='1';
- fifock<='1';
+ if (readreq'event and readreq='1') then
+ readflag<='1';
+ end if;
- when others => NULL;
- end case;
- end process COMBI;
+ -- sur front descendant de fifock, on met fifowrite et fiforead à
+ -- jour
+ if(clock'event and clock='0') then
+ if(readflag='1') then
+ readflag<='0';
+ fiforead<='1';
+ end if;
+
+ if(writeflag='1') then
+ writeflag<='0';
+ fifowrite<='1';
+ end if;
+ end if;
+ end process;
--- la partie SEQU
- SEQU:process(masterck,reset)
+-- la partie SEQU : divise la fréquence d'horloge
+ SEQU:process(masterck)
begin
- if (reset='1') then
- state_actual <= 1;
- elsif (masterck'event and masterck='1') then
+ if (masterck'event and masterck='1') then
if(subck=PRESCAL) then
subck<=0;
- state_actual <= state_next ;
+ clock<='1';
else
subck<=subck+1;
+ clock<='0';
end if;
end if;
end process SEQU;
@@ -77,3 +86,5 @@ end rtl;
+
+